badline 0.11.0 → 0.11.1

data/lib/badline/drive/core.rb

@@ -0,0 +1,172 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drive
+    # What every Commodore disk drive here shares: a 6502 running the DOS
+    # ROM with two VIAs on its bus, VIA 1 facing the serial bus and VIA 2
+    # the disk mechanism, on a clock of its own.
+    #
+    # The drive runs on its own crystal, so it clocks against the host's
+    # clock through a fractional accumulator: each host cycle adds the
+    # drive's clock rate worth of phase, and every whole host period in it
+    # runs a drive cycle. Against the PAL C64's 985,248 Hz a drive at
+    # 1 MHz runs one drive cycle per host cycle and a second one about
+    # every 67. The host sets its clock on attaching the drive, and until
+    # then a 1 MHz drive runs one cycle per host cycle.
+    #
+    # VIA 2's port B runs the Mechanism, which reads a Disk put in with
+    # insert.
+    #
+    # While the DOS idles, host_cycle! skips the drive's cycles and catches
+    # up on them later, exactly (see Idle). The readers of the drive's parts
+    # catch up first, so they find the drive as running every cycle would
+    # have left it. Once the DOS's timer interrupts come round, the drive
+    # sleeps through them too (see Orbit).
+    #
+    # A model includes Core and builds its parts, sets @clock_hz and
+    # @idle_loop, and runs one drive cycle in step.
+    module Core
+      include Sleep
+      include Idle
+      include Orbit
+
+      attr_reader :device, :serial_bus
+
+      def cpu
+        settle!
+        @cpu
+      end
+
+      def bus
+        settle!
+        @bus
+      end
+
+      def via1
+        settle!
+        @via1
+      end
+
+      def via2
+        settle!
+        @via2
+      end
+
+      def mechanism
+        settle!
+        @mechanism
+      end
+
+      def cycles
+        settle!
+        @cycles
+      end
+
+      def ram = bus.ram
+
+      def host_clock_hz=(clock_hz)
+        settle!
+        @host_clock_hz = clock_hz
+      end
+
+      # Plugs the drive into a serial bus, leaving the one it was on. A drive
+      # starts out on a bus of its own, with nothing else on it.
+      def connect(serial_bus)
+        settle!
+        @serial_bus&.detach(self)
+        @serial_bus = serial_bus
+        @serial_port.bus = serial_bus
+        serial_bus.attach(self)
+        @via1.ca1 = @serial_port.atn_low?
+      end
+
+      # Puts a Disk in the drive (Disk.from_d64 makes one from an image).
+      # Nil takes the disk out.
+      def insert(disk)
+        settle!
+        @mechanism.insert(disk)
+      end
+
+      def disk = mechanism.disk
+
+      # Whether the LED is lit. Reading it leaves the drive asleep: the LED
+      # is the same at the end of every pass the drive sleeps through.
+      def led_on? = @mechanism.led_on?
+
+      # VIA 1's port B as it drives the serial bus. It holds still while the
+      # drive sleeps, so reading it leaves the drive asleep.
+      def serial_output = @via1.port_b_output
+
+      # Stores what the head wrote since the motor last stopped in the
+      # disk's image, as the motor stopping does.
+      def flush
+        settle!
+        @mechanism.flush
+      end
+
+      # The serial bus's RESET line reaches the CPU and both VIAs. RAM keeps
+      # its contents.
+      def reset!
+        settle!
+        @via1.reset!
+        @via2.reset!
+        @cpu.reset!
+      end
+
+      # Runs the drive cycles that fall in one host cycle: none, one or two.
+      # The host has run this cycle already, and the drive sees what it did
+      # from the next one on (see SerialPort). Asleep, the drive owes the
+      # cycles instead, until ATN moves or its counters are due (see Idle).
+      # It looks at ATN only after the machine pushed its lines into the bus
+      # (see host_written!).
+      def host_cycle!
+        if @asleep
+          return if (@slept += 1) != @wake_at && @host_still
+
+          return doze
+        end
+
+        phase = @phase + @clock_hz
+        while phase >= @host_clock_hz
+          @asleep ? @owed += 1 : run_cycle
+          phase -= @host_clock_hz
+        end
+        @phase = phase
+        settle! if @serial_port.atn_moved?
+        @serial_port.latch_host
+        plan_wake if @asleep
+      end
+
+      # The machine pushed its lines into the bus, so ATN may have moved.
+      def host_written!
+        @host_still = false
+      end
+
+      # The host moved its fast serial pins, which a 1541 has none to hear.
+      def fast_lines_moved = nil
+
+      # Runs one drive cycle, catching up first on any the drive owes (see
+      # step).
+      def cycle!
+        settle!
+        step
+      end
+
+      def inspect
+        "#<#{self.class.name} cycles=#{cycles} cpu=(#{cpu.inspect})>"
+      end
+
+      private
+
+      # Runs the model's chips beyond the VIAs +cycles+ quiet cycles at once
+      # (see quiet_cycles). The 1541 has none.
+      def fast_forward_chips(_cycles) = nil
+
+      # A drive cycle from host_cycle!, which may find the idle loop.
+      def run_cycle
+        step
+        idle_loop_reached if @cpu.program_counter == @idle_loop && @idle_skip
+      end
+    end
+  end
+end

data/lib/badline/{drive1541 → drive}/idle.rb

@@ -1,18 +1,19 @@
 # frozen_string_literal: true
 
 module Badline
-  class Drive1541
+  module Drive
     # Skipping the drive's cycles while the DOS idles, exactly.
     #
-    # With nothing to do, the DOS goes round its idle loop from $EBFF,
-    # 446 cycles a pass, until VIA 2's timer 1 interrupts it every 14,850
-    # cycles for the job loop, or ATN interrupts it through VIA 1's CA1. A
-    # pass writes RAM and VIA 2's port B, but puts back what it found, so
-    # the drive comes round to $EBFF as it left it. Only the timers'
-    # counters and the cycle counts move.
+    # With nothing to do, the DOS goes round its idle loop from the
+    # model's @idle_loop ($EBFF in the 1541, 446 cycles a pass), until VIA
+    # 2's timer 1 interrupts it every 14,850 cycles for the job loop, or
+    # ATN interrupts it through VIA 1's CA1. A pass writes RAM and VIA 2's
+    # port B, but puts back what it found, so the drive comes round to the
+    # loop's start as it left it. Only the timers' counters and the cycle
+    # counts move.
     #
-    # Each time the CPU comes to $EBFF, the drive records the pass that
-    # follows. At the next $EBFF it checks that the pass
+    # Each time the CPU comes to the loop's start, the drive records the
+    # pass that follows. At the next it checks that the pass
     #
     # - left the CPU, both VIAs but for their counters, the bus's last
     #   byte, the SO pin, the mechanism (Mechanism#idle_state) and what
@@ -30,7 +31,7 @@ module Badline
     # sleeps: host_cycle! only counts the host cycles that go by (see
     # Sleep). It wakes
     # when ATN moves, when a counter is due to set a flag, or when something
-    # outside reads or changes the drive (the readers in Drive1541 call
+    # outside reads or changes the drive (the readers in Core call
     # settle!). Waking counts off the whole passes it owes in bulk,
     # moving the counters on, and runs the rest cycle by cycle.
     #
@@ -39,16 +40,13 @@ module Badline
     # own lines hold still while it sleeps, so the C64 reads them without
     # waking it (serial_output).
     #
-    # A pass starts at $EBFF, where the CPU always comes from the loop's
-    # last instruction, a JMP, so what that leaves in the CPU's working
-    # registers is the same each time round.
+    # A pass starts at the loop's start, where the CPU always comes from
+    # the loop's last instruction, a JMP, so what that leaves in the CPU's
+    # working registers is the same each time round.
     #
     # The timer's interrupts come round too, and once they do, the drive
     # sleeps on through them (see Orbit).
     module Idle
-      # Where the DOS 2.6 idle loop starts over.
-      IDLE_LOOP = 0xebff
-
       # Whether the drive may sleep through its idle loop. On by default,
       # but for a drive whose CPU logs each instruction.
       attr_reader :idle_skip
@@ -69,8 +67,9 @@ module Badline
         init_orbits
       end
 
-      # The CPU is at $EBFF. At an instruction boundary, the drive sleeps if
-      # the pass it recorded can repeat, and otherwise records the next.
+      # The CPU is at the loop's start. At an instruction boundary, the
+      # drive sleeps if the pass it recorded can repeat, and otherwise
+      # records the next.
       def idle_loop_reached
         return unless @cpu.boundary?
 
@@ -128,7 +127,7 @@ module Badline
 
       def idle_state
         mechanism = @mechanism
-        [*@cpu.idle_state, *@via1.idle_state, *@via2.idle_state, @bus.data, @so_pending,
+        [*@cpu.idle_state, *@via1.idle_state, *@via2.idle_state, @bus.data, mechanism.so_pending,
          *mechanism.idle_state, mechanism.read_a(0xff), mechanism.read_b(0xff)]
       end
     end

data/lib/badline/drive/idle_cpu.rb

@@ -0,0 +1,28 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drive
+    # What Idle needs of a drive's 6502, which includes it beside
+    # CPU::Core.
+    module IdleCPU
+      # Everything the CPU holds but its cycle and instruction counts: the
+      # registers, the interrupt lines and pipeline, and what the last
+      # instruction left in its working registers. Drive::Idle compares
+      # it at two instruction boundaries.
+      def idle_state
+        [@program_counter, @stack_pointer, @a, @x, @y, @status.value,
+         @irq, @nmi, @irq_sample, @irq_pending, @nmi_sample, @nmi_pending, @skip_poll,
+         @boundary_irq, @boundary_nmi, @so_high, @interrupt, @brk, @pending_write, @stalled_at, @traps,
+         @operation, @optional_dummy, @boundary_crossed, @branch_taken,
+         @address, @pointer, @dummy_address, @value, @rmw_result]
+      end
+
+      # Counts +cycles+ cycles and +instructions+ instructions that ran
+      # without changing anything idle_state holds.
+      def fast_forward(cycles, instructions)
+        @cycles += cycles
+        @instructions += instructions
+      end
+    end
+  end
+end

data/lib/badline/{drive1541 → drive}/orbit.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 module Badline
-  class Drive1541
+  module Drive
     # Sleeping through the DOS's timer interrupts, exactly, once they come
     # round.
     #
@@ -65,6 +65,7 @@ module Badline
         @cpu.fast_forward(cycles, orbits * @orbit_instructions)
         @via1.skip_orbits(cycles, touched & 0x03)
         @via2.skip_orbits(cycles, touched >> 2)
+        fast_forward_chips(cycles)
         @cycles += cycles
         cycles
       end

data/lib/badline/drive/serial_lines.rb

@@ -0,0 +1,73 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drive
+    # What VIA 1's port B reads from the serial bus. DATA IN (PB0), CLK IN
+    # (PB2) and ATN IN (PB7) come through inverters, so a released line
+    # reads 0 and a pulled one 1. The jumpers on PB5 and PB6 pull a line
+    # low when closed, and both closed make device 8.
+    #
+    # The drive sees the host's side of the bus a host cycle late. The
+    # host's CIA changes its pins at the end of the cycle that writes them,
+    # and the drive's VIA samples its own late in each of its cycles, so a
+    # drive cycle that runs alongside the write reads the lines from
+    # before it. The drive runs after the host in each host cycle (see
+    # Computer#cycle!), so the port reads the host's lines as latch_host
+    # took them at the end of the last one. Fast loaders that time their
+    # transfer from an ATN edge, as VICE's drive tests do, depend on it.
+    #
+    # A model's serial port includes it, with its own port A.
+    module SerialLines
+      DATA_IN = 0x01
+      CLK_IN = 0x04
+      ATN_IN = 0x80
+      SERIAL_INPUTS = DATA_IN | CLK_IN | ATN_IN
+      JUMPERS = 0b0110_0000
+
+      attr_reader :bus
+
+      def bus=(bus)
+        @bus = bus
+        latch_host
+      end
+
+      # Takes the host's lines as the machine last pushed them into the bus,
+      # for the drive cycles of the next host cycle.
+      def latch_host
+        @host = @bus.host_lines
+      end
+
+      # The host's lines as last latched. The jumpers and the bus are the
+      # drive's wiring.
+      def save_state(out)
+        out.int(@host)
+      end
+
+      def load_state(input)
+        @host = input.int
+      end
+
+      # Whether the host has moved ATN since the last latch_host.
+      def atn_moved? = (@bus.host_lines ^ @host).anybits?(IECBus::HOST_ATN_OUT)
+
+      def atn_low? = @bus.atn_low?(@host)
+
+      def read_b(_lines)
+        low = @bus.low_lines(@host)
+        value = @port_b
+        value |= DATA_IN if low.anybits?(IECBus::DATA)
+        value |= CLK_IN if low.anybits?(IECBus::CLK)
+        value |= ATN_IN if low.anybits?(IECBus::ATN)
+        value
+      end
+
+      private
+
+      def init_serial_lines(device, bus)
+        @port_b = (0xff & ~(SERIAL_INPUTS | JUMPERS)) | (((device - 8) & 0x03) << 5)
+        @host = 0
+        self.bus = bus
+      end
+    end
+  end
+end

data/lib/badline/{drive1541 → drive}/sleep.rb

@@ -1,7 +1,7 @@
 # frozen_string_literal: true
 
 module Badline
-  class Drive1541
+  module Drive
     # The drive asleep, as Idle and Orbit let it: host_cycle! counts the
     # host cycles that go by, and waking turns them into drive cycles
     # through the phase accumulator and runs them. Whole orbits and whole
@@ -62,12 +62,12 @@ module Badline
         return @wake_at = 0 if @orbit_cycles
 
         needed = ((@budget - @owed) * @host_clock_hz) - @phase
-        @wake_at = needed.positive? ? (needed + CLOCK_HZ - 1) / CLOCK_HZ : 1
+        @wake_at = needed.positive? ? (needed + @clock_hz - 1) / @clock_hz : 1
       end
 
       # Runs the cycles owed.
       def wake!
-        phase = @phase + (@slept * CLOCK_HZ)
+        phase = @phase + (@slept * @clock_hz)
         @phase = phase % @host_clock_hz
         owed = @owed + (phase / @host_clock_hz)
         @owed = 0
@@ -104,6 +104,7 @@ module Badline
         @cpu.fast_forward(cycles, passes * @pass_instructions)
         @via1.fast_forward(cycles)
         @via2.fast_forward(cycles)
+        fast_forward_chips(cycles)
         @cycles += cycles
         @budget -= cycles
         cycles

data/lib/badline/drive/watch.rb

@@ -0,0 +1,150 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drive
+    # A drive bus's eye on what the CPU reaches, for Idle and Orbit. While
+    # Idle records a pass of the DOS's idle loop, the bus watches it (see
+    # watch!). While Idle looks for an orbit, the bus guards the drive
+    # (see guard!). The bus calls watch_read and watch_write with the
+    # address folded into $0000-$1FFF, RAM and the two VIAs at $1800 and
+    # $1C00, while @watching.
+    module Watch
+      # VIA registers, as bits by offset, whose access makes a watched
+      # stretch volatile: reads of either VIA's counters and shift register
+      # and of VIA 1's port B, and writes to VIA 2's timers, shift register
+      # and ACR. Any write to VIA 1 does too (watch_write).
+      VOLATILE_VIA1_READS = 0x0731
+      VOLATILE_VIA2_READS = 0x0730
+      VOLATILE_VIA2_WRITES = 0x0ff0
+
+      # The timer each VIA register reaches, by offset, as bits: 1 for
+      # timer 1 and 2 for timer 2.
+      TIMER_REGISTERS = [0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 0, 0, 0, 0, 0, 0].freeze
+
+      # Whether a watched stretch did something that makes it unrepeatable.
+      attr_reader :volatile
+
+      # The RAM a watched stretch read or wrote, as each address's value
+      # from before the first access.
+      attr_reader :touched
+
+      # Whether the drive did something since guard! that reached outside
+      # it, or took something in from outside.
+      attr_reader :tainted
+
+      # The timers the drive read or wrote since guard!, as bits: VIA 1's
+      # timer 1 and timer 2 in bits 0 and 1, and VIA 2's in bits 2 and 3.
+      attr_reader :touched_timers
+
+      # Starts watching: see volatile and touched. The bus stops watching
+      # once the stretch turns volatile.
+      def watch!
+        @recording = true
+        @volatile = false
+        @touched = {}
+        watching!
+      end
+
+      def unwatch!
+        @recording = false
+        watching!
+      end
+
+      # Starts guarding: see tainted and touched_timers. Reading VIA 1's
+      # port B, which reads the serial bus, taints the drive, and so do
+      # any write to VIA 1, whose port B drives the serial bus, a write to
+      # VIA 2's shift register or ACR, and VIA 2 turning the motor on or
+      # changing the LED. The bus stops guarding once the drive is tainted.
+      def guard!
+        @guarding = true
+        @tainted = false
+        @touched_timers = 0
+        @led = @via2.port_b_output & Drive1541::Mechanism::LED
+        watching!
+      end
+
+      private
+
+      def init_watch
+        @recording = @guarding = @watching = false
+        @volatile = @tainted = false
+        @touched = {}
+        @touched_timers = 0
+        @led = 0
+      end
+
+      def watching!
+        @watching = @recording || @guarding
+      end
+
+      # An access to a chip beyond the VIAs, as the 1571's CIA and floppy
+      # controller are: it makes the stretch volatile and taints the
+      # drive.
+      def watch_chip
+        volatile! if @recording
+        taint! if @guarding
+      end
+
+      def touch(addr)
+        @touched[addr] = @ram.peek(addr) unless @touched.key?(addr)
+      end
+
+      def watch_read(addr)
+        if addr < 0x0800
+          touch(addr) if @recording
+        elsif addr >= 0x1800
+          via1 = addr < 0x1c00
+          watch(via1 ? VOLATILE_VIA1_READS : VOLATILE_VIA2_READS, addr) if @recording
+          guard_read(via1, addr & 0x0f) if @guarding
+        end
+      end
+
+      def watch_write(addr)
+        if addr >= 0x1c00
+          watch_via2_write(addr) if @recording
+          guard_via2_write(addr & 0x0f) if @guarding
+        elsif addr >= 0x1800
+          volatile! if @recording
+          taint! if @guarding
+        end
+      end
+
+      # Any write to VIA 1 makes the stretch volatile (watch_write), and so
+      # does a write to VIA 2 that leaves the motor on.
+      def watch_via2_write(addr)
+        watch(VOLATILE_VIA2_WRITES, addr)
+        volatile! if @recording && @via2.port_b_output.anybits?(Drive1541::Mechanism::MOTOR)
+      end
+
+      def watch(volatile, addr)
+        volatile! if volatile.anybits?(1 << (addr & 0x0f))
+      end
+
+      def volatile!
+        @volatile = true
+        @recording = false
+        watching!
+      end
+
+      def guard_read(via1, offset)
+        return taint! if via1 && offset.zero?
+
+        @touched_timers |= via1 ? TIMER_REGISTERS[offset] : TIMER_REGISTERS[offset] << 2
+      end
+
+      def guard_via2_write(offset)
+        return taint! if offset.between?(0x0a, 0x0b)
+
+        @touched_timers |= TIMER_REGISTERS[offset] << 2
+        lines = @via2.port_b_output
+        taint! if lines.anybits?(Drive1541::Mechanism::MOTOR) || (lines & Drive1541::Mechanism::LED) != @led
+      end
+
+      def taint!
+        @tainted = true
+        @guarding = false
+        watching!
+      end
+    end
+  end
+end

data/lib/badline/drive.rb

@@ -0,0 +1,9 @@
+# frozen_string_literal: true
+
+require "badline/drive/sleep"
+require "badline/drive/idle"
+require "badline/drive/orbit"
+require "badline/drive/core"
+require "badline/drive/idle_cpu"
+require "badline/drive/watch"
+require "badline/drive/serial_lines"