axi_tdl 0.0.7 → 0.0.12
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- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +42 -0
- data/.github/workflows/ruby.yml +35 -0
- data/.travis.yml +9 -0
- data/Gemfile +4 -0
- data/README.EN.md +317 -0
- data/README.md +24 -18
- data/Rakefile +1 -5
- data/axi_tdl.gemspec +4 -4
- data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +4 -4
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +5 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +7 -7
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +1 -1
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
- data/lib/axi/AXI_stream/axi_stream_latency.sv +56 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +20 -20
- data/lib/axi/AXI_stream/axis_head_cut_verc.rb +99 -43
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +36 -39
- data/lib/axi/AXI_stream/axis_insert_copy.sv +1 -1
- data/lib/axi/AXI_stream/axis_length_split_with_user.sv +87 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.rb +41 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +1 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +37 -16
- data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +3 -2
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync.sv +70 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.rb +49 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +84 -0
- data/lib/axi_tdl.rb +12 -0
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +1 -0
- data/lib/tdl/SDL/path_lib.rb +1 -1
- data/lib/tdl/SDL/vcs_axi4_comptable.rb +9 -0
- data/lib/tdl/SDL/vcs_axis_comptable.rb +17 -0
- data/lib/tdl/SDL/vcs_data_c_comptable.rb +9 -0
- data/lib/tdl/class_hdl/hdl_always_ff.rb +1 -1
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +15 -3
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -0
- data/lib/tdl/examples/2_hdl_class/module_def.rb +2 -1
- data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +3 -1
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +1 -1
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +0 -2
- data/lib/tdl/exlib/test_point.rb +8 -2
- data/lib/tdl/sdlmodule/sdlmodule.rb +64 -0
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +13 -0
- data/lib/tdl/sdlmodule/top_module.rb +1 -0
- data/lib/tdl/tdl.rb +14 -2
- data/lib/tdl/tdlerror/tdlerror.rb +1 -0
- metadata +128 -14
- data/Gemfile.lock +0 -28
@@ -0,0 +1,49 @@
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require_hdl 'data_c_pipe_sync.sv'
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TdlBuild.data_c_pipe_sync_seam(__dir__) do
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parameter.LAT 4
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parameter.DSIZE 32
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## as like: hdl```
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## assign in_datas[0] = in_inf.data + 1;
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## assign in_datas[1] = out_datas[0]+1;```
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input[param.LAT,param.DSIZE] - 'in_datas'
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output[param.LAT,param.DSIZE] - 'out_datas'
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port.data_inf_c.slaver - 'in_inf'
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port.data_inf_c.master - 'out_inf'
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same_clock_domain(in_inf, out_inf)
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in_inf.copy(name: 'in_inf_array', dimension: [param.LAT])
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out_inf.copy(name: 'out_inf_array', dimension: [param.LAT])
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generate(param.LAT) do |kk|
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data_c_pipe_sync.data_c_pipe_sync_inst do |h|
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h.parameter.DSIZE param.DSIZE
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h.input['DSIZE'].in_data in_datas[kk] ##// as like: hdl``` assign in_data = in_inf.data + 1;
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h.output['DSIZE'].out_data out_datas[kk]
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h.port.data_inf_c.slaver.in_inf in_inf_array[kk]
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h.port.data_inf_c.master.out_inf out_inf_array[kk]
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end
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IF kk != 0 do
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Assign do
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in_inf_array[kk].valid <= out_inf_array[kk-1].valid
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in_inf_array[kk].data <= out_inf_array[kk-1].data
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out_inf_array[kk-1].ready <= in_inf_array[kk].ready
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end
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end
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end
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Assign do
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in_inf_array[0].valid <= in_inf.valid
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in_inf_array[0].data <= in_inf.data
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in_inf.ready <= in_inf_array[0].ready
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end
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Assign do
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out_inf.data <= out_inf_array[param.LAT-1].data
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out_inf.valid <= out_inf_array[param.LAT-1].valid
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out_inf_array[param.LAT-1].ready <= out_inf.ready
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end
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end
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@@ -0,0 +1,84 @@
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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created: xxxx.xx.xx
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module data_c_pipe_sync_seam #(
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parameter LAT = 4,
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parameter DSIZE = 32
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)(
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input [ DSIZE-1:0] in_datas [LAT-1:0],
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output [ DSIZE-1:0] out_datas [LAT-1:0],
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data_inf_c.slaver in_inf,
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data_inf_c.master out_inf
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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data_inf_c #(.DSIZE(in_inf.DSIZE)) in_inf_array[LAT-1:0] (.clock(in_inf.clock),.rst_n(in_inf.rst_n)) ;
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data_inf_c #(.DSIZE(out_inf.DSIZE)) out_inf_array[LAT-1:0] (.clock(out_inf.clock),.rst_n(out_inf.rst_n)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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//==========================================================================
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//-------- expression ------------------------------------------------------
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generate
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for(genvar KK0=0;KK0 < LAT;KK0++)begin
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data_c_pipe_sync #(
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.DSIZE (DSIZE )
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)data_c_pipe_sync_inst(
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/* input */.in_data (in_datas[ KK0] ),
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/* output */.out_data (out_datas[ KK0] ),
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/* data_inf_c.slaver */.in_inf (in_inf_array[ KK0] ),
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/* data_inf_c.master */.out_inf (out_inf_array[ KK0] )
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);
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if( KK0!=0)begin
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assign in_inf_array[ KK0].valid = out_inf_array[ KK0-1].valid;
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assign in_inf_array[ KK0].data = out_inf_array[ KK0-1].data;
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assign out_inf_array[ KK0-1].ready = in_inf_array[ KK0].ready;
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end end
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endgenerate
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//-------- CLOCKs Total 2 ----------------------
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//--->> CheckClock <<----------------
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logic cc_done_10,cc_same_10;
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integer cc_afreq_10,cc_bfreq_10;
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ClockSameDomain CheckPClock_inst_10(
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/* input */ .aclk (in_inf.clock ),
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/* input */ .bclk (out_inf.clock ),
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/* output logic */ .done (cc_done_10),
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/* output logic */ .same (cc_same_10),
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/* output integer */ .aFreqK (cc_afreq_10),
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/* output integer */ .bFreqK (cc_bfreq_10)
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);
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initial begin
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wait(cc_done_10);
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assert(cc_same_10)
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else begin
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$error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_10, 1000000.0/cc_bfreq_10);
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repeat(10)begin
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@(posedge in_inf.clock);
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end
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$stop;
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end
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end
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//---<< CheckClock >>----------------
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//======== CLOCKs Total 2 ======================
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assign in_inf_array[0].valid = in_inf.valid;
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assign in_inf_array[0].data = in_inf.data;
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assign in_inf.ready = in_inf_array[0].ready;
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assign out_inf.data = out_inf_array[ LAT-1].data;
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assign out_inf.valid = out_inf_array[ LAT-1].valid;
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assign out_inf_array[ LAT-1].ready = out_inf.ready;
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endmodule
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data/lib/axi_tdl.rb
CHANGED
@@ -8,8 +8,20 @@ end
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add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI_stream"))
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add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI_stream/data_width"))
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add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI_stream/stream_cache"))
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add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI_stream/packet_fifo"))
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add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI4"))
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add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI4/axi4_pipe"))
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add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI4/interconnect"))
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add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI4/width_convert"))
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add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI4/packet_partition"))
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add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/common_fifo"))
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add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/common"))
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add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/data_interface"))
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add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/data_interface/data_inf_c"))
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## base require
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require_hdl 'axis_master_empty.sv'
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require_hdl 'axis_slaver_empty.sv'
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data/lib/axi_tdl/version.rb
CHANGED
@@ -6,6 +6,7 @@ self.real_sv_path = '/home/CookDarwin/work/fpga/axi/AXI_stream/packet_fifo/axi_s
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self.path = File.expand_path(__FILE__)
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parameter.DEPTH 2
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parameter.BYTE_DEPTH 8096
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parameter.USE_KEEP "OFF"
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port.axi_stream_inf.slaver - 'axis_in'
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port.axi_stream_inf.master - 'axis_out'
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end
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data/lib/tdl/SDL/path_lib.rb
CHANGED
@@ -0,0 +1,9 @@
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sm = SdlModule.new(name:File.basename(__FILE__,".rb"))
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sm.Parameter("ORIGIN",'master')
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sm.Parameter("TO",'slaver')
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sm.Input("origin")
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sm.Output("to")
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sm.origin_sv = true
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sm.real_sv_path = File.expand_path(File.join(__dir__, "../../axi/AXI4/vcs_axi4_comptable.sv"))
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@@ -0,0 +1,17 @@
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# sm = SdlModule.new(name:File.basename(__FILE__,".rb"))
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# sm.Parameter("ORIGIN",'master')
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# sm.Parameter("TO",'slaver')
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# sm.Input("origin")
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# sm.Output("to")
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# sm.origin_sv = true
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sm = TdlBuild.vcs_axis_comptable do
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parameter.ORIGIN 'master'
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parameter.TO 'slaver'
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input - 'origin'
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output - 'to'
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end
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sm.real_sv_path = File.expand_path(File.join(__dir__, "../../axi/AXI_stream/vcs_axis_comptable.sv"))
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@@ -0,0 +1,9 @@
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sm = SdlModule.new(name:File.basename(__FILE__,".rb"))
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sm.Parameter("ORIGIN",'master')
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sm.Parameter("TO",'slaver')
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sm.Input("origin")
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sm.Output("to")
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sm.origin_sv = true
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sm.real_sv_path = File.expand_path(File.join(__dir__, "../../axi/data_interface/data_inf_c/vcs_data_c_comptable.sv"))
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@@ -58,9 +58,21 @@ module ClassHDL
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# 计算生成新的OpertorChain 是 self 也需要抛弃
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self.slaver = true
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# return self
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-
new_op =
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-
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-
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new_op = nil
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AssignDefOpertor.with_rollback_opertors(:old) do
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if tree.size == 2 && tree.last[1].to_s == "<="
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new_op = OpertorChain.new
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new_op.tree = new_op.tree + self.tree
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new_op.tree.push [b,os]
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elsif tree.size >= 2 && (!['*',"/","~"].include?(tree.last[1].to_s))
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new_op = brackets
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new_op.tree.push [b,os]
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else
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new_op = OpertorChain.new
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new_op.tree = new_op.tree + self.tree
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new_op.tree.push [b,os]
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end
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end
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if ClassHDL::AssignDefOpertor.curr_assign_block
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ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
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@@ -29,7 +29,7 @@ data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
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//==========================================================================
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//-------- expression ------------------------------------------------------
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always_ff@(posedge clock,negedge rst_n) begin
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-
32*2- 5-
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( 32*2- 5)-6;
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end
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endmodule
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@@ -35,7 +35,7 @@ function status(input [7:0] code,output logic [15:0] pl);
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endfunction:status
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function logic status_xp(input [7:0] code,output logic [15:0] pl);
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-
status_xp = ( inm!=0|
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status_xp = ( ( inm!=0)|( inm!=1));
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endfunction:status_xp
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function SE_STATE_ctrl pre_status(input [7:0] code,output logic [15:0] pl,input SE_STATE_ctrl ll);
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@@ -47,6 +47,6 @@ endfunction:pre_status
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assign gp = status(67, gp+1,opop);
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assign gp = pre_status();
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-
assign gp = ( inm!=0|
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assign gp = ( ( inm!=0)|( inm!=1));
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endmodule
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@@ -19,7 +19,7 @@ module test_module_var #(
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//==========================================================================
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//-------- define ----------------------------------------------------------
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-
localparam ASIZE = 20;
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+
localparam ASIZE = 20 ;
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axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_axis_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_axis0_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
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axi_inf #(.DSIZE(32),.IDSIZE(2),.ASIZE(8),.LSIZE(9),.MODE("BOTH"),.ADDR_STEP(4294967295)) tmp_axi4_inf (.axi_aclk(clock),.axi_aresetn(rst_n)) ;
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data/lib/tdl/exlib/test_point.rb
CHANGED
@@ -113,12 +113,18 @@ module TdlSpace
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113
113
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def root_ref(&block)
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114
114
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ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
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115
115
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rels = path_refs(&block)
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116
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+
if block_given?
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117
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+
sst = "block given"
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118
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+
else
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119
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+
sst = "no block"
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120
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+
end
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121
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+
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116
122
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if rels.size == 1
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117
123
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rels[0]
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118
124
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elsif rels.size == 0
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119
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-
raise TdlError.new "#{self} Cant find root ref"
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125
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+
raise TdlError.new "#{self} Cant find root ref {#{sst}}"
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120
126
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else
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121
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-
raise TdlError.new "#{self} Find multi root refs \n#{rels.join("\n")}\n"
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127
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+
raise TdlError.new "#{self} Find multi root refs {#{sst}} \n#{rels.join("\n")}\n"
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122
128
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end
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123
129
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end
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124
130
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end
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@@ -404,4 +404,68 @@ class SdlModule
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404
404
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405
405
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Clock.same_clock(self, *objs_clks)
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406
406
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end
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407
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+
end
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408
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+
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409
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+
## 获取 引用的所有文件
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410
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+
class SdlModule
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411
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+
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412
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+
def __ref_children_modules__
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413
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+
curr_refs = []
|
414
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+
|
415
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+
@_import_packages_ ||= []
|
416
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+
curr_refs << @_import_packages_
|
417
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+
|
418
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+
instance_and_children_module.values.each do |pm|
|
419
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+
curr_refs << [pm, pm.__ref_children_modules__()]
|
420
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+
end
|
421
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+
|
422
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+
return curr_refs
|
423
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+
end
|
424
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+
|
425
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+
def ref_modules
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426
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+
|
427
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+
curr_refs = __ref_children_modules__.flatten.uniq.reject do |e|
|
428
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+
e.is_a?(ClassHDL::ClearSdlModule)
|
429
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+
end
|
430
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+
curr_refs << self
|
431
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+
end
|
432
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+
|
433
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+
def self.base_hdl_ref
|
434
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+
## 基本接口引用
|
435
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+
_base_refs = []
|
436
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+
_base_refs << ['axi_inf', File.expand_path(File.join(__dir__, "../../axi/interface_define/axi_inf.sv"))]
|
437
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+
_base_refs << ['axi_lite_inf', File.expand_path(File.join(__dir__, "../../axi/interface_define/axi_lite_inf.sv"))]
|
438
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+
_base_refs << ['axi_stream', File.expand_path(File.join(__dir__, "../../axi/interface_define/axi_stream_inf.sv"))]
|
439
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+
_base_refs << ['data_inf', File.expand_path(File.join(__dir__, "../../axi/data_interface/data_interface.sv"))]
|
440
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+
_base_refs << ['data_inf_c', File.expand_path(File.join(__dir__, "../../axi/data_interface/data_interface_pkg.sv"))]
|
441
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+
_base_refs << ['axi_bfm_pkg', File.expand_path(File.join(__dir__, "../../axi/AXI_BFM/AXI_BFM_PKG.sv"))]
|
442
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+
_base_refs << ['cm_ram_inf', File.expand_path(File.join(__dir__, "../../tdl/rebuild_ele/cm_ram_inf.sv"))]
|
443
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+
_base_refs << ['Lite_Addr_Data_CMD', File.expand_path(File.join(__dir__, "../../axi/AXI_Lite/gen_axi_lite_ctrl.sv"))]
|
444
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+
_base_refs
|
445
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+
end
|
446
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+
|
447
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+
def pretty_ref_hdl_moduls_echo
|
448
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+
index = 1
|
449
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+
_indexs = []
|
450
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+
_names = []
|
451
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+
_paths = []
|
452
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+
max_size = 0
|
453
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+
ref_modules.each do |e|
|
454
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+
_indexs << index
|
455
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+
_names << e.module_name
|
456
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+
_paths << File.expand_path(e.real_sv_path)
|
457
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+
index += 1
|
458
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+
if e.module_name.size > max_size
|
459
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+
max_size = e.module_name.size
|
460
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+
end
|
461
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+
end
|
462
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+
puts(pagination(" Modules of <#{module_name}> reference"))
|
463
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+
|
464
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+
# fstr = "[%#{index.to_s.size}d] %-#{ _names.map do |e| e.size end.max }s %s"
|
465
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+
fstr = "[%#{index.to_s.size}d] %-#{ max_size }s %s"
|
466
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+
|
467
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+
(index-1).times do |xi|
|
468
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+
puts (fstr % [_indexs[xi], _names[xi], _paths[xi]])
|
469
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+
end
|
470
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+
end
|
407
471
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end
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@@ -1,5 +1,18 @@
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1
1
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## read sdlmodule head
|
2
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+
class Tdl
|
3
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+
@@__head_logo__ = nil
|
4
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+
def self.head_logo
|
5
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+
@@__head_logo__
|
6
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+
end
|
7
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+
|
8
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+
def self.head_logo=(a)
|
9
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+
$__sdlmodule_head_logo__ = a
|
10
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+
@@__head_logo__ = a
|
11
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+
end
|
12
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+
end
|
13
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+
|
2
14
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$__sdlmodule_head_logo__ = File.open(File.join(__dir__,"sdlmodule_head_logo.txt")).read
|
15
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+
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3
16
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class SdlModule
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4
17
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attr_accessor :origin_sv
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5
18
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