axi_tdl 0.0.7 → 0.0.12

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Files changed (55) hide show
  1. checksums.yaml +4 -4
  2. data/.github/workflows/gem-push.yml +42 -0
  3. data/.github/workflows/ruby.yml +35 -0
  4. data/.travis.yml +9 -0
  5. data/Gemfile +4 -0
  6. data/README.EN.md +317 -0
  7. data/README.md +24 -18
  8. data/Rakefile +1 -5
  9. data/axi_tdl.gemspec +4 -4
  10. data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
  11. data/lib/axi/AXI4/axi4_dpram_cache.sv +4 -4
  12. data/lib/axi/AXI4/axis_to_axi4_wr.rb +5 -0
  13. data/lib/axi/AXI4/axis_to_axi4_wr.sv +7 -7
  14. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +1 -1
  15. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
  16. data/lib/axi/AXI_stream/axi_stream_latency.sv +56 -0
  17. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +20 -20
  18. data/lib/axi/AXI_stream/axis_head_cut_verc.rb +99 -43
  19. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +36 -39
  20. data/lib/axi/AXI_stream/axis_insert_copy.sv +1 -1
  21. data/lib/axi/AXI_stream/axis_length_split_with_user.sv +87 -0
  22. data/lib/axi/AXI_stream/axis_pipe_sync_seam.rb +41 -0
  23. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
  24. data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +1 -0
  25. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +37 -16
  26. data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +3 -2
  27. data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +1 -1
  28. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync.sv +70 -0
  29. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.rb +49 -0
  30. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +84 -0
  31. data/lib/axi_tdl.rb +12 -0
  32. data/lib/axi_tdl/version.rb +1 -1
  33. data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +1 -0
  34. data/lib/tdl/SDL/path_lib.rb +1 -1
  35. data/lib/tdl/SDL/vcs_axi4_comptable.rb +9 -0
  36. data/lib/tdl/SDL/vcs_axis_comptable.rb +17 -0
  37. data/lib/tdl/SDL/vcs_data_c_comptable.rb +9 -0
  38. data/lib/tdl/class_hdl/hdl_always_ff.rb +1 -1
  39. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +15 -3
  40. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -0
  41. data/lib/tdl/examples/2_hdl_class/module_def.rb +2 -1
  42. data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +3 -1
  43. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +1 -1
  44. data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +2 -2
  45. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +1 -1
  46. data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -0
  47. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +0 -2
  48. data/lib/tdl/exlib/test_point.rb +8 -2
  49. data/lib/tdl/sdlmodule/sdlmodule.rb +64 -0
  50. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +13 -0
  51. data/lib/tdl/sdlmodule/top_module.rb +1 -0
  52. data/lib/tdl/tdl.rb +14 -2
  53. data/lib/tdl/tdlerror/tdlerror.rb +1 -0
  54. metadata +128 -14
  55. data/Gemfile.lock +0 -28
@@ -0,0 +1,49 @@
1
+ require_hdl 'data_c_pipe_sync.sv'
2
+
3
+ TdlBuild.data_c_pipe_sync_seam(__dir__) do
4
+ parameter.LAT 4
5
+ parameter.DSIZE 32
6
+ ## as like: hdl```
7
+ ## assign in_datas[0] = in_inf.data + 1;
8
+ ## assign in_datas[1] = out_datas[0]+1;```
9
+ input[param.LAT,param.DSIZE] - 'in_datas'
10
+ output[param.LAT,param.DSIZE] - 'out_datas'
11
+ port.data_inf_c.slaver - 'in_inf'
12
+ port.data_inf_c.master - 'out_inf'
13
+
14
+ same_clock_domain(in_inf, out_inf)
15
+
16
+ in_inf.copy(name: 'in_inf_array', dimension: [param.LAT])
17
+ out_inf.copy(name: 'out_inf_array', dimension: [param.LAT])
18
+
19
+ generate(param.LAT) do |kk|
20
+ data_c_pipe_sync.data_c_pipe_sync_inst do |h|
21
+ h.parameter.DSIZE param.DSIZE
22
+ h.input['DSIZE'].in_data in_datas[kk] ##// as like: hdl``` assign in_data = in_inf.data + 1;
23
+ h.output['DSIZE'].out_data out_datas[kk]
24
+ h.port.data_inf_c.slaver.in_inf in_inf_array[kk]
25
+ h.port.data_inf_c.master.out_inf out_inf_array[kk]
26
+ end
27
+
28
+ IF kk != 0 do
29
+ Assign do
30
+ in_inf_array[kk].valid <= out_inf_array[kk-1].valid
31
+ in_inf_array[kk].data <= out_inf_array[kk-1].data
32
+ out_inf_array[kk-1].ready <= in_inf_array[kk].ready
33
+ end
34
+ end
35
+ end
36
+
37
+ Assign do
38
+ in_inf_array[0].valid <= in_inf.valid
39
+ in_inf_array[0].data <= in_inf.data
40
+ in_inf.ready <= in_inf_array[0].ready
41
+ end
42
+
43
+ Assign do
44
+ out_inf.data <= out_inf_array[param.LAT-1].data
45
+ out_inf.valid <= out_inf_array[param.LAT-1].valid
46
+ out_inf_array[param.LAT-1].ready <= out_inf.ready
47
+ end
48
+
49
+ end
@@ -0,0 +1,84 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ created: xxxx.xx.xx
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+
13
+ module data_c_pipe_sync_seam #(
14
+ parameter LAT = 4,
15
+ parameter DSIZE = 32
16
+ )(
17
+ input [ DSIZE-1:0] in_datas [LAT-1:0],
18
+ output [ DSIZE-1:0] out_datas [LAT-1:0],
19
+ data_inf_c.slaver in_inf,
20
+ data_inf_c.master out_inf
21
+ );
22
+
23
+ //==========================================================================
24
+ //-------- define ----------------------------------------------------------
25
+
26
+ data_inf_c #(.DSIZE(in_inf.DSIZE)) in_inf_array[LAT-1:0] (.clock(in_inf.clock),.rst_n(in_inf.rst_n)) ;
27
+ data_inf_c #(.DSIZE(out_inf.DSIZE)) out_inf_array[LAT-1:0] (.clock(out_inf.clock),.rst_n(out_inf.rst_n)) ;
28
+ //==========================================================================
29
+ //-------- instance --------------------------------------------------------
30
+
31
+ //==========================================================================
32
+ //-------- expression ------------------------------------------------------
33
+ generate
34
+ for(genvar KK0=0;KK0 < LAT;KK0++)begin
35
+ data_c_pipe_sync #(
36
+ .DSIZE (DSIZE )
37
+ )data_c_pipe_sync_inst(
38
+ /* input */.in_data (in_datas[ KK0] ),
39
+ /* output */.out_data (out_datas[ KK0] ),
40
+ /* data_inf_c.slaver */.in_inf (in_inf_array[ KK0] ),
41
+ /* data_inf_c.master */.out_inf (out_inf_array[ KK0] )
42
+ );
43
+ if( KK0!=0)begin
44
+ assign in_inf_array[ KK0].valid = out_inf_array[ KK0-1].valid;
45
+ assign in_inf_array[ KK0].data = out_inf_array[ KK0-1].data;
46
+ assign out_inf_array[ KK0-1].ready = in_inf_array[ KK0].ready;
47
+ end end
48
+ endgenerate
49
+ //-------- CLOCKs Total 2 ----------------------
50
+ //--->> CheckClock <<----------------
51
+ logic cc_done_10,cc_same_10;
52
+ integer cc_afreq_10,cc_bfreq_10;
53
+ ClockSameDomain CheckPClock_inst_10(
54
+ /* input */ .aclk (in_inf.clock ),
55
+ /* input */ .bclk (out_inf.clock ),
56
+ /* output logic */ .done (cc_done_10),
57
+ /* output logic */ .same (cc_same_10),
58
+ /* output integer */ .aFreqK (cc_afreq_10),
59
+ /* output integer */ .bFreqK (cc_bfreq_10)
60
+ );
61
+
62
+ initial begin
63
+ wait(cc_done_10);
64
+ assert(cc_same_10)
65
+ else begin
66
+ $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_10, 1000000.0/cc_bfreq_10);
67
+ repeat(10)begin
68
+ @(posedge in_inf.clock);
69
+ end
70
+ $stop;
71
+ end
72
+ end
73
+ //---<< CheckClock >>----------------
74
+
75
+ //======== CLOCKs Total 2 ======================
76
+ assign in_inf_array[0].valid = in_inf.valid;
77
+ assign in_inf_array[0].data = in_inf.data;
78
+ assign in_inf.ready = in_inf_array[0].ready;
79
+
80
+ assign out_inf.data = out_inf_array[ LAT-1].data;
81
+ assign out_inf.valid = out_inf_array[ LAT-1].valid;
82
+ assign out_inf_array[ LAT-1].ready = out_inf.ready;
83
+
84
+ endmodule
data/lib/axi_tdl.rb CHANGED
@@ -8,8 +8,20 @@ end
8
8
 
9
9
 
10
10
  add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI_stream"))
11
+ add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI_stream/data_width"))
11
12
  add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI_stream/stream_cache"))
13
+ add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI_stream/packet_fifo"))
12
14
  add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI4"))
15
+ add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI4/axi4_pipe"))
16
+ add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI4/interconnect"))
17
+ add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI4/width_convert"))
13
18
  add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI4/packet_partition"))
19
+ add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/common_fifo"))
14
20
  add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/common"))
15
21
  add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/data_interface"))
22
+ add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/data_interface/data_inf_c"))
23
+
24
+ ## base require
25
+ require_hdl 'axis_master_empty.sv'
26
+ require_hdl 'axis_slaver_empty.sv'
27
+
@@ -1,3 +1,3 @@
1
1
  module AxiTdl
2
- VERSION = "0.0.7"
2
+ VERSION = "0.0.12"
3
3
  end
@@ -6,6 +6,7 @@ self.real_sv_path = '/home/CookDarwin/work/fpga/axi/AXI_stream/packet_fifo/axi_s
6
6
  self.path = File.expand_path(__FILE__)
7
7
  parameter.DEPTH 2
8
8
  parameter.BYTE_DEPTH 8096
9
+ parameter.USE_KEEP "OFF"
9
10
  port.axi_stream_inf.slaver - 'axis_in'
10
11
  port.axi_stream_inf.master - 'axis_out'
11
12
  end
@@ -2,5 +2,5 @@
2
2
  require_relative "./../global_scan"
3
3
  curr = File.expand_path(__FILE__)
4
4
  curr_path = File.dirname(curr)
5
- require_path(curr_path)
5
+ # require_path(curr_path)
6
6
  # require_path_and_ignore(curr_path,"logic_condition.rb")
@@ -0,0 +1,9 @@
1
+ sm = SdlModule.new(name:File.basename(__FILE__,".rb"))
2
+
3
+ sm.Parameter("ORIGIN",'master')
4
+ sm.Parameter("TO",'slaver')
5
+ sm.Input("origin")
6
+ sm.Output("to")
7
+
8
+ sm.origin_sv = true
9
+ sm.real_sv_path = File.expand_path(File.join(__dir__, "../../axi/AXI4/vcs_axi4_comptable.sv"))
@@ -0,0 +1,17 @@
1
+ # sm = SdlModule.new(name:File.basename(__FILE__,".rb"))
2
+
3
+ # sm.Parameter("ORIGIN",'master')
4
+ # sm.Parameter("TO",'slaver')
5
+ # sm.Input("origin")
6
+ # sm.Output("to")
7
+
8
+ # sm.origin_sv = true
9
+
10
+ sm = TdlBuild.vcs_axis_comptable do
11
+ parameter.ORIGIN 'master'
12
+ parameter.TO 'slaver'
13
+ input - 'origin'
14
+ output - 'to'
15
+ end
16
+
17
+ sm.real_sv_path = File.expand_path(File.join(__dir__, "../../axi/AXI_stream/vcs_axis_comptable.sv"))
@@ -0,0 +1,9 @@
1
+ sm = SdlModule.new(name:File.basename(__FILE__,".rb"))
2
+
3
+ sm.Parameter("ORIGIN",'master')
4
+ sm.Parameter("TO",'slaver')
5
+ sm.Input("origin")
6
+ sm.Output("to")
7
+
8
+ sm.origin_sv = true
9
+ sm.real_sv_path = File.expand_path(File.join(__dir__, "../../axi/data_interface/data_inf_c/vcs_data_c_comptable.sv"))
@@ -153,7 +153,7 @@ class SdlModule
153
153
 
154
154
  def always_ff(*args,&block)
155
155
  if args[0].is_a? Hash
156
- return Always(args[0],&block)
156
+ return Always(**args[0],&block)
157
157
  end
158
158
  posedge_list = []
159
159
  negedge_list = []
@@ -58,9 +58,21 @@ module ClassHDL
58
58
  # 计算生成新的OpertorChain 是 self 也需要抛弃
59
59
  self.slaver = true
60
60
  # return self
61
- new_op = OpertorChain.new
62
- new_op.tree = new_op.tree + self.tree
63
- new_op.tree.push [b,os]
61
+ new_op = nil
62
+ AssignDefOpertor.with_rollback_opertors(:old) do
63
+ if tree.size == 2 && tree.last[1].to_s == "<="
64
+ new_op = OpertorChain.new
65
+ new_op.tree = new_op.tree + self.tree
66
+ new_op.tree.push [b,os]
67
+ elsif tree.size >= 2 && (!['*',"/","~"].include?(tree.last[1].to_s))
68
+ new_op = brackets
69
+ new_op.tree.push [b,os]
70
+ else
71
+ new_op = OpertorChain.new
72
+ new_op.tree = new_op.tree + self.tree
73
+ new_op.tree.push [b,os]
74
+ end
75
+ end
64
76
 
65
77
  if ClassHDL::AssignDefOpertor.curr_assign_block
66
78
  ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
@@ -9,6 +9,7 @@ created: xxxx.xx.xx
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
12
+ `timescale 1ns/1ps
12
13
 
13
14
  module tb_exp_test_unit();
14
15
  //==========================================================================
@@ -1,5 +1,6 @@
1
- require_relative '../../tdl.rb'
1
+ require 'axi_tdl'
2
2
  # require_relative "./../../class_hdl/hdl_module_def.rb"
3
+ require_hdl 'axi_stream_cache_35bit.sv'
3
4
 
4
5
  TdlBuild.test_module(File.join(__dir__,"tmp")) do
5
6
  input.clock - 'clock'
@@ -1,4 +1,6 @@
1
- require_relative '../../tdl.rb'
1
+ require 'axi_tdl'
2
+ require_hdl 'axi_stream_cache.sv'
3
+ require_hdl 'axis_append_A1.sv'
2
4
 
3
5
  TdlBuild.test_inst_sugar(File.join(__dir__,"tmp")) do
4
6
 
@@ -29,7 +29,7 @@ data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
29
29
  //==========================================================================
30
30
  //-------- expression ------------------------------------------------------
31
31
  always_ff@(posedge clock,negedge rst_n) begin
32
- 32*2- 5- 6;
32
+ ( 32*2- 5)-6;
33
33
  end
34
34
 
35
35
  endmodule
@@ -35,7 +35,7 @@ function status(input [7:0] code,output logic [15:0] pl);
35
35
  endfunction:status
36
36
 
37
37
  function logic status_xp(input [7:0] code,output logic [15:0] pl);
38
- status_xp = ( inm!=0| ( inm!=1));
38
+ status_xp = ( ( inm!=0)|( inm!=1));
39
39
  endfunction:status_xp
40
40
 
41
41
  function SE_STATE_ctrl pre_status(input [7:0] code,output logic [15:0] pl,input SE_STATE_ctrl ll);
@@ -47,6 +47,6 @@ endfunction:pre_status
47
47
 
48
48
  assign gp = status(67, gp+1,opop);
49
49
  assign gp = pre_status();
50
- assign gp = ( inm!=0| ( inm!=1));
50
+ assign gp = ( ( inm!=0)|( inm!=1));
51
51
 
52
52
  endmodule
@@ -19,7 +19,7 @@ module test_module_var #(
19
19
 
20
20
  //==========================================================================
21
21
  //-------- define ----------------------------------------------------------
22
- localparam ASIZE = 20;
22
+ localparam ASIZE = 20 ;
23
23
  axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_axis_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
24
24
  axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_axis0_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
25
25
  axi_inf #(.DSIZE(32),.IDSIZE(2),.ASIZE(8),.LSIZE(9),.MODE("BOTH"),.ADDR_STEP(4294967295)) tmp_axi4_inf (.axi_aclk(clock),.axi_aresetn(rst_n)) ;
@@ -10,6 +10,7 @@ madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
12
12
  `timescale 1ns/1ps
13
+ `timescale 1ns/1ps
13
14
 
14
15
  module tb_test_top();
15
16
  //==========================================================================
@@ -9,8 +9,6 @@ created: xxxx.xx.xx
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
12
- `timescale 1ns/1ps
13
- `timescale 1ns/1ps
14
12
 
15
13
  module tb_test_tttop();
16
14
  //==========================================================================
@@ -113,12 +113,18 @@ module TdlSpace
113
113
  def root_ref(&block)
114
114
  ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
115
115
  rels = path_refs(&block)
116
+ if block_given?
117
+ sst = "block given"
118
+ else
119
+ sst = "no block"
120
+ end
121
+
116
122
  if rels.size == 1
117
123
  rels[0]
118
124
  elsif rels.size == 0
119
- raise TdlError.new "#{self} Cant find root ref"
125
+ raise TdlError.new "#{self} Cant find root ref {#{sst}}"
120
126
  else
121
- raise TdlError.new "#{self} Find multi root refs \n#{rels.join("\n")}\n"
127
+ raise TdlError.new "#{self} Find multi root refs {#{sst}} \n#{rels.join("\n")}\n"
122
128
  end
123
129
  end
124
130
  end
@@ -404,4 +404,68 @@ class SdlModule
404
404
 
405
405
  Clock.same_clock(self, *objs_clks)
406
406
  end
407
+ end
408
+
409
+ ## 获取 引用的所有文件
410
+ class SdlModule
411
+
412
+ def __ref_children_modules__
413
+ curr_refs = []
414
+
415
+ @_import_packages_ ||= []
416
+ curr_refs << @_import_packages_
417
+
418
+ instance_and_children_module.values.each do |pm|
419
+ curr_refs << [pm, pm.__ref_children_modules__()]
420
+ end
421
+
422
+ return curr_refs
423
+ end
424
+
425
+ def ref_modules
426
+
427
+ curr_refs = __ref_children_modules__.flatten.uniq.reject do |e|
428
+ e.is_a?(ClassHDL::ClearSdlModule)
429
+ end
430
+ curr_refs << self
431
+ end
432
+
433
+ def self.base_hdl_ref
434
+ ## 基本接口引用
435
+ _base_refs = []
436
+ _base_refs << ['axi_inf', File.expand_path(File.join(__dir__, "../../axi/interface_define/axi_inf.sv"))]
437
+ _base_refs << ['axi_lite_inf', File.expand_path(File.join(__dir__, "../../axi/interface_define/axi_lite_inf.sv"))]
438
+ _base_refs << ['axi_stream', File.expand_path(File.join(__dir__, "../../axi/interface_define/axi_stream_inf.sv"))]
439
+ _base_refs << ['data_inf', File.expand_path(File.join(__dir__, "../../axi/data_interface/data_interface.sv"))]
440
+ _base_refs << ['data_inf_c', File.expand_path(File.join(__dir__, "../../axi/data_interface/data_interface_pkg.sv"))]
441
+ _base_refs << ['axi_bfm_pkg', File.expand_path(File.join(__dir__, "../../axi/AXI_BFM/AXI_BFM_PKG.sv"))]
442
+ _base_refs << ['cm_ram_inf', File.expand_path(File.join(__dir__, "../../tdl/rebuild_ele/cm_ram_inf.sv"))]
443
+ _base_refs << ['Lite_Addr_Data_CMD', File.expand_path(File.join(__dir__, "../../axi/AXI_Lite/gen_axi_lite_ctrl.sv"))]
444
+ _base_refs
445
+ end
446
+
447
+ def pretty_ref_hdl_moduls_echo
448
+ index = 1
449
+ _indexs = []
450
+ _names = []
451
+ _paths = []
452
+ max_size = 0
453
+ ref_modules.each do |e|
454
+ _indexs << index
455
+ _names << e.module_name
456
+ _paths << File.expand_path(e.real_sv_path)
457
+ index += 1
458
+ if e.module_name.size > max_size
459
+ max_size = e.module_name.size
460
+ end
461
+ end
462
+ puts(pagination(" Modules of <#{module_name}> reference"))
463
+
464
+ # fstr = "[%#{index.to_s.size}d] %-#{ _names.map do |e| e.size end.max }s %s"
465
+ fstr = "[%#{index.to_s.size}d] %-#{ max_size }s %s"
466
+
467
+ (index-1).times do |xi|
468
+ puts (fstr % [_indexs[xi], _names[xi], _paths[xi]])
469
+ end
470
+ end
407
471
  end
@@ -1,5 +1,18 @@
1
1
  ## read sdlmodule head
2
+ class Tdl
3
+ @@__head_logo__ = nil
4
+ def self.head_logo
5
+ @@__head_logo__
6
+ end
7
+
8
+ def self.head_logo=(a)
9
+ $__sdlmodule_head_logo__ = a
10
+ @@__head_logo__ = a
11
+ end
12
+ end
13
+
2
14
  $__sdlmodule_head_logo__ = File.open(File.join(__dir__,"sdlmodule_head_logo.txt")).read
15
+
3
16
  class SdlModule
4
17
  attr_accessor :origin_sv
5
18