axi_tdl 0.0.5 → 0.0.10
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.gitignore +2 -0
- data/Gemfile.lock +1 -1
- data/README.EN.md +317 -0
- data/README.md +24 -18
- data/axi_tdl.gemspec +2 -2
- data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +4 -4
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +5 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +7 -7
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +1 -1
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
- data/lib/axi/AXI_stream/axi_stream_latency.sv +56 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +20 -20
- data/lib/axi/AXI_stream/axis_head_cut_verc.rb +99 -43
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +36 -39
- data/lib/axi/AXI_stream/axis_insert_copy.sv +1 -1
- data/lib/axi/AXI_stream/axis_length_split_with_user.sv +87 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.rb +41 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +1 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +37 -16
- data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +3 -2
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync.sv +70 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.rb +49 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +84 -0
- data/lib/axi_tdl.rb +20 -0
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +1 -0
- data/lib/tdl/SDL/path_lib.rb +1 -1
- data/lib/tdl/SDL/vcs_axi4_comptable.rb +9 -0
- data/lib/tdl/SDL/vcs_axis_comptable.rb +17 -0
- data/lib/tdl/SDL/vcs_data_c_comptable.rb +9 -0
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +15 -3
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +2 -0
- data/lib/tdl/examples/2_hdl_class/module_def.rb +2 -1
- data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +3 -1
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +2 -2
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +0 -1
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +0 -1
- data/lib/tdl/exlib/test_point.rb +8 -2
- data/lib/tdl/sdlmodule/sdlmodule.rb +64 -0
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +13 -0
- data/lib/tdl/sdlmodule/top_module.rb +1 -0
- data/lib/tdl/tdl.rb +14 -2
- data/lib/tdl/tdlerror/tdlerror.rb +1 -0
- metadata +117 -5
@@ -80,14 +80,14 @@ initial begin
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end
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assign a_axis_inf.axis_tready = a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1] || (a_datac_rd_inf.ready && !a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1]);
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assign a_datac_rd_inf.data = {a_axis_inf.axis_tlast,a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1-
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assign a_datac_rd_inf.data = {a_axis_inf.axis_tlast,a_axis_inf.axis_tdata[ ( a_inf.ASIZE+a_inf.DSIZE+1-1)-1: ( a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE)-1]};
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assign a_datac_rd_inf.valid = a_axis_inf.axis_tvalid && !a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1];
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assign a_axis_rd_inf.axis_tvalid = a_datac_rd_rel_inf.valid;
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assign a_axis_rd_inf.axis_tdata = a_datac_rd_rel_inf.data[ a_inf.DSIZE-1:0];
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assign a_axis_rd_inf.axis_tlast = a_datac_rd_rel_inf.data[ a_inf.ASIZE+a_inf.DSIZE+1-1];
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assign a_datac_rd_rel_inf.ready = a_axis_rd_inf.axis_tready;
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assign xram_inf.addra = a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1-
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assign xram_inf.addra = a_axis_inf.axis_tdata[ ( a_inf.ASIZE+a_inf.DSIZE+1-1)-1: ( a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE)-1];
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assign xram_inf.dia = a_axis_inf.axis_tdata[ a_inf.DSIZE-1:0];
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assign xram_inf.wea = {xram_inf.MSIZE{a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1]}};
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assign xram_inf.ena = 1'b1;
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@@ -95,14 +95,14 @@ assign xram_inf.clka = a_inf.axi_aclk;
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assign xram_inf.rsta = ~a_inf.axi_aresetn;
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assign b_axis_inf.axis_tready = b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1] || (b_datac_rd_inf.ready && !b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1]);
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assign b_datac_rd_inf.data = {b_axis_inf.axis_tlast,b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1-
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assign b_datac_rd_inf.data = {b_axis_inf.axis_tlast,b_axis_inf.axis_tdata[ ( b_inf.ASIZE+b_inf.DSIZE+1-1)-1: ( b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE)-1]};
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assign b_datac_rd_inf.valid = b_axis_inf.axis_tvalid && !b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1];
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assign b_axis_rd_inf.axis_tvalid = b_datac_rd_rel_inf.valid;
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assign b_axis_rd_inf.axis_tdata = b_datac_rd_rel_inf.data[ b_inf.DSIZE-1:0];
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assign b_axis_rd_inf.axis_tlast = b_datac_rd_rel_inf.data[ b_inf.ASIZE+b_inf.DSIZE+1-1];
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assign b_datac_rd_rel_inf.ready = b_axis_rd_inf.axis_tready;
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assign xram_inf.addrb = b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1-
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assign xram_inf.addrb = b_axis_inf.axis_tdata[ ( b_inf.ASIZE+b_inf.DSIZE+1-1)-1: ( b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE)-1];
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assign xram_inf.dib = b_axis_inf.axis_tdata[ b_inf.DSIZE-1:0];
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assign xram_inf.web = {xram_inf.MSIZE{b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1]}};
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assign xram_inf.enb = 1'b1;
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@@ -2,6 +2,11 @@
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## raise TdlError.new("The module have be abandon\n Path:[#{__dir__}]\n Name:[#{__FILE__}]")
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require_hdl 'axis_length_split_with_addr.sv'
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require_hdl 'axi_stream_long_fifo.sv'
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require_hdl 'axi4_wr_auxiliary_gen_without_resp.sv'
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require_hdl 'axis_valve_with_pipe.sv'
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new_m = SdlModule.new(name:File.basename(__FILE__,".rb"),out_sv_path:__dir__)
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# Parameter :ADDR_STEP,1.0
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@@ -56,7 +56,7 @@ logic stream_en;
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) long_fifo_axis_out (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP))
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axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R1264 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
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axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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@@ -92,16 +92,16 @@ independent_clock_fifo #(
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/* output */.full (fifo_full )
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);
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axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
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/* output */.stream_en (stream_en
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/* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in
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/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (
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/* output */.stream_en (stream_en ),
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/* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
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/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R1264 )
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);
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vcs_axi4_comptable #(
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.ORIGIN ("master_wr_aux_no_resp" ),
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.TO ("master_wr" )
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)
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/* input */.origin (
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/* output */.to (axi_wr
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)vcs_axi4_comptable_axi_wr_aux_R858_axi_wr_inst(
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/* input */.origin (axi_wr_vcs_cp_R1264 ),
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/* output */.to (axi_wr )
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);
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axis_valve_with_pipe #(
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.MODE ("BOTH" )
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@@ -86,7 +86,7 @@ always_ff@(posedge clock,negedge rst_n) begin
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wait_last_inf.ready <= 1'b0;
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end
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else begin
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wait_last_inf.ready <= ( long_inf.axi_rvalid&long_inf.axi_rready&
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wait_last_inf.ready <= ( ( long_inf.axi_rvalid&long_inf.axi_rready)&long_inf.axi_rlast);
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end
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end
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@@ -31,7 +31,7 @@ logic one_long_stream;
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logic fifo_wr;
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logic [ IDSIZE+4-1:0] curr_id ;
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logic [LSIZE-1:0] curr_length ;
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logic [ data_in.DSIZE-IDSIZE-
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logic [ ( data_in.DSIZE-IDSIZE)-LSIZE-1:0] curr_addr ;
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logic [LSIZE-1:0] wr_length ;
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(* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_full;
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(* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_empty;
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} SE_STATE_ps;
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SE_STATE_ps CSTATE_ps,NSTATE_ps;
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initial begin
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assert( data_in.DSIZE+4==
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assert( ( data_in.DSIZE+4)==data_out.DSIZE)else begin
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$error("data_in.DSIZE<%d> != data_out.DSIZE<%d>",data_in.DSIZE,data_out.DSIZE);
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$stop;
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end
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript: base on planer
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author : Cook.Darwin
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Version: VERA.0.0
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creaded:
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madified:
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***********************************************/
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`timescale 1ns/1ps
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`include "define_macro.sv"
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module axi_stream_latency #(
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parameter LAT = 3
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)(
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input reset,
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axi_stream_inf.slaver axis_in,
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axi_stream_inf.master axis_out
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);
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data_inf_c #(.DSIZE(axis_in.DSIZE + 1 + axis_in.KSIZE + axis_in.USIZE)) data_slaver (.clock(axis_in.aclk), .rst_n(axis_in.aresetn) );
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data_inf_c #(.DSIZE(axis_in.DSIZE + 1 + axis_in.KSIZE + axis_in.USIZE + 1)) data_master (.clock(axis_in.aclk), .rst_n(axis_in.aresetn) );
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data_inf_c_planer_A1 #(
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.LAT (LAT ),
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.DSIZE (1 ),
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.HEAD ("ON" )
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)data_inf_c_planer_A1_inst(
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/* input */ .reset (reset ),
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/* input [DSIZE-1:0] */ .pack_data (1'b0 ),
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/* data_inf_c.slaver */ .slaver (data_slaver ),
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/* data_inf_c.master */ .master (data_master )///HEAD=="ON" : {pack_data,slaver.data} or /HEAD=="OFF" : {slaver.data,pack_data}
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);
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assign data_slaver.data = {axis_in.axis_tuser, axis_in.axis_tkeep, axis_in.axis_tlast, axis_in.axis_tdata};
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assign data_slaver.valid = axis_in.axis_tvalid;
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assign axis_in.axis_tready = data_slaver.ready;
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// axis_to_data_inf #(
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// .CONTAIN_LAST ("ON")
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// )axis_to_data_inf_inst(
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// /* axi_stream_inf.slaver */ .axis_in (axis_in ),
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// /* data_inf_c.master */ .data_out_inf (data_slaver )
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// );
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// data_c_to_axis_full data_c_to_axis_full_inst(
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// /* data_inf_c.slaver */ .data_in_inf (data_master ),
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// /* axi_stream_inf.master */ .axis_out (axis_out )
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// );
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assign {axis_out.axis_tuser, axis_out.axis_tkeep, axis_out.axis_tlast, axis_out.axis_tdata} = data_master.data[data_master.DSIZE-2:0];
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assign axis_out.axis_tvalid = data_master.valid;
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assign data_master.ready = axis_out.axis_tready;
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endmodule
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//-------- CLOCKs Total 3 ----------------------
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//--->> CheckClock <<----------------
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logic
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integer
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ClockSameDomain
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logic cc_done_8,cc_same_8;
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integer cc_afreq_8,cc_bfreq_8;
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ClockSameDomain CheckPClock_inst_8(
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/* input */ .aclk (origin_inf.aclk ),
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/* input */ .bclk (first_inf.aclk ),
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/* output logic */ .done (
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/* output logic */ .same (
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/* output integer */ .aFreqK (
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/* output integer */ .bFreqK (
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/* output logic */ .done (cc_done_8),
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/* output logic */ .same (cc_same_8),
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/* output integer */ .aFreqK (cc_afreq_8),
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/* output integer */ .bFreqK (cc_bfreq_8)
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);
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initial begin
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wait(
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assert(
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wait(cc_done_8);
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assert(cc_same_8)
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else begin
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$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/
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$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
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repeat(10)begin
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@(posedge origin_inf.aclk);
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end
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//---<< CheckClock >>----------------
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//--->> CheckClock <<----------------
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logic
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integer
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ClockSameDomain
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logic cc_done_9,cc_same_9;
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integer cc_afreq_9,cc_bfreq_9;
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ClockSameDomain CheckPClock_inst_9(
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/* input */ .aclk (origin_inf.aclk ),
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/* input */ .bclk (end_inf.aclk ),
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/* output logic */ .done (
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/* output logic */ .same (
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/* output integer */ .aFreqK (
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/* output integer */ .bFreqK (
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/* output logic */ .done (cc_done_9),
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/* output logic */ .same (cc_same_9),
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/* output integer */ .aFreqK (cc_afreq_9),
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/* output integer */ .bFreqK (cc_bfreq_9)
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);
|
93
93
|
|
94
94
|
initial begin
|
95
|
-
wait(
|
96
|
-
assert(
|
95
|
+
wait(cc_done_9);
|
96
|
+
assert(cc_same_9)
|
97
97
|
else begin
|
98
|
-
$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/
|
98
|
+
$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
|
99
99
|
repeat(10)begin
|
100
100
|
@(posedge origin_inf.aclk);
|
101
101
|
end
|
@@ -1,5 +1,7 @@
|
|
1
1
|
## VERC 非整数型剪切,使用 right shift
|
2
2
|
require_hdl 'axis_connect_pipe_right_shift_verb.sv'
|
3
|
+
# require_hdl 'axi_stream_latency.sv'
|
4
|
+
require_sdl 'axis_pipe_sync_seam.rb'
|
3
5
|
|
4
6
|
TdlBuild.axis_head_cut_verc(__dir__) do
|
5
7
|
parameter.BYTE_BITS 8
|
@@ -7,7 +9,7 @@ TdlBuild.axis_head_cut_verc(__dir__) do
|
|
7
9
|
port.axis.slaver - 'origin_inf'
|
8
10
|
port.axis.master - 'out_inf'
|
9
11
|
|
10
|
-
|
12
|
+
parameter.DX (origin_inf.DSIZE / param.BYTE_BITS)
|
11
13
|
|
12
14
|
Initial do
|
13
15
|
assert(param.DX < 17, "param.DX<%0d> !< 17",param.DX)
|
@@ -16,30 +18,61 @@ TdlBuild.axis_head_cut_verc(__dir__) do
|
|
16
18
|
|
17
19
|
origin_inf.clock_reset_taps('clock', 'rst_n')
|
18
20
|
|
19
|
-
axis_slaver_pipe_A1.axis_slaver_pipe_A1_inst do |h| #(
|
20
|
-
|
21
|
-
|
22
|
-
|
23
|
-
end
|
21
|
+
# axis_slaver_pipe_A1.axis_slaver_pipe_A1_inst do |h| #(
|
22
|
+
# h.param.DEPTH 3
|
23
|
+
# h.port.axis.slaver.axis_in origin_inf
|
24
|
+
# h.port.axis.master.axis_out origin_inf.copy(name: 'origin_inf_post')
|
25
|
+
# end
|
26
|
+
|
27
|
+
# axi_stream_latency.axi_stream_latency_inst do |h| #(
|
28
|
+
# h.parameter.LAT 3
|
29
|
+
# h.input.reset 1.b0
|
30
|
+
# h.port.axis.slaver.axis_in origin_inf
|
31
|
+
# h.port.axis.master.axis_out origin_inf.copy(name: 'origin_inf_post')
|
32
|
+
# end
|
33
|
+
|
34
|
+
axis_pipe_sync_seam.axis_pipe_sync_seam_inst do |h|
|
35
|
+
h.parameter.LAT 3
|
36
|
+
h.parameter.DSIZE 10+4+4
|
37
|
+
## as like: hdl```
|
38
|
+
## assign in_datas[0] = in_inf.data + 1;
|
39
|
+
## assign in_datas[1] = out_datas[0]+1;```
|
40
|
+
h.input[h.param.LAT,h.param.DSIZE].in_datas logic[3,18].origin_sync_info
|
41
|
+
h.output[h.param.LAT,h.param.DSIZE].out_datas logic[3,18].origin_sync_info_out
|
42
|
+
h.port.axis.slaver.in_inf origin_inf
|
43
|
+
h.port.axis.master.out_inf origin_inf.copy(name: 'origin_inf_post')
|
44
|
+
end
|
24
45
|
|
25
46
|
## 解析编码
|
47
|
+
## IN_DATA<0> IN_DATA<1> IN_DATA<2>
|
48
|
+
###[11:8] bytes_x_tmp bytes_x_sub_nDx route_addr_P
|
49
|
+
###[7 :4] bytes bytes_x_tmp_Q ???
|
50
|
+
###[3 :0] bytes bytes_Q ??
|
51
|
+
|
52
|
+
## OUT_DATA<0> OUT_DATA<1> IN_DATA<1>
|
53
|
+
###[11:8] bytes_x_tmp_Q bytes_x_sub_nDx_Q route_addr
|
54
|
+
###[7 :4] bytes_Q bytes_x_tmp_QQ ???
|
55
|
+
###[3 :0] bytes_Q bytes_QQ ??
|
56
|
+
|
57
|
+
## IN_DATA<0> IN_DATA<1> OUT<0> IN_DATA<2> OUT<1> OUT<2>
|
58
|
+
## |- bytes ------- | bytes_Q ---------- | bytes_QQ
|
59
|
+
## |> {bytes_x} -- | bytes_x ---------- | bytes_x_Q
|
60
|
+
## |> {bytes_x_sub_nDx} | bytes_x_sub_nDx
|
61
|
+
## |> {route_addr}-------- | route_addr
|
62
|
+
|
63
|
+
logic[10] - 'bytes_Q'
|
64
|
+
logic[10] - 'bytes_QQ'
|
26
65
|
logic[4] - 'bytes_x'
|
27
66
|
logic[4] - 'bytes_x_Q'
|
28
67
|
logic[4] - 'bytes_x_tmp'
|
29
68
|
logic[4] - 'bytes_x_sub_nDx'
|
69
|
+
logic[4] - 'bytes_x_sub_nDx_tmp'
|
30
70
|
logic[2] - 'route_addr'
|
71
|
+
logic[2] - 'route_addr_tmp'
|
72
|
+
# logic - 'route_addr_vld'
|
31
73
|
|
32
|
-
logic[4] - 'bytes_y'
|
33
|
-
logic[10] - 'tmp_loop'
|
34
|
-
|
35
|
-
# genvar - 'cc'
|
36
74
|
|
37
75
|
always_comb() do
|
38
|
-
# FOREACH(tmp_loop) do |ii|
|
39
|
-
# IF bytes < "#{param.DX}*(10-#{ii})".to_nq do
|
40
|
-
# bytes_x_tmp <= (10-1-ii)
|
41
|
-
# end
|
42
|
-
# end
|
43
76
|
bytes_x_tmp <= 0.A
|
44
77
|
FOR(start: 0,stop: 10) do |ii|
|
45
78
|
IF bytes < "#{param.DX}*(10-#{ii})".to_nq do
|
@@ -48,39 +81,62 @@ TdlBuild.axis_head_cut_verc(__dir__) do
|
|
48
81
|
end
|
49
82
|
end
|
50
83
|
|
51
|
-
|
52
|
-
|
53
|
-
|
54
|
-
|
55
|
-
|
56
|
-
|
57
|
-
|
58
|
-
|
59
|
-
|
60
|
-
|
61
|
-
|
84
|
+
Assign do
|
85
|
+
## --------IN<0>--
|
86
|
+
origin_sync_info[0] <= logic_bind_(bytes_x_tmp, bytes_x_tmp , bytes)
|
87
|
+
## ===============
|
88
|
+
## --------OUT<0>
|
89
|
+
logic_bind_(bytes_x, bytes_Q) <= logic_bind_(origin_sync_info_out[0][13,10], origin_sync_info_out[0][9,0])
|
90
|
+
## ==============
|
91
|
+
## --------IN<1>
|
92
|
+
bytes_x_sub_nDx_tmp <= bytes_Q - bytes_x*param.DX
|
93
|
+
origin_sync_info[1] <= logic_bind_(bytes_x_sub_nDx_tmp, bytes_x, bytes_Q)
|
94
|
+
## ==============
|
95
|
+
## --------OUT<1>
|
96
|
+
logic_bind_(bytes_x_sub_nDx, bytes_x_Q,bytes_QQ) <= logic_bind_(origin_sync_info_out[1][17,14],origin_sync_info_out[1][13,10], origin_sync_info_out[1][9,0])
|
97
|
+
## ==============
|
98
|
+
## --------IN<2>
|
99
|
+
origin_sync_info[2] <= logic_bind_(10.d0, route_addr_tmp)
|
100
|
+
## ==============
|
101
|
+
## --------OUT<2>
|
102
|
+
route_addr <= origin_sync_info_out[2][1,0]
|
103
|
+
## ==============
|
62
104
|
end
|
63
|
-
|
64
|
-
|
65
|
-
|
66
|
-
route_addr <= 0.A
|
105
|
+
always_comb do
|
106
|
+
IF bytes_QQ == 0.A do
|
107
|
+
route_addr_tmp <= 2.d0
|
67
108
|
end
|
68
|
-
|
69
|
-
|
70
|
-
|
71
|
-
|
72
|
-
|
73
|
-
route_addr <= 2.d2
|
74
|
-
end
|
75
|
-
ELSIF bytes_x_sub_nDx == 0.A do
|
76
|
-
route_addr <= 2.d1
|
77
|
-
end
|
78
|
-
ELSE do
|
79
|
-
route_addr <= 2.d1
|
80
|
-
end
|
109
|
+
ELSIF bytes_x_Q == 0.A do
|
110
|
+
route_addr_tmp <= 2.d2
|
111
|
+
end
|
112
|
+
ELSIF bytes_x_sub_nDx == 0.A do
|
113
|
+
route_addr_tmp <= 2.d1
|
81
114
|
end
|
115
|
+
ELSE do
|
116
|
+
route_addr_tmp <= 2.d1
|
117
|
+
end
|
82
118
|
end
|
83
119
|
|
120
|
+
# always_ff(posedge.clock ,negedge.rst_n) do
|
121
|
+
# IF ~rst_n do
|
122
|
+
# bytes_x <= 0.A
|
123
|
+
# bytes_x_Q <= 0.A
|
124
|
+
# bytes_x_sub_nDx <= 0.A
|
125
|
+
# bytes_x_vld <= 1.b0
|
126
|
+
# bytes_Q <= 0.A
|
127
|
+
# bytes_QQ <= 0.A
|
128
|
+
# end
|
129
|
+
# ELSE do
|
130
|
+
# bytes_Q <= bytes
|
131
|
+
# bytes_QQ <= bytes_Q
|
132
|
+
|
133
|
+
# bytes_x <= bytes_x_tmp
|
134
|
+
# bytes_x_Q <= bytes_x
|
135
|
+
|
136
|
+
# bytes_x_sub_nDx <= bytes_Q - bytes_x*param.DX
|
137
|
+
# bytes_x_vld <= origin_inf.vld_rdy
|
138
|
+
# end
|
139
|
+
# end
|
84
140
|
|
85
141
|
axi_stream_interconnect_S2M.axi_stream_interconnect_S2M_inst do |h| #(
|
86
142
|
h.param.NUM 3
|
@@ -11,7 +11,8 @@ madified:
|
|
11
11
|
`timescale 1ns/1ps
|
12
12
|
|
13
13
|
module axis_head_cut_verc #(
|
14
|
-
parameter BYTE_BITS = 8
|
14
|
+
parameter BYTE_BITS = 8,
|
15
|
+
parameter DX = origin_inf.DSIZE/BYTE_BITS
|
15
16
|
)(
|
16
17
|
input [9:0] bytes,
|
17
18
|
axi_stream_inf.slaver origin_inf,
|
@@ -20,16 +21,19 @@ module axis_head_cut_verc #(
|
|
20
21
|
|
21
22
|
//==========================================================================
|
22
23
|
//-------- define ----------------------------------------------------------
|
23
|
-
localparam DX = origin_inf.DSIZE/BYTE_BITS;
|
24
24
|
logic clock;
|
25
25
|
logic rst_n;
|
26
|
+
logic [18-1:0] origin_sync_info[3-1:0] ;
|
27
|
+
logic [18-1:0] origin_sync_info_out[3-1:0] ;
|
28
|
+
logic [10-1:0] bytes_Q ;
|
29
|
+
logic [10-1:0] bytes_QQ ;
|
26
30
|
logic [4-1:0] bytes_x ;
|
27
31
|
logic [4-1:0] bytes_x_Q ;
|
28
32
|
logic [4-1:0] bytes_x_tmp ;
|
29
33
|
logic [4-1:0] bytes_x_sub_nDx ;
|
34
|
+
logic [4-1:0] bytes_x_sub_nDx_tmp ;
|
30
35
|
logic [2-1:0] route_addr ;
|
31
|
-
logic [
|
32
|
-
logic [10-1:0] tmp_loop ;
|
36
|
+
logic [2-1:0] route_addr_tmp ;
|
33
37
|
logic fifo_wr_en;
|
34
38
|
logic [4-1:0] int_cut_len ;
|
35
39
|
logic [4-1:0] shift_sel_pre ;
|
@@ -41,14 +45,17 @@ axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss (.aclk(origin
|
|
41
45
|
axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_cut_mix (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
|
42
46
|
axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss_E0 (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
|
43
47
|
axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss_E0_CH (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
|
44
|
-
axi_stream_inf #(.DSIZE(out_inf.DSIZE),.USIZE(1))
|
48
|
+
axi_stream_inf #(.DSIZE(out_inf.DSIZE),.USIZE(1)) out_inf_branchR671 (.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1)) ;
|
45
49
|
//==========================================================================
|
46
50
|
//-------- instance --------------------------------------------------------
|
47
|
-
|
48
|
-
.
|
49
|
-
)
|
50
|
-
|
51
|
-
/*
|
51
|
+
axis_pipe_sync_seam #(
|
52
|
+
.LAT (3 ),
|
53
|
+
.DSIZE (18 )
|
54
|
+
)axis_pipe_sync_seam_inst(
|
55
|
+
/* input */.in_datas (origin_sync_info ),
|
56
|
+
/* output */.out_datas (origin_sync_info_out ),
|
57
|
+
/* axi_stream_inf.slaver */.in_inf (origin_inf ),
|
58
|
+
/* axi_stream_inf.master */.out_inf (origin_inf_post )
|
52
59
|
);
|
53
60
|
axi_stream_interconnect_S2M #(
|
54
61
|
.NUM (3 )
|
@@ -115,7 +122,7 @@ axis_connect_pipe_right_shift_verb #(
|
|
115
122
|
axis_head_cut_verb last_cut_inst(
|
116
123
|
/* input */.length (16'd1 ),
|
117
124
|
/* axi_stream_inf.slaver */.axis_in (origin_inf_ss_E0_CH ),
|
118
|
-
/* axi_stream_inf.master */.axis_out (
|
125
|
+
/* axi_stream_inf.master */.axis_out (out_inf_branchR671 )
|
119
126
|
);
|
120
127
|
//==========================================================================
|
121
128
|
//-------- expression ------------------------------------------------------
|
@@ -129,7 +136,7 @@ axis_direct axis_direct_out_inf_inst0 (
|
|
129
136
|
);
|
130
137
|
|
131
138
|
axis_direct axis_direct_out_inf_inst1 (
|
132
|
-
/* axi_stream_inf.slaver*/ .slaver (
|
139
|
+
/* axi_stream_inf.slaver*/ .slaver (out_inf_branchR671),
|
133
140
|
/* axi_stream_inf.master*/ .master (sub_out_inf[1])
|
134
141
|
);
|
135
142
|
|
@@ -160,41 +167,31 @@ always_comb begin
|
|
160
167
|
bytes_x_tmp = '0;
|
161
168
|
for(integer gvar_cc_1=0;gvar_cc_1<10;gvar_cc_1=gvar_cc_1+1)begin
|
162
169
|
if( bytes<DX*(10-gvar_cc_1))begin
|
163
|
-
bytes_x_tmp = ( 10-1-
|
170
|
+
bytes_x_tmp = ( ( 10-1)-gvar_cc_1);
|
164
171
|
end
|
165
172
|
end
|
166
173
|
end
|
167
174
|
|
168
|
-
|
169
|
-
|
170
|
-
|
171
|
-
|
172
|
-
|
175
|
+
assign origin_sync_info[0] = {bytes_x_tmp,bytes_x_tmp,bytes};
|
176
|
+
assign {bytes_x,bytes_Q} = {origin_sync_info_out[0][13:10],origin_sync_info_out[0][9:0]};
|
177
|
+
assign bytes_x_sub_nDx_tmp = ( bytes_Q-( bytes_x*DX));
|
178
|
+
assign origin_sync_info[1] = {bytes_x_sub_nDx_tmp,bytes_x,bytes_Q};
|
179
|
+
assign {bytes_x_sub_nDx,bytes_x_Q,bytes_QQ} = {origin_sync_info_out[1][17:14],origin_sync_info_out[1][13:10],origin_sync_info_out[1][9:0]};
|
180
|
+
assign origin_sync_info[2] = {10'd0,route_addr_tmp};
|
181
|
+
assign route_addr = origin_sync_info_out[2][1:0];
|
182
|
+
|
183
|
+
always_comb begin
|
184
|
+
if( bytes_QQ=='0)begin
|
185
|
+
route_addr_tmp = 2'd0;
|
173
186
|
end
|
174
|
-
else begin
|
175
|
-
|
176
|
-
bytes_x_Q <= bytes_x;
|
177
|
-
bytes_x_sub_nDx <= ( bytes-( bytes_x*DX));
|
187
|
+
else if( bytes_x_Q=='0)begin
|
188
|
+
route_addr_tmp = 2'd2;
|
178
189
|
end
|
179
|
-
|
180
|
-
|
181
|
-
always_ff@(posedge clock,negedge rst_n) begin
|
182
|
-
if(~rst_n)begin
|
183
|
-
route_addr <= '0;
|
190
|
+
else if( bytes_x_sub_nDx=='0)begin
|
191
|
+
route_addr_tmp = 2'd1;
|
184
192
|
end
|
185
193
|
else begin
|
186
|
-
|
187
|
-
route_addr <= 2'd0;
|
188
|
-
end
|
189
|
-
else if( bytes_x=='0)begin
|
190
|
-
route_addr <= 2'd2;
|
191
|
-
end
|
192
|
-
else if( bytes_x_sub_nDx=='0)begin
|
193
|
-
route_addr <= 2'd1;
|
194
|
-
end
|
195
|
-
else begin
|
196
|
-
route_addr <= 2'd1;
|
197
|
-
end
|
194
|
+
route_addr_tmp = 2'd1;
|
198
195
|
end
|
199
196
|
end
|
200
197
|
|