axi_tdl 0.0.4 → 0.0.9

data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.rb

@@ -0,0 +1,49 @@
+require_hdl 'data_c_pipe_sync.sv'
+
+TdlBuild.data_c_pipe_sync_seam(__dir__) do 
+    parameter.LAT       4 
+    parameter.DSIZE     32
+    ## as like: hdl``` 
+    ## assign in_datas[0] = in_inf.data + 1;
+    ## assign in_datas[1] = out_datas[0]+1;```
+    input[param.LAT,param.DSIZE]        - 'in_datas'    
+    output[param.LAT,param.DSIZE]       - 'out_datas'
+    port.data_inf_c.slaver              - 'in_inf'
+    port.data_inf_c.master              - 'out_inf'
+
+    same_clock_domain(in_inf, out_inf)
+
+    in_inf.copy(name: 'in_inf_array', dimension: [param.LAT])
+    out_inf.copy(name: 'out_inf_array', dimension: [param.LAT])
+
+    generate(param.LAT) do |kk|
+        data_c_pipe_sync.data_c_pipe_sync_inst do |h|
+            h.parameter.DSIZE           param.DSIZE 
+            h.input['DSIZE'].in_data    in_datas[kk]   ##// as like: hdl``` assign in_data = in_inf.data + 1;
+            h.output['DSIZE'].out_data  out_datas[kk]
+            h.port.data_inf_c.slaver.in_inf     in_inf_array[kk]
+            h.port.data_inf_c.master.out_inf    out_inf_array[kk]
+        end
+
+        IF kk != 0 do 
+            Assign do 
+                in_inf_array[kk].valid     <= out_inf_array[kk-1].valid
+                in_inf_array[kk].data      <= out_inf_array[kk-1].data
+                out_inf_array[kk-1].ready  <= in_inf_array[kk].ready
+            end     
+        end
+    end
+
+    Assign do 
+        in_inf_array[0].valid     <= in_inf.valid
+        in_inf_array[0].data      <= in_inf.data
+        in_inf.ready              <= in_inf_array[0].ready
+    end
+
+    Assign do 
+        out_inf.data  <= out_inf_array[param.LAT-1].data
+        out_inf.valid <= out_inf_array[param.LAT-1].valid
+        out_inf_array[param.LAT-1].ready    <= out_inf.ready
+    end
+
+end

data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv

@@ -0,0 +1,84 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: xxxx.xx.xx
+madified:
+***********************************************/
+`timescale 1ns/1ps
+
+module data_c_pipe_sync_seam #(
+    parameter  LAT   = 4,
+    parameter  DSIZE = 32
+)(
+    input [ DSIZE-1:0]  in_datas  [LAT-1:0],
+    output [ DSIZE-1:0] out_datas [LAT-1:0],
+    data_inf_c.slaver   in_inf,
+    data_inf_c.master   out_inf
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+
+data_inf_c #(.DSIZE(in_inf.DSIZE)) in_inf_array[LAT-1:0] (.clock(in_inf.clock),.rst_n(in_inf.rst_n)) ;
+data_inf_c #(.DSIZE(out_inf.DSIZE)) out_inf_array[LAT-1:0] (.clock(out_inf.clock),.rst_n(out_inf.rst_n)) ;
+//==========================================================================
+//-------- instance --------------------------------------------------------
+
+//==========================================================================
+//-------- expression ------------------------------------------------------
+generate
+for(genvar KK0=0;KK0 < LAT;KK0++)begin
+    data_c_pipe_sync #(
+        .DSIZE (DSIZE )
+    )data_c_pipe_sync_inst(
+    /* input             */.in_data  (in_datas[ KK0]      ),
+    /* output            */.out_data (out_datas[ KK0]     ),
+    /* data_inf_c.slaver */.in_inf   (in_inf_array[ KK0]  ),
+    /* data_inf_c.master */.out_inf  (out_inf_array[ KK0] )
+    );
+    if( KK0!=0)begin
+        assign  in_inf_array[ KK0].valid = out_inf_array[ KK0-1].valid;
+        assign  in_inf_array[ KK0].data = out_inf_array[ KK0-1].data;
+        assign  out_inf_array[ KK0-1].ready = in_inf_array[ KK0].ready;
+    end end
+endgenerate
+//-------- CLOCKs Total 2 ----------------------
+//--->> CheckClock <<----------------
+logic cc_done_10,cc_same_10;
+integer cc_afreq_10,cc_bfreq_10;
+ClockSameDomain CheckPClock_inst_10(
+/*  input         */      .aclk     (in_inf.clock           ),
+/*  input         */      .bclk     (out_inf.clock          ),
+/*  output logic  */      .done     (cc_done_10),
+/*  output logic  */      .same     (cc_same_10),
+/*  output integer */     .aFreqK   (cc_afreq_10),
+/*  output integer */     .bFreqK   (cc_bfreq_10)
+);
+
+initial begin
+    wait(cc_done_10);
+    assert(cc_same_10)
+    else begin
+        $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_10, 1000000.0/cc_bfreq_10);
+        repeat(10)begin 
+            @(posedge in_inf.clock);
+        end
+        $stop;
+    end
+end
+//---<< CheckClock >>----------------
+
+//======== CLOCKs Total 2 ======================
+assign  in_inf_array[0].valid = in_inf.valid;
+assign  in_inf_array[0].data = in_inf.data;
+assign  in_inf.ready = in_inf_array[0].ready;
+
+assign  out_inf.data = out_inf_array[ LAT-1].data;
+assign  out_inf.valid = out_inf_array[ LAT-1].valid;
+assign  out_inf_array[ LAT-1].ready = out_inf.ready;
+
+endmodule

data/lib/axi_tdl.rb

@@ -5,3 +5,23 @@ module AxiTdl
     AXI_PATH = File.expand_path(File.join(__dir__,"axi"))
     TDL_PATH = File.expand_path(File.join(__dir__,"tdl"))
 end
+
+
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/AXI_stream"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/AXI_stream/data_width"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/AXI_stream/stream_cache"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/AXI_stream/packet_fifo"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/AXI4"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/AXI4/axi4_pipe"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/AXI4/interconnect"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/AXI4/width_convert"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/AXI4/packet_partition"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/common_fifo"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/common"))
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/data_interface")) 
+add_to_tdl_paths    File.expand_path(File.join(__dir__, "axi/data_interface/data_inf_c"))
+
+## base require 
+require_hdl 'axis_master_empty.sv'
+require_hdl 'axis_slaver_empty.sv'
+

data/lib/axi_tdl/version.rb

@@ -1,3 +1,3 @@
 module AxiTdl
-  VERSION = "0.0.4"
+  VERSION = "0.0.9"
 end

data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb

@@ -6,6 +6,7 @@ self.real_sv_path = '/home/CookDarwin/work/fpga/axi/AXI_stream/packet_fifo/axi_s
 self.path = File.expand_path(__FILE__)
 parameter.DEPTH   2
 parameter.BYTE_DEPTH   8096
+parameter.USE_KEEP    "OFF"
 port.axi_stream_inf.slaver - 'axis_in' 
 port.axi_stream_inf.master - 'axis_out' 
 end

data/lib/tdl/SDL/path_lib.rb

@@ -2,5 +2,5 @@
 require_relative "./../global_scan"
 curr = File.expand_path(__FILE__)
 curr_path = File.dirname(curr)
-require_path(curr_path)
+# require_path(curr_path)
 # require_path_and_ignore(curr_path,"logic_condition.rb")

data/lib/tdl/SDL/vcs_axi4_comptable.rb

@@ -0,0 +1,9 @@
+sm = SdlModule.new(name:File.basename(__FILE__,".rb"))
+
+sm.Parameter("ORIGIN",'master')
+sm.Parameter("TO",'slaver')
+sm.Input("origin")
+sm.Output("to")
+
+sm.origin_sv = true
+sm.real_sv_path = File.expand_path(File.join(__dir__, "../../axi/AXI4/vcs_axi4_comptable.sv"))

data/lib/tdl/SDL/vcs_axis_comptable.rb

@@ -0,0 +1,17 @@
+# sm = SdlModule.new(name:File.basename(__FILE__,".rb"))
+
+# sm.Parameter("ORIGIN",'master')
+# sm.Parameter("TO",'slaver')
+# sm.Input("origin")
+# sm.Output("to")
+
+# sm.origin_sv = true
+
+sm = TdlBuild.vcs_axis_comptable do 
+    parameter.ORIGIN   'master'
+    parameter.TO        'slaver'
+    input   - 'origin'
+    output  - 'to'
+end 
+
+sm.real_sv_path = File.expand_path(File.join(__dir__, "../../axi/AXI_stream/vcs_axis_comptable.sv"))

data/lib/tdl/SDL/vcs_data_c_comptable.rb

@@ -0,0 +1,9 @@
+sm = SdlModule.new(name:File.basename(__FILE__,".rb"))
+
+sm.Parameter("ORIGIN",'master')
+sm.Parameter("TO",'slaver')
+sm.Input("origin")
+sm.Output("to")
+
+sm.origin_sv = true
+sm.real_sv_path = File.expand_path(File.join(__dir__, "../../axi/data_interface/data_inf_c/vcs_data_c_comptable.sv"))

data/lib/tdl/class_hdl/hdl_redefine_opertor.rb

@@ -58,9 +58,21 @@ module ClassHDL
                 # 计算生成新的OpertorChain 是 self 也需要抛弃
                 self.slaver = true
                 # return self
-                new_op =  OpertorChain.new 
-                new_op.tree = new_op.tree + self.tree
-                new_op.tree.push [b,os] 
+                new_op = nil
+                AssignDefOpertor.with_rollback_opertors(:old) do 
+                    if tree.size == 2 && tree.last[1].to_s == "<="
+                        new_op =  OpertorChain.new 
+                        new_op.tree = new_op.tree + self.tree
+                        new_op.tree.push [b,os] 
+                    elsif  tree.size >= 2 && (!['*',"/","~"].include?(tree.last[1].to_s))
+                        new_op =  brackets 
+                        new_op.tree.push [b,os] 
+                    else
+                        new_op =  OpertorChain.new 
+                        new_op.tree = new_op.tree + self.tree
+                        new_op.tree.push [b,os] 
+                    end 
+                end
 
                 if ClassHDL::AssignDefOpertor.curr_assign_block
                     ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)

data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv

@@ -9,6 +9,8 @@ created: xxxx.xx.xx
 madified:
 ***********************************************/
 `timescale 1ns/1ps
+`timescale 1ns/1ps
+`timescale 1ns/1ps
 
 module tb_exp_test_unit();
 //==========================================================================

data/lib/tdl/examples/2_hdl_class/module_def.rb

@@ -1,5 +1,6 @@
-require_relative '../../tdl.rb'
+require 'axi_tdl'
 # require_relative "./../../class_hdl/hdl_module_def.rb"
+require_hdl 'axi_stream_cache_35bit.sv'
 
 TdlBuild.test_module(File.join(__dir__,"tmp")) do 
     input.clock     - 'clock'

data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb

@@ -1,4 +1,6 @@
-require_relative '../../tdl.rb'
+require 'axi_tdl'
+require_hdl 'axi_stream_cache.sv'
+require_hdl 'axis_append_A1.sv'
 
 TdlBuild.test_inst_sugar(File.join(__dir__,"tmp")) do 
 

data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv

@@ -29,7 +29,7 @@ data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
 //==========================================================================
 //-------- expression ------------------------------------------------------
 always_ff@(posedge clock,negedge rst_n) begin 
-     32*2- 5- 6;
+     ( 32*2- 5)-6;
 end
 
 endmodule

data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv

@@ -35,7 +35,7 @@ function status(input [7:0] code,output logic [15:0] pl);
 endfunction:status
 
 function logic status_xp(input [7:0] code,output logic [15:0] pl); 
-     status_xp = ( inm!=0| ( inm!=1));
+     status_xp = ( ( inm!=0)|( inm!=1));
 endfunction:status_xp
 
 function SE_STATE_ctrl pre_status(input [7:0] code,output logic [15:0] pl,input SE_STATE_ctrl ll); 
@@ -47,6 +47,6 @@ endfunction:pre_status
 
 assign  gp = status(67, gp+1,opop);
 assign  gp = pre_status();
-assign  gp = ( inm!=0| ( inm!=1));
+assign  gp = ( ( inm!=0)|( inm!=1));
 
 endmodule

data/lib/tdl/examples/8_top_module/tb_test_top.sv

@@ -10,7 +10,6 @@ madified:
 ***********************************************/
 `timescale 1ns/1ps
 `timescale 1ns/1ps
-`timescale 1ns/1ps
 
 module tb_test_top();
 //==========================================================================

data/lib/tdl/examples/9_itegration/tb_test_tttop.sv

@@ -9,7 +9,6 @@ created: xxxx.xx.xx
 madified:
 ***********************************************/
 `timescale 1ns/1ps
-`timescale 1ns/1ps
 
 module tb_test_tttop();
 //==========================================================================

data/lib/tdl/exlib/test_point.rb

@@ -113,12 +113,18 @@ module TdlSpace
         def root_ref(&block)
             ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
                 rels = path_refs(&block)
+                if block_given?
+                    sst = "block given"
+                else
+                    sst = "no block"
+                end
+
                 if rels.size == 1
                     rels[0]
                 elsif rels.size == 0
-                    raise TdlError.new "#{self} Cant find root ref"
+                    raise TdlError.new "#{self} Cant find root ref {#{sst}}"
                 else
-                    raise TdlError.new "#{self} Find multi root refs \n#{rels.join("\n")}\n"
+                    raise TdlError.new "#{self} Find multi root refs {#{sst}} \n#{rels.join("\n")}\n"
                 end
             end
         end

data/lib/tdl/sdlmodule/sdlmodule.rb

@@ -404,4 +404,68 @@ class SdlModule
 
         Clock.same_clock(self, *objs_clks)
     end
+end
+
+## 获取 引用的所有文件
+class SdlModule
+
+    def __ref_children_modules__
+        curr_refs = []
+
+        @_import_packages_ ||= []
+        curr_refs << @_import_packages_
+
+        instance_and_children_module.values.each do |pm|
+            curr_refs << [pm, pm.__ref_children_modules__()]
+        end
+
+        return curr_refs
+    end
+
+    def ref_modules
+
+        curr_refs = __ref_children_modules__.flatten.uniq.reject do |e|
+            e.is_a?(ClassHDL::ClearSdlModule)
+        end
+        curr_refs << self
+    end
+
+    def self.base_hdl_ref
+        ## 基本接口引用
+        _base_refs = []
+        _base_refs << ['axi_inf', File.expand_path(File.join(__dir__, "../../axi/interface_define/axi_inf.sv"))]
+        _base_refs << ['axi_lite_inf', File.expand_path(File.join(__dir__, "../../axi/interface_define/axi_lite_inf.sv"))]
+        _base_refs << ['axi_stream', File.expand_path(File.join(__dir__, "../../axi/interface_define/axi_stream_inf.sv"))]
+        _base_refs << ['data_inf', File.expand_path(File.join(__dir__, "../../axi/data_interface/data_interface.sv"))]
+        _base_refs << ['data_inf_c', File.expand_path(File.join(__dir__, "../../axi/data_interface/data_interface_pkg.sv"))]
+        _base_refs << ['axi_bfm_pkg', File.expand_path(File.join(__dir__, "../../axi/AXI_BFM/AXI_BFM_PKG.sv"))]
+        _base_refs << ['cm_ram_inf', File.expand_path(File.join(__dir__, "../../tdl/rebuild_ele/cm_ram_inf.sv"))]
+        _base_refs << ['Lite_Addr_Data_CMD', File.expand_path(File.join(__dir__, "../../axi/AXI_Lite/gen_axi_lite_ctrl.sv"))]
+        _base_refs
+    end
+
+    def pretty_ref_hdl_moduls_echo
+        index = 1
+        _indexs = []
+        _names = []
+        _paths = []
+        max_size = 0
+        ref_modules.each do |e| 
+            _indexs << index 
+            _names << e.module_name
+            _paths << File.expand_path(e.real_sv_path)
+            index += 1
+            if e.module_name.size > max_size
+                max_size = e.module_name.size 
+            end
+        end
+        puts(pagination(" Modules of <#{module_name}> reference"))
+
+        # fstr = "[%#{index.to_s.size}d] %-#{ _names.map do |e| e.size end.max }s    %s"
+        fstr = "[%#{index.to_s.size}d] %-#{ max_size }s    %s"
+
+        (index-1).times do |xi|
+            puts (fstr % [_indexs[xi], _names[xi], _paths[xi]])
+        end
+    end
 end

data/lib/tdl/sdlmodule/sdlmodule_draw.rb

@@ -1,5 +1,18 @@
 ## read sdlmodule head
+class Tdl 
+    @@__head_logo__ = nil 
+    def self.head_logo 
+        @@__head_logo__
+    end
+
+    def self.head_logo=(a) 
+        $__sdlmodule_head_logo__ = a
+        @@__head_logo__ = a
+    end
+end
+
 $__sdlmodule_head_logo__ = File.open(File.join(__dir__,"sdlmodule_head_logo.txt")).read
+
 class SdlModule
     attr_accessor :origin_sv
 

data/lib/tdl/sdlmodule/top_module.rb

@@ -541,3 +541,4 @@ class SdlModule
 end
 
 
+

data/lib/tdl/tdl.rb

@@ -89,7 +89,11 @@ require_relative "./exlib/itegration"
 require_relative "./exlib/itegration_verb"
 require_relative "./exlib/parse_argv"
 # require_relative "./tdlmodule_ex"
-require_relative "./SDL/path_lib"     # require sdlmodule
+# require_relative "./SDL/path_lib"     # require sdlmodule
+## VSC COMPATABLE support 
+require_relative "./SDL/vcs_axi4_comptable.rb"
+require_relative "./SDL/vcs_data_c_comptable.rb"
+require_relative "./SDL/vcs_axis_comptable.rb"
 
 ## 添加 M2S方法
 require_relative "./axi_stream/axi_stream_interconnect.rb"
@@ -123,7 +127,7 @@ require_relative "./exlib/dve_tcl.rb"
 
 ## === INIT BLOCK Methods =====
 $argvs_hash = {}
-$argvs_hash = Parser.parse(ARGV) unless $_child_argv_
+$argvs_hash = Parser.parse($TdlARGV || ARGV) unless $_child_argv_
 TopModule.sim = $argvs_hash[:sim]
 
 class Tdl
@@ -254,6 +258,14 @@ class Tdl
         puts TopModule.current.test_unit.echo_units if TopModule.current
         puts(pagination("SUMMARY"))
         puts "#{TopModule.sim ? 'SIM' : 'SYNTH'} RUN SPEND #{Time.now - $__start_time__} sec @ TIME : #{Time.now}"
+
+        ## ----------- 
+        # TopModule.current.ref_modules.uniq.each do |e| 
+        #     unless  e.is_a? ClassHDL::ClearSdlModule
+        #         puts "#{e.real_sv_path}: #{e.module_name}"
+        #     end
+        # end
+        ## ===========
     end
 
 end