axi_tdl 0.0.4 → 0.0.9

checksums.yaml

@@ -1,7 +1,7 @@
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data/.gitignore

@@ -6,3 +6,5 @@
 /pkg/
 /spec/reports/
 /tmp/
+.rake_tasks~
+lib/tdl/auto_script/tmp/

data/Gemfile.lock

@@ -1,32 +1,18 @@
 PATH
   remote: .
   specs:
-    axi_tdl (0.0.4)
+    axi_tdl (0.0.9)
 
 GEM
   remote: https://rubygems.org/
   specs:
     coderay (1.1.3)
-    diff-lcs (1.4.4)
     method_source (1.0.0)
     minitest (5.14.3)
     pry (0.14.0)
       coderay (~> 1.1)
       method_source (~> 1.0)
     rake (10.5.0)
-    rspec (3.10.0)
-      rspec-core (~> 3.10.0)
-      rspec-expectations (~> 3.10.0)
-      rspec-mocks (~> 3.10.0)
-    rspec-core (3.10.1)
-      rspec-support (~> 3.10.0)
-    rspec-expectations (3.10.1)
-      diff-lcs (>= 1.2.0, < 2.0)
-      rspec-support (~> 3.10.0)
-    rspec-mocks (3.10.2)
-      diff-lcs (>= 1.2.0, < 2.0)
-      rspec-support (~> 3.10.0)
-    rspec-support (3.10.2)
 
 PLATFORMS
   ruby
@@ -37,7 +23,6 @@ DEPENDENCIES
   minitest
   pry
   rake (~> 10.0)
-  rspec
 
 BUNDLED WITH
    1.17.3

data/README.md

@@ -1,5 +1,11 @@
 # Axi
-  It is a wonderful library of axi4, but it is not full axi4, It is designed by systemverilog. I compact axi4 and add something to it. 
+  It is a wonderful library of axi4, but it is not full axi4, It is designed by systemverilog. I compact axi4 and add something to it.
+
+  axi hdl path
+```ruby
+require 'axi_tdl'
+AxiTdl::AXI_PATH
+```
 # Other
   It contain a simple interface that only define three signals, `valid`, `ready`, and `data`. I think it is useful for design. 
 

data/axi_tdl.gemspec

@@ -16,7 +16,7 @@ Gem::Specification.new do |spec|
   spec.license       = "LGPL-2.1"
   spec.files         = Dir['lib/**/*']
   spec.require_paths = ["lib"]
-
+  spec.required_ruby_version = '>= 2.5.0'
   # Prevent pushing this gem to RubyGems.org. To allow pushes either set the 'allowed_push_host'
   # to allow pushing to a single host or delete this section to allow pushing to any host.
   if spec.respond_to?(:metadata)
@@ -37,7 +37,7 @@ Gem::Specification.new do |spec|
 
   spec.add_development_dependency "bundler", "~> 1.16"
   spec.add_development_dependency "rake", "~> 10.0"
-  spec.add_development_dependency "rspec"
+  # spec.add_development_dependency "rspec"
   spec.add_development_dependency "pry"
   spec.add_development_dependency "minitest"
 end

data/lib/axi/AXI4/axi4_dpram_cache.rb

@@ -3,6 +3,7 @@ require_hdl File.join(__dir__,'full_axi4_to_axis_partition_wr_rd.sv')
 require_sdl 'common_ram_wrapper.rb'
 
 require_hdl File.join(__dir__,"./full_axi4_to_axis.sv")
+require_hdl 'data_inf_c_planer_A1.sv'
 
 TdlBuild.axi4_dpram_cache(__dir__) do 
     parameter.INIT_FILE     ''

data/lib/axi/AXI4/axi4_dpram_cache.sv

@@ -80,14 +80,14 @@ initial begin
 end
 
 assign  a_axis_inf.axis_tready = a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1] || (a_datac_rd_inf.ready && !a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1]);
-assign  a_datac_rd_inf.data = {a_axis_inf.axis_tlast,a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1- 1: a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE- 1]};
+assign  a_datac_rd_inf.data = {a_axis_inf.axis_tlast,a_axis_inf.axis_tdata[ ( a_inf.ASIZE+a_inf.DSIZE+1-1)-1: ( a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE)-1]};
 assign  a_datac_rd_inf.valid = a_axis_inf.axis_tvalid && !a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1];
 
 assign  a_axis_rd_inf.axis_tvalid = a_datac_rd_rel_inf.valid;
 assign  a_axis_rd_inf.axis_tdata = a_datac_rd_rel_inf.data[ a_inf.DSIZE-1:0];
 assign  a_axis_rd_inf.axis_tlast = a_datac_rd_rel_inf.data[ a_inf.ASIZE+a_inf.DSIZE+1-1];
 assign  a_datac_rd_rel_inf.ready = a_axis_rd_inf.axis_tready;
-assign  xram_inf.addra = a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1- 1: a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE- 1];
+assign  xram_inf.addra = a_axis_inf.axis_tdata[ ( a_inf.ASIZE+a_inf.DSIZE+1-1)-1: ( a_inf.ASIZE+a_inf.DSIZE+1-a_inf.ASIZE)-1];
 assign  xram_inf.dia = a_axis_inf.axis_tdata[ a_inf.DSIZE-1:0];
 assign  xram_inf.wea = {xram_inf.MSIZE{a_axis_inf.axis_tdata[ a_inf.ASIZE+a_inf.DSIZE+1-1]}};
 assign  xram_inf.ena = 1'b1;
@@ -95,14 +95,14 @@ assign  xram_inf.clka = a_inf.axi_aclk;
 assign  xram_inf.rsta = ~a_inf.axi_aresetn;
 
 assign  b_axis_inf.axis_tready = b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1] || (b_datac_rd_inf.ready && !b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1]);
-assign  b_datac_rd_inf.data = {b_axis_inf.axis_tlast,b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1- 1: b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE- 1]};
+assign  b_datac_rd_inf.data = {b_axis_inf.axis_tlast,b_axis_inf.axis_tdata[ ( b_inf.ASIZE+b_inf.DSIZE+1-1)-1: ( b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE)-1]};
 assign  b_datac_rd_inf.valid = b_axis_inf.axis_tvalid && !b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1];
 
 assign  b_axis_rd_inf.axis_tvalid = b_datac_rd_rel_inf.valid;
 assign  b_axis_rd_inf.axis_tdata = b_datac_rd_rel_inf.data[ b_inf.DSIZE-1:0];
 assign  b_axis_rd_inf.axis_tlast = b_datac_rd_rel_inf.data[ b_inf.ASIZE+b_inf.DSIZE+1-1];
 assign  b_datac_rd_rel_inf.ready = b_axis_rd_inf.axis_tready;
-assign  xram_inf.addrb = b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1- 1: b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE- 1];
+assign  xram_inf.addrb = b_axis_inf.axis_tdata[ ( b_inf.ASIZE+b_inf.DSIZE+1-1)-1: ( b_inf.ASIZE+b_inf.DSIZE+1-b_inf.ASIZE)-1];
 assign  xram_inf.dib = b_axis_inf.axis_tdata[ b_inf.DSIZE-1:0];
 assign  xram_inf.web = {xram_inf.MSIZE{b_axis_inf.axis_tdata[ b_inf.ASIZE+b_inf.DSIZE+1-1]}};
 assign  xram_inf.enb = 1'b1;

data/lib/axi/AXI4/axis_to_axi4_wr.rb

@@ -2,6 +2,11 @@
 
 ## raise TdlError.new("The module have be abandon\n    Path:[#{__dir__}]\n    Name:[#{__FILE__}]")
 
+require_hdl 'axis_length_split_with_addr.sv'
+require_hdl 'axi_stream_long_fifo.sv'
+require_hdl 'axi4_wr_auxiliary_gen_without_resp.sv'
+require_hdl 'axis_valve_with_pipe.sv'
+
 new_m = SdlModule.new(name:File.basename(__FILE__,".rb"),out_sv_path:__dir__)
 
 # Parameter :ADDR_STEP,1.0

data/lib/axi/AXI4/axis_to_axi4_wr.sv

@@ -56,7 +56,7 @@ logic stream_en;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) long_fifo_axis_out (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
 axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
-axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R442 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
+axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R1264 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
 axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
 //==========================================================================
 //-------- instance --------------------------------------------------------
@@ -92,16 +92,16 @@ independent_clock_fifo #(
 /* output */.full     (fifo_full                                                              )
 );
 axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
-/* output                        */.stream_en     (stream_en          ),
-/* axi_stream_inf.slaver         */.id_add_len_in (id_add_len_in      ),
-/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux    (axi_wr_vcs_cp_R442 )
+/* output                        */.stream_en     (stream_en           ),
+/* axi_stream_inf.slaver         */.id_add_len_in (id_add_len_in       ),
+/* axi_inf.master_wr_aux_no_resp */.axi_wr_aux    (axi_wr_vcs_cp_R1264 )
 );
 vcs_axi4_comptable #(
     .ORIGIN ("master_wr_aux_no_resp" ),
     .TO     ("master_wr"             )
-)vcs_axi4_comptable_axi_wr_aux_R1813_axi_wr_inst(
-/* input  */.origin (axi_wr_vcs_cp_R442 ),
-/* output */.to     (axi_wr             )
+)vcs_axi4_comptable_axi_wr_aux_R858_axi_wr_inst(
+/* input  */.origin (axi_wr_vcs_cp_R1264 ),
+/* output */.to     (axi_wr              )
 );
 axis_valve_with_pipe #(
     .MODE ("BOTH" )

data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv

@@ -86,7 +86,7 @@ always_ff@(posedge clock,negedge rst_n) begin
          wait_last_inf.ready <= 1'b0;
     end
     else begin
-         wait_last_inf.ready <= ( long_inf.axi_rvalid&long_inf.axi_rready& long_inf.axi_rlast);
+         wait_last_inf.ready <= ( ( long_inf.axi_rvalid&long_inf.axi_rready)&long_inf.axi_rlast);
     end
 end
 

data/lib/axi/AXI4/packet_partition/data_inf_partition.sv

@@ -31,7 +31,7 @@ logic one_long_stream;
 logic fifo_wr;
 logic [ IDSIZE+4-1:0]  curr_id ;
 logic [LSIZE-1:0]  curr_length ;
-logic [ data_in.DSIZE-IDSIZE- LSIZE-1:0]  curr_addr ;
+logic [ ( data_in.DSIZE-IDSIZE)-LSIZE-1:0]  curr_addr ;
 logic [LSIZE-1:0]  wr_length ;
 (* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_full;
 (* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_empty;
@@ -68,7 +68,7 @@ typedef enum {
 } SE_STATE_ps;
 SE_STATE_ps CSTATE_ps,NSTATE_ps;
 initial begin
-    assert( data_in.DSIZE+4== data_out.DSIZE)else begin
+    assert( ( data_in.DSIZE+4)==data_out.DSIZE)else begin
          $error("data_in.DSIZE<%d> != data_out.DSIZE<%d>",data_in.DSIZE,data_out.DSIZE);
          $stop;
     end

data/lib/axi/AXI_stream/axi_stream_latency.sv

@@ -0,0 +1,56 @@
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript: base on planer
+author : Cook.Darwin
+Version: VERA.0.0
+creaded: 
+madified:
+***********************************************/
+`timescale 1ns/1ps
+`include "define_macro.sv"
+module axi_stream_latency #(
+    parameter LAT   = 3
+)(
+    input                 reset,
+    axi_stream_inf.slaver axis_in,
+    axi_stream_inf.master axis_out        
+);
+
+data_inf_c #(.DSIZE(axis_in.DSIZE + 1 + axis_in.KSIZE + axis_in.USIZE)) data_slaver (.clock(axis_in.aclk), .rst_n(axis_in.aresetn) );
+data_inf_c #(.DSIZE(axis_in.DSIZE + 1 + axis_in.KSIZE + axis_in.USIZE + 1)) data_master (.clock(axis_in.aclk), .rst_n(axis_in.aresetn) );
+
+
+data_inf_c_planer_A1 #(
+    .LAT        (LAT        ),
+    .DSIZE      (1      ),
+    .HEAD       ("ON"    )
+)data_inf_c_planer_A1_inst(
+/*  input             */ .reset         (reset      ),
+/*  input [DSIZE-1:0] */ .pack_data     (1'b0       ),
+/*  data_inf_c.slaver */ .slaver        (data_slaver    ),
+/*  data_inf_c.master */ .master        (data_master    )///HEAD=="ON" : {pack_data,slaver.data} or /HEAD=="OFF" : {slaver.data,pack_data}
+);
+
+assign data_slaver.data  = {axis_in.axis_tuser, axis_in.axis_tkeep, axis_in.axis_tlast, axis_in.axis_tdata};
+assign data_slaver.valid = axis_in.axis_tvalid;
+assign axis_in.axis_tready = data_slaver.ready;
+
+// axis_to_data_inf #(
+//     .CONTAIN_LAST   ("ON")
+// )axis_to_data_inf_inst(
+// /*  axi_stream_inf.slaver  */ .axis_in      (axis_in        ),
+// /*  data_inf_c.master      */ .data_out_inf (data_slaver    )
+// );
+
+// data_c_to_axis_full data_c_to_axis_full_inst(
+// /* data_inf_c.slaver     */ .data_in_inf            (data_master    ),
+// /* axi_stream_inf.master */ .axis_out               (axis_out       )
+// );
+
+assign {axis_out.axis_tuser, axis_out.axis_tkeep, axis_out.axis_tlast, axis_out.axis_tdata} = data_master.data[data_master.DSIZE-2:0];
+assign axis_out.axis_tvalid = data_master.valid;
+assign data_master.ready    = axis_out.axis_tready;
+
+endmodule

data/lib/axi/AXI_stream/axi_stream_split_channel.sv

@@ -55,22 +55,22 @@ axis_direct  axis_direct_end_inf_inst0 (
 );
 //-------- CLOCKs Total 3 ----------------------
 //--->> CheckClock <<----------------
-logic cc_done_7,cc_same_7;
-integer cc_afreq_7,cc_bfreq_7;
-ClockSameDomain CheckPClock_inst_7(
+logic cc_done_8,cc_same_8;
+integer cc_afreq_8,cc_bfreq_8;
+ClockSameDomain CheckPClock_inst_8(
 /*  input         */      .aclk     (origin_inf.aclk        ),
 /*  input         */      .bclk     (first_inf.aclk         ),
-/*  output logic  */      .done     (cc_done_7),
-/*  output logic  */      .same     (cc_same_7),
-/*  output integer */     .aFreqK   (cc_afreq_7),
-/*  output integer */     .bFreqK   (cc_bfreq_7)
+/*  output logic  */      .done     (cc_done_8),
+/*  output logic  */      .same     (cc_same_8),
+/*  output integer */     .aFreqK   (cc_afreq_8),
+/*  output integer */     .bFreqK   (cc_bfreq_8)
 );
 
 initial begin
-    wait(cc_done_7);
-    assert(cc_same_7)
+    wait(cc_done_8);
+    assert(cc_same_8)
     else begin
-        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_7, 1000000.0/cc_bfreq_7);
+        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
         repeat(10)begin 
             @(posedge origin_inf.aclk);
         end
@@ -80,22 +80,22 @@ end
 //---<< CheckClock >>----------------
 
 //--->> CheckClock <<----------------
-logic cc_done_8,cc_same_8;
-integer cc_afreq_8,cc_bfreq_8;
-ClockSameDomain CheckPClock_inst_8(
+logic cc_done_9,cc_same_9;
+integer cc_afreq_9,cc_bfreq_9;
+ClockSameDomain CheckPClock_inst_9(
 /*  input         */      .aclk     (origin_inf.aclk        ),
 /*  input         */      .bclk     (end_inf.aclk           ),
-/*  output logic  */      .done     (cc_done_8),
-/*  output logic  */      .same     (cc_same_8),
-/*  output integer */     .aFreqK   (cc_afreq_8),
-/*  output integer */     .bFreqK   (cc_bfreq_8)
+/*  output logic  */      .done     (cc_done_9),
+/*  output logic  */      .same     (cc_same_9),
+/*  output integer */     .aFreqK   (cc_afreq_9),
+/*  output integer */     .bFreqK   (cc_bfreq_9)
 );
 
 initial begin
-    wait(cc_done_8);
-    assert(cc_same_8)
+    wait(cc_done_9);
+    assert(cc_same_9)
     else begin
-        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
+        $error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_9, 1000000.0/cc_bfreq_9);
         repeat(10)begin 
             @(posedge origin_inf.aclk);
         end

data/lib/axi/AXI_stream/axis_head_cut_verc.rb

@@ -1,5 +1,7 @@
 ## VERC 非整数型剪切,使用 right shift 
 require_hdl 'axis_connect_pipe_right_shift_verb.sv'
+# require_hdl 'axi_stream_latency.sv'
+require_sdl 'axis_pipe_sync_seam.rb'
 
 TdlBuild.axis_head_cut_verc(__dir__) do 
     parameter.BYTE_BITS     8
@@ -7,7 +9,7 @@ TdlBuild.axis_head_cut_verc(__dir__) do
     port.axis.slaver        - 'origin_inf'
     port.axis.master        - 'out_inf'
 
-    localparam.DX   (origin_inf.DSIZE / param.BYTE_BITS)
+    parameter.DX   (origin_inf.DSIZE / param.BYTE_BITS)
 
     Initial do 
         assert(param.DX < 17, "param.DX<%0d> !< 17",param.DX)
@@ -16,30 +18,61 @@ TdlBuild.axis_head_cut_verc(__dir__) do
 
     origin_inf.clock_reset_taps('clock', 'rst_n')
 
-    axis_slaver_pipe_A1.axis_slaver_pipe_A1_inst do |h| #(
-        h.param.DEPTH               3
-        h.port.axis.slaver.axis_in      origin_inf
-        h.port.axis.master.axis_out     origin_inf.copy(name: 'origin_inf_post')
-    end 
+    # axis_slaver_pipe_A1.axis_slaver_pipe_A1_inst do |h| #(
+    #     h.param.DEPTH               3
+    #     h.port.axis.slaver.axis_in      origin_inf
+    #     h.port.axis.master.axis_out     origin_inf.copy(name: 'origin_inf_post')
+    # end 
+
+    # axi_stream_latency.axi_stream_latency_inst do |h| #(
+    #     h.parameter.LAT                 3
+    #     h.input.reset                   1.b0
+    #     h.port.axis.slaver.axis_in      origin_inf
+    #     h.port.axis.master.axis_out     origin_inf.copy(name: 'origin_inf_post')   
+    # end
+
+    axis_pipe_sync_seam.axis_pipe_sync_seam_inst  do |h|
+        h.parameter.LAT       3 
+        h.parameter.DSIZE     10+4+4
+        ## as like: hdl``` 
+        ## assign in_datas[0] = in_inf.data + 1;
+        ## assign in_datas[1] = out_datas[0]+1;```
+        h.input[h.param.LAT,h.param.DSIZE].in_datas         logic[3,18].origin_sync_info
+        h.output[h.param.LAT,h.param.DSIZE].out_datas       logic[3,18].origin_sync_info_out
+        h.port.axis.slaver.in_inf                           origin_inf
+        h.port.axis.master.out_inf                          origin_inf.copy(name: 'origin_inf_post')   
+    end
 
     ## 解析编码
+    ##          IN_DATA<0>      IN_DATA<1>         IN_DATA<2>
+    ###[11:8]   bytes_x_tmp     bytes_x_sub_nDx    route_addr_P
+    ###[7 :4]   bytes           bytes_x_tmp_Q      ???
+    ###[3 :0]   bytes           bytes_Q            ??    
+    
+    ##          OUT_DATA<0>     OUT_DATA<1>       IN_DATA<1>
+    ###[11:8]   bytes_x_tmp_Q   bytes_x_sub_nDx_Q route_addr
+    ###[7 :4]   bytes_Q         bytes_x_tmp_QQ    ???
+    ###[3 :0]   bytes_Q         bytes_QQ          ?? 
+
+    ##             IN_DATA<0>       IN_DATA<1> OUT<0>     IN_DATA<2> OUT<1>         OUT<2>
+    ##          |- bytes  ------- | bytes_Q ----------  | bytes_QQ
+    ##          |> {bytes_x}   -- | bytes_x ----------  | bytes_x_Q
+    ##                            |> {bytes_x_sub_nDx}  | bytes_x_sub_nDx
+    ##                                                  |> {route_addr}-------- | route_addr 
+
+    logic[10]       - 'bytes_Q'
+    logic[10]       - 'bytes_QQ'
     logic[4]        - 'bytes_x'
     logic[4]        - 'bytes_x_Q'
     logic[4]        - 'bytes_x_tmp'
     logic[4]        - 'bytes_x_sub_nDx'
+    logic[4]        - 'bytes_x_sub_nDx_tmp'
     logic[2]        - 'route_addr'
+    logic[2]        - 'route_addr_tmp'
+    # logic           - 'route_addr_vld'
 
-    logic[4]        - 'bytes_y'
-    logic[10]       - 'tmp_loop'
-
-    # genvar - 'cc'
 
     always_comb() do  
-        # FOREACH(tmp_loop) do |ii|
-        #     IF bytes < "#{param.DX}*(10-#{ii})".to_nq do 
-        #         bytes_x_tmp <= (10-1-ii)
-        #     end
-        # end
         bytes_x_tmp <= 0.A
         FOR(start: 0,stop: 10) do |ii|
             IF bytes < "#{param.DX}*(10-#{ii})".to_nq do 
@@ -48,39 +81,62 @@ TdlBuild.axis_head_cut_verc(__dir__) do
         end
     end
 
-    always_ff(posedge.clock ,negedge.rst_n) do 
-        IF ~rst_n do 
-            bytes_x             <= 0.A 
-            bytes_x_Q           <= 0.A 
-            bytes_x_sub_nDx     <= 0.A
-        end 
-        ELSE do 
-            bytes_x             <= bytes_x_tmp
-            bytes_x_Q           <= bytes_x
-            bytes_x_sub_nDx     <= bytes - bytes_x*param.DX
-        end
+    Assign do 
+        ## --------IN<0>--
+        origin_sync_info[0]     <= logic_bind_(bytes_x_tmp, bytes_x_tmp , bytes)
+        ## ===============
+        ## --------OUT<0> 
+        logic_bind_(bytes_x, bytes_Q) <= logic_bind_(origin_sync_info_out[0][13,10], origin_sync_info_out[0][9,0])
+        ## ==============
+        ## --------IN<1>
+        bytes_x_sub_nDx_tmp <= bytes_Q - bytes_x*param.DX
+        origin_sync_info[1] <= logic_bind_(bytes_x_sub_nDx_tmp, bytes_x, bytes_Q)
+        ## ==============
+        ## --------OUT<1>
+        logic_bind_(bytes_x_sub_nDx, bytes_x_Q,bytes_QQ) <= logic_bind_(origin_sync_info_out[1][17,14],origin_sync_info_out[1][13,10], origin_sync_info_out[1][9,0])
+        ## ==============
+        ## --------IN<2>
+        origin_sync_info[2] <= logic_bind_(10.d0, route_addr_tmp)
+        ## ==============
+        ## --------OUT<2>
+        route_addr  <= origin_sync_info_out[2][1,0]
+        ## ==============
     end
-
-    always_ff(posedge.clock, negedge.rst_n) do 
-        IF ~rst_n do 
-            route_addr  <= 0.A 
+    always_comb do 
+        IF bytes_QQ == 0.A do 
+            route_addr_tmp  <= 2.d0 
         end
-        ELSE do 
-            IF bytes == 0.A do 
-                route_addr  <= 2.d0 
-            end
-            ELSIF bytes_x == 0.A do 
-                route_addr  <= 2.d2
-            end
-            ELSIF bytes_x_sub_nDx == 0.A do 
-                route_addr  <= 2.d1 
-            end
-            ELSE do 
-                route_addr  <= 2.d1
-            end 
+        ELSIF bytes_x_Q == 0.A do 
+            route_addr_tmp  <= 2.d2
+        end
+        ELSIF bytes_x_sub_nDx == 0.A do 
+            route_addr_tmp  <= 2.d1 
         end
+        ELSE do 
+            route_addr_tmp  <= 2.d1
+        end 
     end
 
+    # always_ff(posedge.clock ,negedge.rst_n) do 
+    #     IF ~rst_n do 
+    #         bytes_x             <= 0.A 
+    #         bytes_x_Q           <= 0.A 
+    #         bytes_x_sub_nDx     <= 0.A
+    #         bytes_x_vld         <= 1.b0
+    #         bytes_Q             <= 0.A 
+    #         bytes_QQ            <= 0.A 
+    #     end 
+    #     ELSE do 
+    #         bytes_Q             <= bytes
+    #         bytes_QQ            <= bytes_Q
+
+    #         bytes_x             <= bytes_x_tmp
+    #         bytes_x_Q           <= bytes_x
+
+    #         bytes_x_sub_nDx     <= bytes_Q - bytes_x*param.DX
+    #         bytes_x_vld         <= origin_inf.vld_rdy
+    #     end
+    # end
 
     axi_stream_interconnect_S2M.axi_stream_interconnect_S2M_inst do |h| #(
         h.param.NUM                         3