asmjit 0.2.0 → 0.2.2

Sign up to get free protection for your applications and to get access to all the features.
Files changed (204) hide show
  1. checksums.yaml +4 -4
  2. data/Gemfile.lock +1 -1
  3. data/Rakefile +5 -3
  4. data/asmjit.gemspec +1 -3
  5. data/ext/asmjit/asmjit/.editorconfig +10 -0
  6. data/ext/asmjit/asmjit/.github/FUNDING.yml +1 -0
  7. data/ext/asmjit/asmjit/.github/workflows/build-config.json +47 -0
  8. data/ext/asmjit/asmjit/.github/workflows/build.yml +156 -0
  9. data/ext/asmjit/asmjit/.gitignore +6 -0
  10. data/ext/asmjit/asmjit/CMakeLists.txt +611 -0
  11. data/ext/asmjit/asmjit/LICENSE.md +17 -0
  12. data/ext/asmjit/asmjit/README.md +69 -0
  13. data/ext/asmjit/asmjit/src/asmjit/a64.h +62 -0
  14. data/ext/asmjit/asmjit/src/asmjit/arm/a64archtraits_p.h +81 -0
  15. data/ext/asmjit/asmjit/src/asmjit/arm/a64assembler.cpp +5115 -0
  16. data/ext/asmjit/asmjit/src/asmjit/arm/a64assembler.h +72 -0
  17. data/ext/asmjit/asmjit/src/asmjit/arm/a64builder.cpp +51 -0
  18. data/ext/asmjit/asmjit/src/asmjit/arm/a64builder.h +57 -0
  19. data/ext/asmjit/asmjit/src/asmjit/arm/a64compiler.cpp +60 -0
  20. data/ext/asmjit/asmjit/src/asmjit/arm/a64compiler.h +247 -0
  21. data/ext/asmjit/asmjit/src/asmjit/arm/a64emithelper.cpp +464 -0
  22. data/ext/asmjit/asmjit/src/asmjit/arm/a64emithelper_p.h +50 -0
  23. data/ext/asmjit/asmjit/src/asmjit/arm/a64emitter.h +1228 -0
  24. data/ext/asmjit/asmjit/src/asmjit/arm/a64formatter.cpp +298 -0
  25. data/ext/asmjit/asmjit/src/asmjit/arm/a64formatter_p.h +59 -0
  26. data/ext/asmjit/asmjit/src/asmjit/arm/a64func.cpp +189 -0
  27. data/ext/asmjit/asmjit/src/asmjit/arm/a64func_p.h +33 -0
  28. data/ext/asmjit/asmjit/src/asmjit/arm/a64globals.h +1894 -0
  29. data/ext/asmjit/asmjit/src/asmjit/arm/a64instapi.cpp +278 -0
  30. data/ext/asmjit/asmjit/src/asmjit/arm/a64instapi_p.h +41 -0
  31. data/ext/asmjit/asmjit/src/asmjit/arm/a64instdb.cpp +1957 -0
  32. data/ext/asmjit/asmjit/src/asmjit/arm/a64instdb.h +74 -0
  33. data/ext/asmjit/asmjit/src/asmjit/arm/a64instdb_p.h +876 -0
  34. data/ext/asmjit/asmjit/src/asmjit/arm/a64operand.cpp +85 -0
  35. data/ext/asmjit/asmjit/src/asmjit/arm/a64operand.h +312 -0
  36. data/ext/asmjit/asmjit/src/asmjit/arm/a64rapass.cpp +852 -0
  37. data/ext/asmjit/asmjit/src/asmjit/arm/a64rapass_p.h +105 -0
  38. data/ext/asmjit/asmjit/src/asmjit/arm/a64utils.h +179 -0
  39. data/ext/asmjit/asmjit/src/asmjit/arm/armformatter.cpp +143 -0
  40. data/ext/asmjit/asmjit/src/asmjit/arm/armformatter_p.h +44 -0
  41. data/ext/asmjit/asmjit/src/asmjit/arm/armglobals.h +21 -0
  42. data/ext/asmjit/asmjit/src/asmjit/arm/armoperand.h +621 -0
  43. data/ext/asmjit/asmjit/src/asmjit/arm.h +62 -0
  44. data/ext/asmjit/asmjit/src/asmjit/asmjit-scope-begin.h +17 -0
  45. data/ext/asmjit/asmjit/src/asmjit/asmjit-scope-end.h +9 -0
  46. data/ext/asmjit/asmjit/src/asmjit/asmjit.h +33 -0
  47. data/ext/asmjit/asmjit/src/asmjit/core/api-build_p.h +55 -0
  48. data/ext/asmjit/asmjit/src/asmjit/core/api-config.h +613 -0
  49. data/ext/asmjit/asmjit/src/asmjit/core/archcommons.h +229 -0
  50. data/ext/asmjit/asmjit/src/asmjit/core/archtraits.cpp +160 -0
  51. data/ext/asmjit/asmjit/src/asmjit/core/archtraits.h +290 -0
  52. data/ext/asmjit/asmjit/src/asmjit/core/assembler.cpp +406 -0
  53. data/ext/asmjit/asmjit/src/asmjit/core/assembler.h +129 -0
  54. data/ext/asmjit/asmjit/src/asmjit/core/builder.cpp +889 -0
  55. data/ext/asmjit/asmjit/src/asmjit/core/builder.h +1391 -0
  56. data/ext/asmjit/asmjit/src/asmjit/core/codebuffer.h +113 -0
  57. data/ext/asmjit/asmjit/src/asmjit/core/codeholder.cpp +1149 -0
  58. data/ext/asmjit/asmjit/src/asmjit/core/codeholder.h +1035 -0
  59. data/ext/asmjit/asmjit/src/asmjit/core/codewriter.cpp +175 -0
  60. data/ext/asmjit/asmjit/src/asmjit/core/codewriter_p.h +179 -0
  61. data/ext/asmjit/asmjit/src/asmjit/core/compiler.cpp +582 -0
  62. data/ext/asmjit/asmjit/src/asmjit/core/compiler.h +737 -0
  63. data/ext/asmjit/asmjit/src/asmjit/core/compilerdefs.h +173 -0
  64. data/ext/asmjit/asmjit/src/asmjit/core/constpool.cpp +363 -0
  65. data/ext/asmjit/asmjit/src/asmjit/core/constpool.h +250 -0
  66. data/ext/asmjit/asmjit/src/asmjit/core/cpuinfo.cpp +1162 -0
  67. data/ext/asmjit/asmjit/src/asmjit/core/cpuinfo.h +813 -0
  68. data/ext/asmjit/asmjit/src/asmjit/core/emithelper.cpp +323 -0
  69. data/ext/asmjit/asmjit/src/asmjit/core/emithelper_p.h +58 -0
  70. data/ext/asmjit/asmjit/src/asmjit/core/emitter.cpp +333 -0
  71. data/ext/asmjit/asmjit/src/asmjit/core/emitter.h +741 -0
  72. data/ext/asmjit/asmjit/src/asmjit/core/emitterutils.cpp +129 -0
  73. data/ext/asmjit/asmjit/src/asmjit/core/emitterutils_p.h +89 -0
  74. data/ext/asmjit/asmjit/src/asmjit/core/environment.cpp +46 -0
  75. data/ext/asmjit/asmjit/src/asmjit/core/environment.h +508 -0
  76. data/ext/asmjit/asmjit/src/asmjit/core/errorhandler.cpp +14 -0
  77. data/ext/asmjit/asmjit/src/asmjit/core/errorhandler.h +228 -0
  78. data/ext/asmjit/asmjit/src/asmjit/core/formatter.cpp +584 -0
  79. data/ext/asmjit/asmjit/src/asmjit/core/formatter.h +247 -0
  80. data/ext/asmjit/asmjit/src/asmjit/core/formatter_p.h +34 -0
  81. data/ext/asmjit/asmjit/src/asmjit/core/func.cpp +286 -0
  82. data/ext/asmjit/asmjit/src/asmjit/core/func.h +1445 -0
  83. data/ext/asmjit/asmjit/src/asmjit/core/funcargscontext.cpp +293 -0
  84. data/ext/asmjit/asmjit/src/asmjit/core/funcargscontext_p.h +199 -0
  85. data/ext/asmjit/asmjit/src/asmjit/core/globals.cpp +133 -0
  86. data/ext/asmjit/asmjit/src/asmjit/core/globals.h +393 -0
  87. data/ext/asmjit/asmjit/src/asmjit/core/inst.cpp +113 -0
  88. data/ext/asmjit/asmjit/src/asmjit/core/inst.h +772 -0
  89. data/ext/asmjit/asmjit/src/asmjit/core/jitallocator.cpp +1242 -0
  90. data/ext/asmjit/asmjit/src/asmjit/core/jitallocator.h +261 -0
  91. data/ext/asmjit/asmjit/src/asmjit/core/jitruntime.cpp +80 -0
  92. data/ext/asmjit/asmjit/src/asmjit/core/jitruntime.h +89 -0
  93. data/ext/asmjit/asmjit/src/asmjit/core/logger.cpp +69 -0
  94. data/ext/asmjit/asmjit/src/asmjit/core/logger.h +198 -0
  95. data/ext/asmjit/asmjit/src/asmjit/core/misc_p.h +33 -0
  96. data/ext/asmjit/asmjit/src/asmjit/core/operand.cpp +132 -0
  97. data/ext/asmjit/asmjit/src/asmjit/core/operand.h +1611 -0
  98. data/ext/asmjit/asmjit/src/asmjit/core/osutils.cpp +84 -0
  99. data/ext/asmjit/asmjit/src/asmjit/core/osutils.h +61 -0
  100. data/ext/asmjit/asmjit/src/asmjit/core/osutils_p.h +68 -0
  101. data/ext/asmjit/asmjit/src/asmjit/core/raassignment_p.h +418 -0
  102. data/ext/asmjit/asmjit/src/asmjit/core/rabuilders_p.h +612 -0
  103. data/ext/asmjit/asmjit/src/asmjit/core/radefs_p.h +1204 -0
  104. data/ext/asmjit/asmjit/src/asmjit/core/ralocal.cpp +1166 -0
  105. data/ext/asmjit/asmjit/src/asmjit/core/ralocal_p.h +254 -0
  106. data/ext/asmjit/asmjit/src/asmjit/core/rapass.cpp +1969 -0
  107. data/ext/asmjit/asmjit/src/asmjit/core/rapass_p.h +1183 -0
  108. data/ext/asmjit/asmjit/src/asmjit/core/rastack.cpp +184 -0
  109. data/ext/asmjit/asmjit/src/asmjit/core/rastack_p.h +171 -0
  110. data/ext/asmjit/asmjit/src/asmjit/core/string.cpp +559 -0
  111. data/ext/asmjit/asmjit/src/asmjit/core/string.h +372 -0
  112. data/ext/asmjit/asmjit/src/asmjit/core/support.cpp +494 -0
  113. data/ext/asmjit/asmjit/src/asmjit/core/support.h +1773 -0
  114. data/ext/asmjit/asmjit/src/asmjit/core/target.cpp +14 -0
  115. data/ext/asmjit/asmjit/src/asmjit/core/target.h +53 -0
  116. data/ext/asmjit/asmjit/src/asmjit/core/type.cpp +74 -0
  117. data/ext/asmjit/asmjit/src/asmjit/core/type.h +419 -0
  118. data/ext/asmjit/asmjit/src/asmjit/core/virtmem.cpp +722 -0
  119. data/ext/asmjit/asmjit/src/asmjit/core/virtmem.h +242 -0
  120. data/ext/asmjit/asmjit/src/asmjit/core/zone.cpp +353 -0
  121. data/ext/asmjit/asmjit/src/asmjit/core/zone.h +615 -0
  122. data/ext/asmjit/asmjit/src/asmjit/core/zonehash.cpp +309 -0
  123. data/ext/asmjit/asmjit/src/asmjit/core/zonehash.h +186 -0
  124. data/ext/asmjit/asmjit/src/asmjit/core/zonelist.cpp +163 -0
  125. data/ext/asmjit/asmjit/src/asmjit/core/zonelist.h +209 -0
  126. data/ext/asmjit/asmjit/src/asmjit/core/zonestack.cpp +176 -0
  127. data/ext/asmjit/asmjit/src/asmjit/core/zonestack.h +239 -0
  128. data/ext/asmjit/asmjit/src/asmjit/core/zonestring.h +120 -0
  129. data/ext/asmjit/asmjit/src/asmjit/core/zonetree.cpp +99 -0
  130. data/ext/asmjit/asmjit/src/asmjit/core/zonetree.h +380 -0
  131. data/ext/asmjit/asmjit/src/asmjit/core/zonevector.cpp +356 -0
  132. data/ext/asmjit/asmjit/src/asmjit/core/zonevector.h +690 -0
  133. data/ext/asmjit/asmjit/src/asmjit/core.h +1861 -0
  134. data/ext/asmjit/asmjit/src/asmjit/x86/x86archtraits_p.h +148 -0
  135. data/ext/asmjit/asmjit/src/asmjit/x86/x86assembler.cpp +5110 -0
  136. data/ext/asmjit/asmjit/src/asmjit/x86/x86assembler.h +685 -0
  137. data/ext/asmjit/asmjit/src/asmjit/x86/x86builder.cpp +52 -0
  138. data/ext/asmjit/asmjit/src/asmjit/x86/x86builder.h +351 -0
  139. data/ext/asmjit/asmjit/src/asmjit/x86/x86compiler.cpp +61 -0
  140. data/ext/asmjit/asmjit/src/asmjit/x86/x86compiler.h +721 -0
  141. data/ext/asmjit/asmjit/src/asmjit/x86/x86emithelper.cpp +619 -0
  142. data/ext/asmjit/asmjit/src/asmjit/x86/x86emithelper_p.h +60 -0
  143. data/ext/asmjit/asmjit/src/asmjit/x86/x86emitter.h +4315 -0
  144. data/ext/asmjit/asmjit/src/asmjit/x86/x86formatter.cpp +944 -0
  145. data/ext/asmjit/asmjit/src/asmjit/x86/x86formatter_p.h +58 -0
  146. data/ext/asmjit/asmjit/src/asmjit/x86/x86func.cpp +503 -0
  147. data/ext/asmjit/asmjit/src/asmjit/x86/x86func_p.h +33 -0
  148. data/ext/asmjit/asmjit/src/asmjit/x86/x86globals.h +2169 -0
  149. data/ext/asmjit/asmjit/src/asmjit/x86/x86instapi.cpp +1732 -0
  150. data/ext/asmjit/asmjit/src/asmjit/x86/x86instapi_p.h +41 -0
  151. data/ext/asmjit/asmjit/src/asmjit/x86/x86instdb.cpp +4427 -0
  152. data/ext/asmjit/asmjit/src/asmjit/x86/x86instdb.h +563 -0
  153. data/ext/asmjit/asmjit/src/asmjit/x86/x86instdb_p.h +311 -0
  154. data/ext/asmjit/asmjit/src/asmjit/x86/x86opcode_p.h +436 -0
  155. data/ext/asmjit/asmjit/src/asmjit/x86/x86operand.cpp +231 -0
  156. data/ext/asmjit/asmjit/src/asmjit/x86/x86operand.h +1085 -0
  157. data/ext/asmjit/asmjit/src/asmjit/x86/x86rapass.cpp +1509 -0
  158. data/ext/asmjit/asmjit/src/asmjit/x86/x86rapass_p.h +94 -0
  159. data/ext/asmjit/asmjit/src/asmjit/x86.h +93 -0
  160. data/ext/asmjit/asmjit/src/asmjit.natvis +245 -0
  161. data/ext/asmjit/asmjit/test/asmjit_test_assembler.cpp +84 -0
  162. data/ext/asmjit/asmjit/test/asmjit_test_assembler.h +85 -0
  163. data/ext/asmjit/asmjit/test/asmjit_test_assembler_a64.cpp +4006 -0
  164. data/ext/asmjit/asmjit/test/asmjit_test_assembler_x64.cpp +17833 -0
  165. data/ext/asmjit/asmjit/test/asmjit_test_assembler_x86.cpp +8300 -0
  166. data/ext/asmjit/asmjit/test/asmjit_test_compiler.cpp +253 -0
  167. data/ext/asmjit/asmjit/test/asmjit_test_compiler.h +73 -0
  168. data/ext/asmjit/asmjit/test/asmjit_test_compiler_a64.cpp +690 -0
  169. data/ext/asmjit/asmjit/test/asmjit_test_compiler_x86.cpp +4317 -0
  170. data/ext/asmjit/asmjit/test/asmjit_test_emitters.cpp +197 -0
  171. data/ext/asmjit/asmjit/test/asmjit_test_instinfo.cpp +181 -0
  172. data/ext/asmjit/asmjit/test/asmjit_test_misc.h +257 -0
  173. data/ext/asmjit/asmjit/test/asmjit_test_perf.cpp +62 -0
  174. data/ext/asmjit/asmjit/test/asmjit_test_perf.h +61 -0
  175. data/ext/asmjit/asmjit/test/asmjit_test_perf_a64.cpp +699 -0
  176. data/ext/asmjit/asmjit/test/asmjit_test_perf_x86.cpp +5032 -0
  177. data/ext/asmjit/asmjit/test/asmjit_test_unit.cpp +172 -0
  178. data/ext/asmjit/asmjit/test/asmjit_test_x86_sections.cpp +172 -0
  179. data/ext/asmjit/asmjit/test/asmjitutils.h +38 -0
  180. data/ext/asmjit/asmjit/test/broken.cpp +312 -0
  181. data/ext/asmjit/asmjit/test/broken.h +148 -0
  182. data/ext/asmjit/asmjit/test/cmdline.h +61 -0
  183. data/ext/asmjit/asmjit/test/performancetimer.h +41 -0
  184. data/ext/asmjit/asmjit/tools/configure-makefiles.sh +13 -0
  185. data/ext/asmjit/asmjit/tools/configure-ninja.sh +13 -0
  186. data/ext/asmjit/asmjit/tools/configure-sanitizers.sh +13 -0
  187. data/ext/asmjit/asmjit/tools/configure-vs2019-x64.bat +2 -0
  188. data/ext/asmjit/asmjit/tools/configure-vs2019-x86.bat +2 -0
  189. data/ext/asmjit/asmjit/tools/configure-vs2022-x64.bat +2 -0
  190. data/ext/asmjit/asmjit/tools/configure-vs2022-x86.bat +2 -0
  191. data/ext/asmjit/asmjit/tools/configure-xcode.sh +8 -0
  192. data/ext/asmjit/asmjit/tools/enumgen.js +417 -0
  193. data/ext/asmjit/asmjit/tools/enumgen.sh +3 -0
  194. data/ext/asmjit/asmjit/tools/tablegen-arm.js +365 -0
  195. data/ext/asmjit/asmjit/tools/tablegen-arm.sh +3 -0
  196. data/ext/asmjit/asmjit/tools/tablegen-x86.js +2638 -0
  197. data/ext/asmjit/asmjit/tools/tablegen-x86.sh +3 -0
  198. data/ext/asmjit/asmjit/tools/tablegen.js +947 -0
  199. data/ext/asmjit/asmjit/tools/tablegen.sh +4 -0
  200. data/ext/asmjit/asmjit.cc +167 -30
  201. data/ext/asmjit/extconf.rb +9 -9
  202. data/lib/asmjit/version.rb +1 -1
  203. data/lib/asmjit.rb +14 -4
  204. metadata +198 -17
@@ -0,0 +1,563 @@
1
+ // This file is part of AsmJit project <https://asmjit.com>
2
+ //
3
+ // See asmjit.h or LICENSE.md for license and copyright information
4
+ // SPDX-License-Identifier: Zlib
5
+
6
+ #ifndef ASMJIT_X86_X86INSTDB_H_INCLUDED
7
+ #define ASMJIT_X86_X86INSTDB_H_INCLUDED
8
+
9
+ #include "../x86/x86globals.h"
10
+
11
+ ASMJIT_BEGIN_SUB_NAMESPACE(x86)
12
+
13
+ //! \addtogroup asmjit_x86
14
+ //! \{
15
+
16
+ //! Instruction database (X86).
17
+ namespace InstDB {
18
+
19
+ //! Describes which operation mode is supported by an instruction.
20
+ enum class Mode : uint8_t {
21
+ //! Invalid mode.
22
+ kNone = 0x00u,
23
+ //! X86 mode supported.
24
+ kX86 = 0x01u,
25
+ //! X64 mode supported.
26
+ kX64 = 0x02u,
27
+ //! Both X86 and X64 modes supported.
28
+ kAny = 0x03u
29
+ };
30
+ ASMJIT_DEFINE_ENUM_FLAGS(Mode)
31
+
32
+ //! Converts architecture to operation mode, see \ref Mode.
33
+ static constexpr Mode modeFromArch(Arch arch) noexcept {
34
+ return arch == Arch::kX86 ? Mode::kX86 :
35
+ arch == Arch::kX64 ? Mode::kX64 : Mode::kNone;
36
+ }
37
+
38
+ //! Operand signature flags used by \ref OpSignature.
39
+ enum class OpFlags : uint64_t {
40
+ //! No operand flags.
41
+ kNone = 0u,
42
+
43
+ kRegGpbLo = 0x0000000000000001u, //!< Operand can be low 8-bit GPB register.
44
+ kRegGpbHi = 0x0000000000000002u, //!< Operand can be high 8-bit GPB register.
45
+ kRegGpw = 0x0000000000000004u, //!< Operand can be 16-bit GPW register.
46
+ kRegGpd = 0x0000000000000008u, //!< Operand can be 32-bit GPD register.
47
+ kRegGpq = 0x0000000000000010u, //!< Operand can be 64-bit GPQ register.
48
+ kRegXmm = 0x0000000000000020u, //!< Operand can be 128-bit XMM register.
49
+ kRegYmm = 0x0000000000000040u, //!< Operand can be 256-bit YMM register.
50
+ kRegZmm = 0x0000000000000080u, //!< Operand can be 512-bit ZMM register.
51
+ kRegMm = 0x0000000000000100u, //!< Operand can be 64-bit MM register.
52
+ kRegKReg = 0x0000000000000200u, //!< Operand can be 64-bit K register.
53
+ kRegSReg = 0x0000000000000400u, //!< Operand can be SReg (segment register).
54
+ kRegCReg = 0x0000000000000800u, //!< Operand can be CReg (control register).
55
+ kRegDReg = 0x0000000000001000u, //!< Operand can be DReg (debug register).
56
+ kRegSt = 0x0000000000002000u, //!< Operand can be 80-bit ST register (X87).
57
+ kRegBnd = 0x0000000000004000u, //!< Operand can be 128-bit BND register.
58
+ kRegTmm = 0x0000000000008000u, //!< Operand can be 0..8192-bit TMM register.
59
+ kRegMask = 0x000000000000FFFFu, //!< Mask of all possible register types.
60
+
61
+ kMemUnspecified = 0x0000000000040000u, //!< Operand can be a scalar memory pointer without size.
62
+ kMem8 = 0x0000000000080000u, //!< Operand can be an 8-bit memory pointer.
63
+ kMem16 = 0x0000000000100000u, //!< Operand can be a 16-bit memory pointer.
64
+ kMem32 = 0x0000000000200000u, //!< Operand can be a 32-bit memory pointer.
65
+ kMem48 = 0x0000000000400000u, //!< Operand can be a 48-bit memory pointer (FAR pointers only).
66
+ kMem64 = 0x0000000000800000u, //!< Operand can be a 64-bit memory pointer.
67
+ kMem80 = 0x0000000001000000u, //!< Operand can be an 80-bit memory pointer.
68
+ kMem128 = 0x0000000002000000u, //!< Operand can be a 128-bit memory pointer.
69
+ kMem256 = 0x0000000004000000u, //!< Operand can be a 256-bit memory pointer.
70
+ kMem512 = 0x0000000008000000u, //!< Operand can be a 512-bit memory pointer.
71
+ kMem1024 = 0x0000000010000000u, //!< Operand can be a 1024-bit memory pointer.
72
+ kMemMask = 0x000000001FFC0000u, //!< Mask of all possible scalar memory types.
73
+
74
+ kVm32x = 0x0000000040000000u, //!< Operand can be a vm32x (vector) pointer.
75
+ kVm32y = 0x0000000080000000u, //!< Operand can be a vm32y (vector) pointer.
76
+ kVm32z = 0x0000000100000000u, //!< Operand can be a vm32z (vector) pointer.
77
+ kVm64x = 0x0000000200000000u, //!< Operand can be a vm64x (vector) pointer.
78
+ kVm64y = 0x0000000400000000u, //!< Operand can be a vm64y (vector) pointer.
79
+ kVm64z = 0x0000000800000000u, //!< Operand can be a vm64z (vector) pointer.
80
+ kVmMask = 0x0000000FC0000000u, //!< Mask of all possible vector memory types.
81
+
82
+ kImmI4 = 0x0000001000000000u, //!< Operand can be signed 4-bit immediate.
83
+ kImmU4 = 0x0000002000000000u, //!< Operand can be unsigned 4-bit immediate.
84
+ kImmI8 = 0x0000004000000000u, //!< Operand can be signed 8-bit immediate.
85
+ kImmU8 = 0x0000008000000000u, //!< Operand can be unsigned 8-bit immediate.
86
+ kImmI16 = 0x0000010000000000u, //!< Operand can be signed 16-bit immediate.
87
+ kImmU16 = 0x0000020000000000u, //!< Operand can be unsigned 16-bit immediate.
88
+ kImmI32 = 0x0000040000000000u, //!< Operand can be signed 32-bit immediate.
89
+ kImmU32 = 0x0000080000000000u, //!< Operand can be unsigned 32-bit immediate.
90
+ kImmI64 = 0x0000100000000000u, //!< Operand can be signed 64-bit immediate.
91
+ kImmU64 = 0x0000200000000000u, //!< Operand can be unsigned 64-bit immediate.
92
+ kImmMask = 0x00003FF000000000u, //!< Mask of all immediate types.
93
+
94
+ kRel8 = 0x0000400000000000u, //!< Operand can be relative 8-bit displacement.
95
+ kRel32 = 0x0000800000000000u, //!< Operand can be relative 32-bit displacement.
96
+ kRelMask = 0x0000C00000000000u, //!< Mask of all relative displacement types.
97
+
98
+ kFlagMemBase = 0x0001000000000000u, //!< Flag: Only memory base is allowed (no index, no offset).
99
+ kFlagMemDs = 0x0002000000000000u, //!< Flag: Implicit memory operand's DS segment.
100
+ kFlagMemEs = 0x0004000000000000u, //!< Flag: Implicit memory operand's ES segment.
101
+
102
+ kFlagMib = 0x0008000000000000u, //!< Flag: Operand is MIB (base+index) pointer.
103
+ kFlagTMem = 0x0010000000000000u, //!< Flag: Operand is TMEM (sib_mem), AMX memory pointer.
104
+
105
+ kFlagImplicit = 0x0080000000000000u, //!< Flag: Operand is implicit.
106
+ kFlagMask = 0x009F000000000000u, //!< Mask of all flags.
107
+
108
+ //! Contains mask of all registers, memory operands, immediate operands, and displacement operands.
109
+ kOpMask = kRegMask | kMemMask | kVmMask | kImmMask | kRelMask
110
+ };
111
+ ASMJIT_DEFINE_ENUM_FLAGS(OpFlags)
112
+
113
+ //! Operand signature.
114
+ //!
115
+ //! Contains all possible operand combinations, memory size information, and a fixed register id (or `BaseReg::kIdBad`
116
+ //! if fixed id isn't required).
117
+ struct OpSignature {
118
+ //! \name Members
119
+ //! \{
120
+
121
+ uint64_t _flags : 56;
122
+ uint64_t _regMask : 8;
123
+
124
+ //! \}
125
+
126
+ //! \name Accessors
127
+ //! \{
128
+
129
+ //! Returns operand signature flags.
130
+ inline OpFlags flags() const noexcept { return (OpFlags)_flags; }
131
+
132
+ //! Tests whether the given `flag` is set.
133
+ inline bool hasFlag(OpFlags flag) const noexcept { return (_flags & uint64_t(flag)) != 0; }
134
+
135
+ //! Tests whether this signature contains at least one register operand of any type.
136
+ inline bool hasReg() const noexcept { return hasFlag(OpFlags::kRegMask); }
137
+ //! Tests whether this signature contains at least one scalar memory operand of any type.
138
+ inline bool hasMem() const noexcept { return hasFlag(OpFlags::kMemMask); }
139
+ //! Tests whether this signature contains at least one vector memory operand of any type.
140
+ inline bool hasVm() const noexcept { return hasFlag(OpFlags::kVmMask); }
141
+ //! Tests whether this signature contains at least one immediate operand of any type.
142
+ inline bool hasImm() const noexcept { return hasFlag(OpFlags::kImmMask); }
143
+ //! Tests whether this signature contains at least one relative displacement operand of any type.
144
+ inline bool hasRel() const noexcept { return hasFlag(OpFlags::kRelMask); }
145
+
146
+ //! Tests whether the operand is implicit.
147
+ inline bool isImplicit() const noexcept { return hasFlag(OpFlags::kFlagImplicit); }
148
+
149
+ //! Returns a physical register mask.
150
+ inline RegMask regMask() const noexcept { return _regMask; }
151
+
152
+ //! \}
153
+ };
154
+
155
+ ASMJIT_VARAPI const OpSignature _opSignatureTable[];
156
+
157
+ //! Instruction signature.
158
+ //!
159
+ //! Contains a sequence of operands' combinations and other metadata that defines a single instruction. This data is
160
+ //! used by instruction validator.
161
+ struct InstSignature {
162
+ //! \name Members
163
+ //! \{
164
+
165
+ //! Count of operands in `opIndex` (0..6).
166
+ uint8_t _opCount : 3;
167
+ //! Architecture modes supported (X86 / X64).
168
+ uint8_t _mode : 2;
169
+ //! Number of implicit operands.
170
+ uint8_t _implicitOpCount : 3;
171
+ //! Reserved for future use.
172
+ uint8_t _reserved;
173
+ //! Indexes to `OpSignature` table.
174
+ uint8_t _opSignatureIndexes[Globals::kMaxOpCount];
175
+
176
+ //! \}
177
+
178
+ //! \name Accessors
179
+ //! \{
180
+
181
+ //! Returns instruction operation mode.
182
+ inline Mode mode() const noexcept { return (Mode)_mode; }
183
+ //! Tests whether the instruction supports the given operating mode.
184
+ inline bool supportsMode(Mode mode) const noexcept { return (uint8_t(_mode) & uint8_t(mode)) != 0; }
185
+
186
+ //! Returns the number of operands of this signature.
187
+ inline uint32_t opCount() const noexcept { return _opCount; }
188
+ //! Returns the number of implicit operands this signature has.
189
+ inline uint32_t implicitOpCount() const noexcept { return _implicitOpCount; }
190
+ //! Tests whether this instruction signature has at least one implicit operand.
191
+ inline bool hasImplicitOperands() const noexcept { return _implicitOpCount != 0; }
192
+
193
+ //! Returns indexes to \ref _opSignatureTable for each operand of the instruction.
194
+ //!
195
+ //! \note The returned array always provides indexes for all operands (see \ref Globals::kMaxOpCount) even if the
196
+ //! instruction provides less operands. Undefined operands have always index of zero.
197
+ inline const uint8_t* opSignatureIndexes() const noexcept { return _opSignatureIndexes; }
198
+
199
+ //! Returns index to \ref _opSignatureTable, corresponding to the requested operand `index` of the instruction.
200
+ inline uint8_t opSignatureIndex(size_t index) const noexcept {
201
+ ASMJIT_ASSERT(index < Globals::kMaxOpCount);
202
+ return _opSignatureIndexes[index];
203
+ }
204
+
205
+ //! Returns \ref OpSignature corresponding to the requested operand `index` of the instruction.
206
+ inline const OpSignature& opSignature(size_t index) const noexcept {
207
+ ASMJIT_ASSERT(index < Globals::kMaxOpCount);
208
+ return _opSignatureTable[_opSignatureIndexes[index]];
209
+ }
210
+
211
+ //! \}
212
+ };
213
+
214
+ ASMJIT_VARAPI const InstSignature _instSignatureTable[];
215
+
216
+ //! Instruction flags.
217
+ //!
218
+ //! Details about instruction encoding, operation, features, and some limitations.
219
+ enum class InstFlags : uint32_t {
220
+ //! No flags.
221
+ kNone = 0x00000000u,
222
+
223
+ // Instruction Family
224
+ // ------------------
225
+ //
226
+ // Instruction family information.
227
+
228
+ //! Instruction that accesses FPU registers.
229
+ kFpu = 0x00000100u,
230
+ //! Instruction that accesses MMX registers (including 3DNOW and GEODE) and EMMS.
231
+ kMmx = 0x00000200u,
232
+ //! Instruction that accesses XMM registers (SSE, AVX, AVX512).
233
+ kVec = 0x00000400u,
234
+
235
+ // FPU Flags
236
+ // ---------
237
+ //
238
+ // Used to tell the encoder which memory operand sizes are encodable.
239
+
240
+ //! FPU instruction can address `word_ptr` (shared with M80).
241
+ kFpuM16 = 0x00000800u,
242
+ //! FPU instruction can address `dword_ptr`.
243
+ kFpuM32 = 0x00001000u,
244
+ //! FPU instruction can address `qword_ptr`.
245
+ kFpuM64 = 0x00002000u,
246
+ //! FPU instruction can address `tword_ptr` (shared with M16).
247
+ kFpuM80 = 0x00000800u,
248
+
249
+ // Prefixes and Encoding Flags
250
+ // ---------------------------
251
+ //
252
+ // These describe optional X86 prefixes that can be used to change the instruction's operation.
253
+
254
+ //! Instruction can be prefixed with using the REP(REPE) or REPNE prefix.
255
+ kRep = 0x00004000u,
256
+ //! Rep prefix is accepted, but it has no effect other than being emitted with the instruction (as an extra byte).
257
+ kRepIgnored = 0x00008000u,
258
+ //! Instruction can be prefixed with using the LOCK prefix.
259
+ kLock = 0x00010000u,
260
+ //! Instruction can be prefixed with using the XACQUIRE prefix.
261
+ kXAcquire = 0x00020000u,
262
+ //! Instruction can be prefixed with using the XRELEASE prefix.
263
+ kXRelease = 0x00040000u,
264
+ //! Instruction uses MIB (BNDLDX|BNDSTX) to encode two registers.
265
+ kMib = 0x00080000u,
266
+ //! Instruction uses VSIB instead of legacy SIB.
267
+ kVsib = 0x00100000u,
268
+ //! Instruction uses TSIB (or SIB_MEM) encoding (MODRM followed by SIB).
269
+ kTsib = 0x00200000u,
270
+
271
+ // If both `kPrefixVex` and `kPrefixEvex` flags are specified it means that the instructions can be encoded
272
+ // by either VEX or EVEX prefix. In that case AsmJit checks global options and also instruction options to decide
273
+ // whether to emit VEX or EVEX prefix.
274
+
275
+ //! Instruction can be encoded by VEX|XOP (AVX|AVX2|BMI|XOP|...).
276
+ kVex = 0x00400000u,
277
+ //! Instruction can be encoded by EVEX (AVX512).
278
+ kEvex = 0x00800000u,
279
+ //! EVEX encoding is preferred over VEX encoding (AVX515_VNNI vs AVX_VNNI).
280
+ kPreferEvex = 0x01000000u,
281
+ //! EVEX and VEX signatures are compatible.
282
+ kEvexCompat = 0x02000000u,
283
+ //! EVEX instruction requires K register in the first operand (compare instructions).
284
+ kEvexKReg = 0x04000000u,
285
+ //! EVEX instruction requires two operands and K register as a selector (gather instructions).
286
+ kEvexTwoOp = 0x08000000u,
287
+ //! VEX instruction that can be transformed to a compatible EVEX instruction.
288
+ kEvexTransformable = 0x10000000u,
289
+
290
+ // Other Flags
291
+ // -----------
292
+
293
+ //! Instruction uses consecutive registers.
294
+ //!
295
+ //! Used by V4FMADDPS, V4FMADDSS, V4FNMADDPS, V4FNMADDSS, VP4DPWSSD, VP4DPWSSDS, VP2INTERSECTD, and VP2INTERSECTQ
296
+ //! instructions
297
+ kConsecutiveRegs = 0x20000000u
298
+ };
299
+ ASMJIT_DEFINE_ENUM_FLAGS(InstFlags)
300
+
301
+ //! AVX-512 flags.
302
+ enum class Avx512Flags : uint32_t {
303
+ //! No AVX-512 flags.
304
+ kNone = 0,
305
+
306
+ //! Internally used in tables, has no meaning.
307
+ k_ = 0x00000000u,
308
+ //! Supports masking {k1..k7}.
309
+ kK = 0x00000001u,
310
+ //! Supports zeroing {z}, must be used together with `kAvx512k`.
311
+ kZ = 0x00000002u,
312
+ //! Supports 'embedded-rounding' {er} with implicit {sae},
313
+ kER = 0x00000004u,
314
+ //! Supports 'suppress-all-exceptions' {sae}.
315
+ kSAE = 0x00000008u,
316
+ //! Supports 16-bit broadcast 'b16'.
317
+ kB16 = 0x00000010u,
318
+ //! Supports 32-bit broadcast 'b32'.
319
+ kB32 = 0x00000020u,
320
+ //! Supports 64-bit broadcast 'b64'.
321
+ kB64 = 0x00000040u,
322
+ //! Operates on a vector of consecutive registers (AVX512_4FMAPS and AVX512_4VNNIW).
323
+ kT4X = 0x00000080u,
324
+
325
+ //! Implicit zeroing if {k} masking is used. Using {z} is not valid in this case as it's implicit.
326
+ kImplicitZ = 0x00000100,
327
+ };
328
+ ASMJIT_DEFINE_ENUM_FLAGS(Avx512Flags)
329
+
330
+ //! Instruction common information.
331
+ //!
332
+ //! Aggregated information shared across one or more instruction.
333
+ struct CommonInfo {
334
+ //! Instruction flags.
335
+ uint32_t _flags;
336
+ //! Reserved for future use.
337
+ uint32_t _avx512Flags : 11;
338
+ //! First `InstSignature` entry in the database.
339
+ uint32_t _iSignatureIndex : 11;
340
+ //! Number of relevant `ISignature` entries.
341
+ uint32_t _iSignatureCount : 5;
342
+ //! Instruction control flow category, see \ref InstControlFlow.
343
+ uint32_t _controlFlow : 3;
344
+ //! Specifies what happens if all source operands share the same register.
345
+ uint32_t _sameRegHint : 2;
346
+
347
+ //! \name Accessors
348
+ //! \{
349
+
350
+ //! Returns instruction flags.
351
+ inline InstFlags flags() const noexcept { return (InstFlags)_flags; }
352
+ //! Tests whether the instruction has a `flag`.
353
+ inline bool hasFlag(InstFlags flag) const noexcept { return Support::test(_flags, flag); }
354
+
355
+ //! Returns instruction AVX-512 flags.
356
+ inline Avx512Flags avx512Flags() const noexcept { return (Avx512Flags)_avx512Flags; }
357
+ //! Tests whether the instruction has an AVX-512 `flag`.
358
+ inline bool hasAvx512Flag(Avx512Flags flag) const noexcept { return Support::test(_avx512Flags, flag); }
359
+
360
+ //! Tests whether the instruction is FPU instruction.
361
+ inline bool isFpu() const noexcept { return hasFlag(InstFlags::kFpu); }
362
+ //! Tests whether the instruction is MMX/3DNOW instruction that accesses MMX registers (includes EMMS and FEMMS).
363
+ inline bool isMmx() const noexcept { return hasFlag(InstFlags::kMmx); }
364
+ //! Tests whether the instruction is SSE|AVX|AVX512 instruction that accesses XMM|YMM|ZMM registers.
365
+ inline bool isVec() const noexcept { return hasFlag(InstFlags::kVec); }
366
+ //! Tests whether the instruction is SSE+ (SSE4.2, AES, SHA included) instruction that accesses XMM registers.
367
+ inline bool isSse() const noexcept { return (flags() & (InstFlags::kVec | InstFlags::kVex | InstFlags::kEvex)) == InstFlags::kVec; }
368
+ //! Tests whether the instruction is AVX+ (FMA included) instruction that accesses XMM|YMM|ZMM registers.
369
+ inline bool isAvx() const noexcept { return isVec() && isVexOrEvex(); }
370
+
371
+ //! Tests whether the instruction can be prefixed with LOCK prefix.
372
+ inline bool hasLockPrefix() const noexcept { return hasFlag(InstFlags::kLock); }
373
+ //! Tests whether the instruction can be prefixed with REP (REPE|REPZ) prefix.
374
+ inline bool hasRepPrefix() const noexcept { return hasFlag(InstFlags::kRep); }
375
+ //! Tests whether the instruction can be prefixed with XACQUIRE prefix.
376
+ inline bool hasXAcquirePrefix() const noexcept { return hasFlag(InstFlags::kXAcquire); }
377
+ //! Tests whether the instruction can be prefixed with XRELEASE prefix.
378
+ inline bool hasXReleasePrefix() const noexcept { return hasFlag(InstFlags::kXRelease); }
379
+
380
+ //! Tests whether the rep prefix is supported by the instruction, but ignored (has no effect).
381
+ inline bool isRepIgnored() const noexcept { return hasFlag(InstFlags::kRepIgnored); }
382
+ //! Tests whether the instruction uses MIB.
383
+ inline bool isMibOp() const noexcept { return hasFlag(InstFlags::kMib); }
384
+ //! Tests whether the instruction uses VSIB.
385
+ inline bool isVsibOp() const noexcept { return hasFlag(InstFlags::kVsib); }
386
+ //! Tests whether the instruction uses TSIB (AMX, instruction requires MOD+SIB).
387
+ inline bool isTsibOp() const noexcept { return hasFlag(InstFlags::kTsib); }
388
+ //! Tests whether the instruction uses VEX (can be set together with EVEX if both are encodable).
389
+ inline bool isVex() const noexcept { return hasFlag(InstFlags::kVex); }
390
+ //! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
391
+ inline bool isEvex() const noexcept { return hasFlag(InstFlags::kEvex); }
392
+ //! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
393
+ inline bool isVexOrEvex() const noexcept { return hasFlag(InstFlags::kVex | InstFlags::kEvex); }
394
+
395
+ //! Tests whether the instruction should prefer EVEX prefix instead of VEX prefix.
396
+ inline bool preferEvex() const noexcept { return hasFlag(InstFlags::kPreferEvex); }
397
+
398
+ inline bool isEvexCompatible() const noexcept { return hasFlag(InstFlags::kEvexCompat); }
399
+ inline bool isEvexKRegOnly() const noexcept { return hasFlag(InstFlags::kEvexKReg); }
400
+ inline bool isEvexTwoOpOnly() const noexcept { return hasFlag(InstFlags::kEvexTwoOp); }
401
+ inline bool isEvexTransformable() const noexcept { return hasFlag(InstFlags::kEvexTransformable); }
402
+
403
+ //! Tests whether the instruction supports AVX512 masking {k}.
404
+ inline bool hasAvx512K() const noexcept { return hasAvx512Flag(Avx512Flags::kK); }
405
+ //! Tests whether the instruction supports AVX512 zeroing {k}{z}.
406
+ inline bool hasAvx512Z() const noexcept { return hasAvx512Flag(Avx512Flags::kZ); }
407
+ //! Tests whether the instruction supports AVX512 embedded-rounding {er}.
408
+ inline bool hasAvx512ER() const noexcept { return hasAvx512Flag(Avx512Flags::kER); }
409
+ //! Tests whether the instruction supports AVX512 suppress-all-exceptions {sae}.
410
+ inline bool hasAvx512SAE() const noexcept { return hasAvx512Flag(Avx512Flags::kSAE); }
411
+ //! Tests whether the instruction supports AVX512 broadcast (either 32-bit or 64-bit).
412
+ inline bool hasAvx512B() const noexcept { return hasAvx512Flag(Avx512Flags::kB16 | Avx512Flags::kB32 | Avx512Flags::kB64); }
413
+ //! Tests whether the instruction supports AVX512 broadcast (16-bit).
414
+ inline bool hasAvx512B16() const noexcept { return hasAvx512Flag(Avx512Flags::kB16); }
415
+ //! Tests whether the instruction supports AVX512 broadcast (32-bit).
416
+ inline bool hasAvx512B32() const noexcept { return hasAvx512Flag(Avx512Flags::kB32); }
417
+ //! Tests whether the instruction supports AVX512 broadcast (64-bit).
418
+ inline bool hasAvx512B64() const noexcept { return hasAvx512Flag(Avx512Flags::kB64); }
419
+
420
+ // Returns the size of the broadcast - either 2, 4, or 8, or 0 if broadcast is not supported.
421
+ inline uint32_t broadcastSize() const noexcept {
422
+ constexpr uint32_t kShift = Support::ConstCTZ<uint32_t(Avx512Flags::kB16)>::value;
423
+ return (uint32_t(_avx512Flags) & uint32_t(Avx512Flags::kB16 | Avx512Flags::kB32 | Avx512Flags::kB64)) >> (kShift - 1);
424
+ }
425
+
426
+ inline uint32_t signatureIndex() const noexcept { return _iSignatureIndex; }
427
+ inline uint32_t signatureCount() const noexcept { return _iSignatureCount; }
428
+
429
+ inline const InstSignature* signatureData() const noexcept { return _instSignatureTable + _iSignatureIndex; }
430
+ inline const InstSignature* signatureEnd() const noexcept { return _instSignatureTable + _iSignatureIndex + _iSignatureCount; }
431
+
432
+ //! Returns a control flow category of the instruction.
433
+ inline InstControlFlow controlFlow() const noexcept { return (InstControlFlow)_controlFlow; }
434
+
435
+ //! Returns a hint that can be used when both inputs are the same register.
436
+ inline InstSameRegHint sameRegHint() const noexcept { return (InstSameRegHint)_sameRegHint; }
437
+
438
+ //! \}
439
+ };
440
+
441
+ ASMJIT_VARAPI const CommonInfo _commonInfoTable[];
442
+
443
+ //! Instruction information.
444
+ struct InstInfo {
445
+ //! Index to \ref _nameData.
446
+ uint32_t _nameDataIndex : 14;
447
+ //! Index to \ref _commonInfoTable.
448
+ uint32_t _commonInfoIndex : 10;
449
+ //! Index to \ref _additionalInfoTable.
450
+ uint32_t _additionalInfoIndex : 8;
451
+
452
+ //! Instruction encoding (internal encoding identifier used by \ref Assembler).
453
+ uint8_t _encoding;
454
+ //! Main opcode value (0..255).
455
+ uint8_t _mainOpcodeValue;
456
+ //! Index to \ref _mainOpcodeTable` that is combined with \ref _mainOpcodeValue to form the final opcode.
457
+ uint8_t _mainOpcodeIndex;
458
+ //! Index to \ref _altOpcodeTable that contains a full alternative opcode.
459
+ uint8_t _altOpcodeIndex;
460
+
461
+ //! \name Accessors
462
+ //! \{
463
+
464
+ //! Returns common information, see \ref CommonInfo.
465
+ inline const CommonInfo& commonInfo() const noexcept { return _commonInfoTable[_commonInfoIndex]; }
466
+
467
+ //! Returns instruction flags, see \ref Flags.
468
+ inline InstFlags flags() const noexcept { return commonInfo().flags(); }
469
+ //! Tests whether the instruction has flag `flag`, see \ref Flags.
470
+ inline bool hasFlag(InstFlags flag) const noexcept { return commonInfo().hasFlag(flag); }
471
+
472
+ //! Returns instruction AVX-512 flags, see \ref Avx512Flags.
473
+ inline Avx512Flags avx512Flags() const noexcept { return commonInfo().avx512Flags(); }
474
+ //! Tests whether the instruction has an AVX-512 `flag`, see \ref Avx512Flags.
475
+ inline bool hasAvx512Flag(Avx512Flags flag) const noexcept { return commonInfo().hasAvx512Flag(flag); }
476
+
477
+ //! Tests whether the instruction is FPU instruction.
478
+ inline bool isFpu() const noexcept { return commonInfo().isFpu(); }
479
+ //! Tests whether the instruction is MMX/3DNOW instruction that accesses MMX registers (includes EMMS and FEMMS).
480
+ inline bool isMmx() const noexcept { return commonInfo().isMmx(); }
481
+ //! Tests whether the instruction is SSE|AVX|AVX512 instruction that accesses XMM|YMM|ZMM registers.
482
+ inline bool isVec() const noexcept { return commonInfo().isVec(); }
483
+ //! Tests whether the instruction is SSE+ (SSE4.2, AES, SHA included) instruction that accesses XMM registers.
484
+ inline bool isSse() const noexcept { return commonInfo().isSse(); }
485
+ //! Tests whether the instruction is AVX+ (FMA included) instruction that accesses XMM|YMM|ZMM registers.
486
+ inline bool isAvx() const noexcept { return commonInfo().isAvx(); }
487
+
488
+ //! Tests whether the instruction can be prefixed with LOCK prefix.
489
+ inline bool hasLockPrefix() const noexcept { return commonInfo().hasLockPrefix(); }
490
+ //! Tests whether the instruction can be prefixed with REP (REPE|REPZ) prefix.
491
+ inline bool hasRepPrefix() const noexcept { return commonInfo().hasRepPrefix(); }
492
+ //! Tests whether the instruction can be prefixed with XACQUIRE prefix.
493
+ inline bool hasXAcquirePrefix() const noexcept { return commonInfo().hasXAcquirePrefix(); }
494
+ //! Tests whether the instruction can be prefixed with XRELEASE prefix.
495
+ inline bool hasXReleasePrefix() const noexcept { return commonInfo().hasXReleasePrefix(); }
496
+
497
+ //! Tests whether the rep prefix is supported by the instruction, but ignored (has no effect).
498
+ inline bool isRepIgnored() const noexcept { return commonInfo().isRepIgnored(); }
499
+ //! Tests whether the instruction uses MIB.
500
+ inline bool isMibOp() const noexcept { return hasFlag(InstFlags::kMib); }
501
+ //! Tests whether the instruction uses VSIB.
502
+ inline bool isVsibOp() const noexcept { return hasFlag(InstFlags::kVsib); }
503
+ //! Tests whether the instruction uses VEX (can be set together with EVEX if both are encodable).
504
+ inline bool isVex() const noexcept { return hasFlag(InstFlags::kVex); }
505
+ //! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
506
+ inline bool isEvex() const noexcept { return hasFlag(InstFlags::kEvex); }
507
+ //! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
508
+ inline bool isVexOrEvex() const noexcept { return hasFlag(InstFlags::kVex | InstFlags::kEvex); }
509
+
510
+ inline bool isEvexCompatible() const noexcept { return hasFlag(InstFlags::kEvexCompat); }
511
+ inline bool isEvexKRegOnly() const noexcept { return hasFlag(InstFlags::kEvexKReg); }
512
+ inline bool isEvexTwoOpOnly() const noexcept { return hasFlag(InstFlags::kEvexTwoOp); }
513
+ inline bool isEvexTransformable() const noexcept { return hasFlag(InstFlags::kEvexTransformable); }
514
+
515
+ //! Tests whether the instruction supports AVX512 masking {k}.
516
+ inline bool hasAvx512K() const noexcept { return hasAvx512Flag(Avx512Flags::kK); }
517
+ //! Tests whether the instruction supports AVX512 zeroing {k}{z}.
518
+ inline bool hasAvx512Z() const noexcept { return hasAvx512Flag(Avx512Flags::kZ); }
519
+ //! Tests whether the instruction supports AVX512 embedded-rounding {er}.
520
+ inline bool hasAvx512ER() const noexcept { return hasAvx512Flag(Avx512Flags::kER); }
521
+ //! Tests whether the instruction supports AVX512 suppress-all-exceptions {sae}.
522
+ inline bool hasAvx512SAE() const noexcept { return hasAvx512Flag(Avx512Flags::kSAE); }
523
+ //! Tests whether the instruction supports AVX512 broadcast (either 32-bit or 64-bit).
524
+ inline bool hasAvx512B() const noexcept { return hasAvx512Flag(Avx512Flags::kB16 | Avx512Flags::kB32 | Avx512Flags::kB64); }
525
+ //! Tests whether the instruction supports AVX512 broadcast (16-bit).
526
+ inline bool hasAvx512B16() const noexcept { return hasAvx512Flag(Avx512Flags::kB16); }
527
+ //! Tests whether the instruction supports AVX512 broadcast (32-bit).
528
+ inline bool hasAvx512B32() const noexcept { return hasAvx512Flag(Avx512Flags::kB32); }
529
+ //! Tests whether the instruction supports AVX512 broadcast (64-bit).
530
+ inline bool hasAvx512B64() const noexcept { return hasAvx512Flag(Avx512Flags::kB64); }
531
+
532
+ //! Returns a control flow category of the instruction.
533
+ inline InstControlFlow controlFlow() const noexcept { return commonInfo().controlFlow(); }
534
+ //! Returns a hint that can be used when both inputs are the same register.
535
+ inline InstSameRegHint sameRegHint() const noexcept { return commonInfo().sameRegHint(); }
536
+
537
+ inline uint32_t signatureIndex() const noexcept { return commonInfo().signatureIndex(); }
538
+ inline uint32_t signatureCount() const noexcept { return commonInfo().signatureCount(); }
539
+
540
+ inline const InstSignature* signatureData() const noexcept { return commonInfo().signatureData(); }
541
+ inline const InstSignature* signatureEnd() const noexcept { return commonInfo().signatureEnd(); }
542
+
543
+ //! \}
544
+ };
545
+
546
+ ASMJIT_VARAPI const InstInfo _instInfoTable[];
547
+
548
+ static inline const InstInfo& infoById(InstId instId) noexcept {
549
+ ASMJIT_ASSERT(Inst::isDefinedId(instId));
550
+ return _instInfoTable[instId];
551
+ }
552
+
553
+ //! \cond INTERNAL
554
+ static_assert(sizeof(OpSignature) == 8, "InstDB::OpSignature must be 8 bytes long");
555
+ //! \endcond
556
+
557
+ } // {InstDB}
558
+
559
+ //! \}
560
+
561
+ ASMJIT_END_SUB_NAMESPACE
562
+
563
+ #endif // ASMJIT_X86_X86INSTDB_H_INCLUDED