HDLRuby 3.9.5 → 3.9.7

data/lib/HDLRuby/hruby_verilog.rb

@@ -1562,10 +1562,14 @@ module HDLRuby::Low
         # Converts the system to Verilog code.
         def to_verilog
             # if self.base.name.to_s != "bit"
+            first = self.range.first
+            first = first.to_verilog if first.is_a?(Expression)
+            last = self.range.last
+            last = last.to_verilog if last.is_a?(Expression)
             if VERILOG_BASE_TYPES.include?(self.base.name.to_s)
-                return " #{self.base.name.to_s}[#{self.range.first}:#{self.range.last}]"
+              return " #{self.base.name.to_s}[#{first}:#{last}]"
             end
-            return " [#{self.range.first}:#{self.range.last}]"
+            return " [#{first}:#{last}]"
         end
     end
 
@@ -1630,9 +1634,9 @@ module HDLRuby::Low
             res = ""
             sels = self.select.to_verilog
             @choices[0..-2].each_with_index do |choice,i|
-                res << "#{sels} == #{i} ? #{choice.to_verilog} : "
+                res << "(#{sels} == #{i} ? #{choice.to_verilog} : "
             end
-            res << @choices[-1].to_verilog
+            res << @choices[-1].to_verilog + (")" * @choices[0..-2].size)
             return res
         end
     end
@@ -1676,6 +1680,9 @@ module HDLRuby::Low
                 # return "#{self.type.width}'b#{str}"
             else
                 str = self.content.to_verilog
+                if str.length > self.type.width then
+                  str = str[str.length-self.type.width..-1]
+                end
                 if self.content.negative? then
                     return "#{str.length}'sb#{str}"
                 else
@@ -1738,7 +1745,11 @@ module HDLRuby::Low
 
             result = " " * spc # Indented based on space_count.
 
-            result << "case(#{self.value.to_verilog})\n"
+            if @mode == :casez then
+              result << "casez(#{self.value.to_verilog})\n"
+            else
+              result << "case(#{self.value.to_verilog})\n"
+            end
 
             # n the case statement, each branch is partitioned by when. Process each time when.
             self.each_when do |whens| 
@@ -2150,7 +2161,7 @@ module HDLRuby::Low
             inout = self.each_inout.to_a
 
             # Spelling necessary for simulation.
-            code = "`timescale 1ps/1ps\n\n"
+            code = "`timescale 10ps/1ps\n\n"
 
             # self.properties[:verilog_name] = vname
             # Output the module name.

data/lib/HDLRuby/std/decoder.rb

@@ -131,10 +131,10 @@ module HDLRuby::High::Std
             format = format.to_s
             width = format.size
             # For that purpose create the regular expression used to process it.
-            prs = "([0-1]+)|(a+)|(b+)|(c+)|(d+)|(e+)|(g+)|(h+)|(i+)|(j+)|(k+)|(l+)|(m+)|(n+)|(o+)|(p+)|(q+)|(r+)|(s+)|(t+)|(u+)|(v+)|(w+)|(x+)|(y+)|(z+)"
+            prs = "([0-1]+)|(a+)|(b+)|(c+)|(d+)|(e+)|(f+)|(g+)|(h+)|(i+)|(j+)|(k+)|(l+)|(m+)|(n+)|(o+)|(p+)|(q+)|(r+)|(s+)|(t+)|(u+)|(v+)|(w+)|(x+)|(y+)|(z+)"
             # Check if the format is compatible with it.
             unless format =~ Regexp.new("^(#{prs})+$") then
-                raise AnyError("Invalid format for a field: #{format}")
+                raise AnyError, "Invalid format for a field: #{format}"
             end
             # Split the format in fields.
             format = format.split(Regexp.new(prs)).select {|str| !str.empty?}
@@ -182,6 +182,76 @@ module HDLRuby::High::Std
     end
 
 
+    ##
+    # Class for building an expression decoder.
+    #
+    class EDecoderMaker
+      # Create a new decoder generator for input +sig+ that returns an
+      # array of bits for each value from +vals+ that matches given as
+      # subsequent arguments.
+      # Note: supports chaining using the call operator in wich case
+      # [sig,*value] is treated as a composite input signal and each set
+      # of values is given by the susequent call.
+      def initialize(sig,*values)
+        @sig = sig
+        @values = values
+        if @values.last.is_a?(::Symbol) then
+          @op = @values.pop
+        else
+          @op = :&
+        end
+        @targets = nil
+      end
+
+      # Add a decoder line in composite case.
+      # +target+ is the target bit and +set+ is the of values which sets
+      # the target
+      def call(target,set)
+        if @targets then
+          # Already composite, add the values.
+          @targets << target
+          @values << set
+        else
+          # Transform the decoder with composite values.
+          @sig = [ @sig, *@values ]
+          @targets = [ target ]
+          @values = [ set ]
+        end
+
+        # Generate the decode line.
+        target <= @sig.map.with_index do |sig,i|
+          set[i] ? (sig.to_expr == set[i]).as(HDLRuby::High.bit) : HDLRuby::High.top_user._b1
+        end.reduce(@op)
+
+        return self
+      end
+
+      # Convert the expression if to an expression mux.
+      def to_expr
+        raise "Not an expression decoder." if @targets
+        return @values.map do |set|
+          (@sig.to_expr == set).as(HDLRuby::High.bit)
+        end.to_expr
+      end
+
+      [:"-@",:"+@",:"~", :abs,
+       :boolean, :bit, :signed, :unsigned].each do |operator|
+         define_method(operator) do
+           self.to_expr.send(operator)
+         end
+       end
+
+      [:"+",:"-",:"*",:"/",:"%",:"**",
+       :"&",:"|",:"^",
+       :"<<",:">>",# :ls,:rs,:lr,:rr, # ls, rs lr and rr are treated separately
+       :"==",:"!=",:"<",:">",:"<=",:">="].each do |operator|
+         define_method(operator) do |expr|
+           self.to_expr.send(operator,expr)
+         end
+       end
+
+    end
+
 
 
     ## Declare a new decoder.
@@ -192,6 +262,11 @@ module HDLRuby::High::Std
     #
     #  If provided, +ruby_block+ the fsm is directly instantiated with it.
     def decoder(*args, &ruby_block)
+        # Is it an expression decoder?
+        unless ruby_block then
+          # Yes.
+          return EDecoderMaker.new(*args)
+        end
         # Sets the name if any
         unless args[0].respond_to?(:to_expr) then
             name = args.shift.to_sym

data/lib/HDLRuby/std/hruby_enum.rb

@@ -1261,4 +1261,107 @@ module HDLRuby::High::Std
     end
   end
 
+  module BlockHBreak
+    # Build the block by executing +ruby_block+.
+    def build(&ruby_block)
+      High.space_push(@namespace)
+      cur_hbreak = true
+      catch(:HDLRubyThrow) do
+        @return_value = High.top_user.instance_eval(&ruby_block)
+        cur_hbreak = false
+      end
+      @hbreak = true if cur_hbreak
+      High.space_pop
+      @return_value
+    end
+
+    # # Creates and adds a new block executed in +mode+, with possible
+    # # +name+ and built by executing +ruby_block+.
+    # def add_block(mode = nil, name = :"", &ruby_block)
+    #   # Creates the block.
+    #   block = High.make_block(mode,name,&ruby_block)
+    #   # Adds it as a statement.
+    #   self.add_statement(block)
+    #   # Handle the breaks if any.
+    #   @hbreak = block.hbreak
+    #   # Use its return value.
+    #   return block.return_value
+    # end
+
+    # Adds a +statement+.
+    #
+    # NOTE: TimeWait is not supported unless for TimeBlock objects.
+    def add_statement(statement)
+      res = super(statement)
+      hbrk = statement.instance_variable_get(:@hbreak)
+      @hbreak = hbrk if hbrk
+      return res
+    end
+  end
+
+  HDLRuby::High::Block.prepend(BlockHBreak)
+
+  module IfHBreak
+    # Creates a new if statement with a +condition+ that when met lead
+    # to the execution of the block in +mode+ generated by the execution of
+    # +ruby_block+.
+    def initialize(condition, mode = nil, &ruby_block)
+      super
+      hbrk = yes.instance_variable_get(:@hbreak)
+      @hbreak = hbrk if hbrk
+    end
+
+    # Sets the no block.
+    #
+    # No shoud only be set once, but this is not checked here for
+    # sake of flexibility.
+    def no=(no)
+      res = super(no)
+      hbrk = no.instance_variable_get(:@hbreak)
+      raise AnyError, "Invalid hbreak." if hbrk
+      return res
+    end
+
+    # Adds an alternative if statement (elsif) testing +next_cond+
+    # and executing +next_yes+ when the condition is met.
+    def add_noif(next_cond, next_yes)
+      res = super(next_cond,next_yes)
+      hbrk = next_yes.instance_variable_get(:@hbreak)
+      raise AnyError, "Invalid hbreak." if hbrk
+      return res
+    end
+  end
+
+  HDLRuby::High::If.prepend(IfHBreak)
+
+  module BehaviorHBreak
+    # Creates a new behavior executing +block+ activated on a list of
+    # +events+, possible name (of main block) +name+ and built by
+    # executing +ruby_block+.
+    # +mode+ can be either :seq or :par for respectively sequential or
+    # parallel.
+    def initialize(mode, *events, name: nil, &ruby_block)
+      super(mode,*events, name: name, &ruby_block)
+      if self.block.instance_variable_get(:@hbreak) then
+        stmnt0 = self.block.each_statement.first
+        unless stmnt0.is_a?(HDLRuby::High::If) then
+          raise AnyError, "Unsuported usage of hbreak."
+        end
+        if stmnt0.no || stmnt0.each_noif.any? then
+          raise AnyError, "Unsuported usage of hbreak."
+        end
+        # Extract the hif an put it as the single statement whose else
+        # part is the current block.
+        self.block.delete_statement!(stmnt0)
+        self.block.parent = nil
+        self.block.instance_variable_set(:@hbreak,false)
+        stmnt0.no = self.block
+        self.block = HDLRuby::High.make_block(self.block.mode) {}
+        self.block.add_statement(stmnt0)
+      end
+    end
+  end
+
+  HDLRuby::High::Behavior.prepend(BehaviorHBreak)
+
 end

data/lib/HDLRuby/verilog_hruby.rb

@@ -889,6 +889,34 @@ module VerilogTools
         state.indent = indent
         state.level  = level
         return case_txt
+      when :casez
+        # Saves the state.
+        indent = state.indent
+        level = state.level
+        # Generate the hcase.
+        state.indent += "  "
+        case_txt = indent + "hcasez(" + ast[1].to_HDLRuby(state) + ")\n"
+        # Generate the case items.
+        case_txt += ast[2].map do |item|
+          res_txt = ""
+          if item[0] != "default" then
+            # hwhen case.
+            res_txt += indent + "hwhen(" 
+            res_txt += item[0].map {|e| e.to_HDLRuby(state) }.join(",")
+            res_txt += ") do\n"
+            res_txt += item[1].to_HDLRuby(state)
+            res_txt += indent + "end\n"
+          else
+            # helse case.
+            res_txt += indent + "helse do\n"
+            res_txt += item[1].to_HDLRuby(state) + indent + "end\n"
+          end
+          res_txt
+        end.join
+        # Restore the state and return the result.
+        state.indent = indent
+        state.level  = level
+        return case_txt
       when :blocking_assignment, :non_blocking_assignment
         return ast[0].to_HDLRuby(state)
       when :statement
@@ -1094,6 +1122,8 @@ module VerilogTools
       base = ast[1] ? ast[1].to_HDLRuby(state) : ""
       # Get the second number if any.
       number1 = ast[2] ? ast[2].to_HDLRuby(state) : ""
+      # In HDLRuby, for now, wildcards work like z.
+      number1 = number1.gsub("?","z")
       # Depending on the base.
       case base
       when "'b"

data/lib/HDLRuby/verilog_parser.rb

@@ -1220,7 +1220,7 @@ module VerilogTools
     CLOSE_BRA_COLON_TOKS = [ "\\" + CLOSE_BRA_TOK, COLON_TOK ]
     CLOSE_BRA_COLON_REX  = /\G#{S}(#{CLOSE_BRA_COLON_TOKS.join("|")})/
 
-    STATEMENT_TOKS = [ IF_TOK, CASE_TOK, CASEZ_TOK, CASEX_TOK, 
+    STATEMENT_TOKS = [ IF_TOK, CASEZ_TOK, CASEX_TOK, CASE_TOK,  
                        FOREVER_TOK, REPEAT_TOK, WHILE_TOK, FOR_TOK,
                        WAIT_TOK, RIGHT_ARROW_TOK, DISABLE_TOK,
                        ASSIGN_TOK, FORCE_TOK, DEASSIGN_TOK, RELEASE_TOK ]

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "3.9.5"
+  VERSION = "3.9.7"
 end

metadata

@@ -1,7 +1,7 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 3.9.5
+  version: 3.9.7
 platform: ruby
 authors:
 - Lovic Gauthier
@@ -193,11 +193,14 @@ files:
 - lib/HDLRuby/hdr_samples/tuple.rb
 - lib/HDLRuby/hdr_samples/type_minmax_bench.rb
 - lib/HDLRuby/hdr_samples/verilog_parser_bench.rb
+- lib/HDLRuby/hdr_samples/with_assign_to_slice.rb
+- lib/HDLRuby/hdr_samples/with_auto_connect.rb
 - lib/HDLRuby/hdr_samples/with_board.rb
 - lib/HDLRuby/hdr_samples/with_board_sequencer.rb
 - lib/HDLRuby/hdr_samples/with_bram.rb
 - lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb
 - lib/HDLRuby/hdr_samples/with_bram_stack.rb
+- lib/HDLRuby/hdr_samples/with_casez.rb
 - lib/HDLRuby/hdr_samples/with_casts.rb
 - lib/HDLRuby/hdr_samples/with_channel.rb
 - lib/HDLRuby/hdr_samples/with_channel_other.rb
@@ -210,12 +213,15 @@ files:
 - lib/HDLRuby/hdr_samples/with_def.rb
 - lib/HDLRuby/hdr_samples/with_define_operator.rb
 - lib/HDLRuby/hdr_samples/with_delay.rb
+- lib/HDLRuby/hdr_samples/with_expr_decoder.rb
+- lib/HDLRuby/hdr_samples/with_expr_hif.rb
 - lib/HDLRuby/hdr_samples/with_fixpoint.rb
 - lib/HDLRuby/hdr_samples/with_fixpoint_adv.rb
 - lib/HDLRuby/hdr_samples/with_fsm.rb
 - lib/HDLRuby/hdr_samples/with_function_generator.rb
 - lib/HDLRuby/hdr_samples/with_generic_in_generic.rb
 - lib/HDLRuby/hdr_samples/with_handshake.rb
+- lib/HDLRuby/hdr_samples/with_hbreak.rb
 - lib/HDLRuby/hdr_samples/with_henumerable.rb
 - lib/HDLRuby/hdr_samples/with_init.rb
 - lib/HDLRuby/hdr_samples/with_instance.rb
@@ -502,7 +508,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 4.0.14
+rubygems_version: 4.0.20
 specification_version: 4
 summary: HDLRuby is a library for describing and simulating digital electronic systems.
 test_files: []