HDLRuby 3.7.2 → 3.7.4
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- checksums.yaml +4 -4
- data/README.md +27 -0
- data/ext/hruby_sim/hruby_rcsim_build.c +47 -2
- data/ext/hruby_sim/hruby_sim.h +8 -0
- data/ext/hruby_sim/hruby_sim_calc.c +3 -2
- data/ext/hruby_sim/hruby_sim_core.c +24 -7
- data/lib/HDLRuby/hdr_samples/ruby_program/with_sw_hruby_function.rb +31 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_array.rb +48 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_sequencer.rb +49 -0
- data/lib/HDLRuby/hruby_high.rb +23 -0
- data/lib/HDLRuby/hruby_low.rb +25 -0
- data/lib/HDLRuby/hruby_rcsim.rb +8 -0
- data/lib/HDLRuby/std/sequencer.rb +5 -0
- data/lib/HDLRuby/std/sequencer_sw.rb +404 -104
- data/lib/HDLRuby/version.rb +1 -1
- data/lib/rubyHDL.rb +26 -0
- metadata +6 -3
data/lib/HDLRuby/version.rb
CHANGED
data/lib/rubyHDL.rb
CHANGED
@@ -6,6 +6,32 @@ require 'hruby_sim/hruby_sim'
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########################################################################
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module RubyHDL
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# Wrapper for array signal accesses.
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class ArrayWrapper
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# Create a new memory wrapper for signal +sig+
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def initialize(sig)
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@signal = sig
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end
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# Read the array.
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def [](idx)
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return RCSim.rcsim_read_index_fixnum(@signal,idx)
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end
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# Write to the array.
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def []=(idx,val)
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return RCSim.rcsim_write_index_fixnum_seq(@signal,idx,val)
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end
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end
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# Creates a new array port 'name' assigned to signal 'sig'.
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def self.arrayport(name,sig)
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# Creating the accessing method.
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define_singleton_method(name.to_sym) do
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ArrayWrapper.new(sig)
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end
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end
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# Creates a new port 'name' assigned to signal 'sig' for reading.
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def self.inport(name,sig)
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# Create the accessing methods.
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metadata
CHANGED
@@ -1,13 +1,13 @@
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--- !ruby/object:Gem::Specification
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name: HDLRuby
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version: !ruby/object:Gem::Version
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-
version: 3.7.
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version: 3.7.4
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platform: ruby
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authors:
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- Lovic Gauthier
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bindir: exe
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cert_chain: []
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-
date:
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date: 1980-01-02 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: bundler
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@@ -180,6 +180,7 @@ files:
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- lib/HDLRuby/hdr_samples/ruby_program/sw_inc_mem.rb
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- lib/HDLRuby/hdr_samples/ruby_program/sw_log.rb
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- lib/HDLRuby/hdr_samples/ruby_program/with_sw_hruby.rb
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+
- lib/HDLRuby/hdr_samples/ruby_program/with_sw_hruby_function.rb
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- lib/HDLRuby/hdr_samples/ruby_program/with_sw_hruby_hruby_test.rb
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- lib/HDLRuby/hdr_samples/seqpar_bench.rb
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- lib/HDLRuby/hdr_samples/simple_counter_bench.rb
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@@ -226,9 +227,11 @@ files:
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- lib/HDLRuby/hdr_samples/with_of.rb
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- lib/HDLRuby/hdr_samples/with_program_c.rb
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- lib/HDLRuby/hdr_samples/with_program_ruby.rb
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- lib/HDLRuby/hdr_samples/with_program_ruby_array.rb
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- lib/HDLRuby/hdr_samples/with_program_ruby_cpu.rb
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- lib/HDLRuby/hdr_samples/with_program_ruby_io.rb
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- lib/HDLRuby/hdr_samples/with_program_ruby_mem.rb
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- lib/HDLRuby/hdr_samples/with_program_ruby_sequencer.rb
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- lib/HDLRuby/hdr_samples/with_program_ruby_threads.rb
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- lib/HDLRuby/hdr_samples/with_reconf.rb
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- lib/HDLRuby/hdr_samples/with_reduce.rb
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@@ -491,7 +494,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
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- !ruby/object:Gem::Version
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version: '0'
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requirements: []
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-
rubygems_version: 3.6.
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+
rubygems_version: 3.6.8
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specification_version: 4
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summary: HDLRuby is a library for describing and simulating digital electronic systems.
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test_files: []
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