HDLRuby 3.7.2 → 3.7.4

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data/README.md

@@ -17,6 +17,10 @@ hdrcc --get-tuto
 
 __What's new__
 
+For HDLRuby version 3.7.3:
+
+* Added the possibility to use software sequencers inside HDLRuby's program construct, and use within them program ports like they were input or output signals.
+
 For HDLRuby version 3.7.2:
 
 * Added the `text` command for the sequencers in software.
@@ -3981,6 +3985,29 @@ sequencer do
 end
 ```
 
+#### Using Software Sequencer Inside a HDLRuby program.
+
+HDLRuby supports hardware/software co-design through the `program` [construct](#declaring-a-software-component). Since software sequencers are software components, they can be used within this construct when the selected language is Ruby, however the command `activate_sequencer_sw(binding)` must be inserted in the first line of the Ruby code. Software sequencers can also be used with the C language, but in that case, the corresponding C code must first be generated.
+
+For Ruby, software sequencer signals can be automatically connected to the ports of the program construct by declaring them as input signals for `inport` and output signals for `outport`. For example, the following code describes a software sequencer that echoes the value from the input port `inP` to the output port `outP` (`sig0` and `sig1` are signals from the upper RTL design).
+
+```ruby
+program(:ruby) do
+  actport clk.posedge
+  inport inP: sig0
+  outport outP: sig1
+  code do
+    activate_sequencer_sw(binding)
+    input :inP
+    output :outP
+    sequencer do
+      outP <= inP
+    end
+  end
+end
+```
+
+
 
 ## Fixed-point (fixpoint): `std/fixpoint.rb`
 <a name="fixpoint"></a>

data/ext/hruby_sim/hruby_rcsim_build.c

@@ -1682,7 +1682,7 @@ VALUE rcsim_transmit_fixnum_to_signal(VALUE mod, VALUE signalV, VALUE valR) {
     /* Get the C signal from the Ruby value. */
     SignalI signal;
     value_to_rcsim(SignalIS,signalV,signal);
-    /* Compute the simualtion value from valR. */
+    /* Compute the simulation value from valR. */
     Value value = get_value();
     value->type = signal->type;
     value->numeric = 1;
@@ -1699,7 +1699,7 @@ VALUE rcsim_transmit_fixnum_to_signal_seq(VALUE mod, VALUE signalV, VALUE valR)
     /* Get the C signal from the Ruby value. */
     SignalI signal;
     value_to_rcsim(SignalIS,signalV,signal);
-    /* Compute the simualtion value from valR. */
+    /* Compute the simulation value from valR. */
     Value value = get_value();
     value->type = signal->type;
     value->numeric = 1;
@@ -1711,6 +1711,49 @@ VALUE rcsim_transmit_fixnum_to_signal_seq(VALUE mod, VALUE signalV, VALUE valR)
 }
 
 
+/** Reads an elements of a C signal array at an index and returns
+ *  the result as a Ruby fixnum.
+ *  Sets 0 if the value contains x or z bits. */
+VALUE rcsim_read_index_fixnum(VALUE mod, VALUE signalV, VALUE idxV) {
+    Value value = get_value();
+    /* Get the C signal from the Ruby value. */
+    SignalI signal;
+    value_to_rcsim(SignalIS,signalV,signal);
+    /* Get its base type.*/
+    Type base = get_type_vector(get_type_bit(),signal->type->base);
+    /* Get the index. */
+    unsigned long long idx = FIX2LONG(idxV);
+    /* Access the value. */
+    read_range(signal->c_value,idx,idx,base,value);
+    /* Get the value from the signal. */
+    return LONG2FIX(value2integer(value));
+}
+
+/** Transmit a Ruby fixnum inside a C signal array at an index in 
+ *  a blocking fashion.
+ * NOTE: the simulator events are updated. */
+VALUE rcsim_write_index_fixnum_seq(VALUE mod, VALUE signalV, VALUE idxV, VALUE valR) {
+    /* Get the C signal from the Ruby value. */
+    SignalI signal;
+    value_to_rcsim(SignalIS,signalV,signal);
+    // /* Get its base type.*/
+    // Type base = get_type_vector(get_type_bit(),signal->type->base);
+    /* Get the index. */
+    unsigned long long idx = FIX2LONG(idxV);
+    /* Compute the simulation value from valR. */
+    Value value = get_value();
+    value->type = signal->type;
+    value->numeric = 1;
+    value->data_int = FIX2LONG(valR);
+    /* Transmit it. */
+    transmit_to_signal_range_num_seq(value, signal, idx,idx);
+    /* End, return the transmitted expression. */
+    return valR;
+}
+
+
+
+
 // /** Execute a behavior. */
 // VALUE rcsim_execute_behavior(VALUE mod, VALUE behaviorV) {
 //     /* Get the behavior. */
@@ -1900,6 +1943,8 @@ void Init_hruby_sim() {
     /* The Ruby software interface. */
     rb_define_singleton_method(mod,"rcsim_get_signal_fixnum",rcsim_get_signal_fixnum,1);
     rb_define_singleton_method(mod,"rcsim_transmit_fixnum_to_signal_seq",rcsim_transmit_fixnum_to_signal_seq,2);
+    rb_define_singleton_method(mod,"rcsim_read_index_fixnum",rcsim_read_index_fixnum,2);
+    rb_define_singleton_method(mod,"rcsim_write_index_fixnum_seq",rcsim_write_index_fixnum_seq,3);
     // rb_define_singleton_method(mod,"rcsim_execute_behavior",rcsim_execute_behavior,1);
 
 }

data/ext/hruby_sim/hruby_sim.h

@@ -901,6 +901,14 @@ extern void transmit_to_signal_seq(Value value, SignalI signal);
  *         value to. */
 extern void transmit_to_signal_range_seq(Value value, RefRangeS ref);
 
+/** Transmit a value to a range within a signal in case of sequential
+ *  execution model.
+ *  @param value the value to transmit
+ *  @param ref the reference to the range in the signal to transmit the
+ *         value to. */
+extern void transmit_to_signal_range_num_seq(Value value, SignalI signal,
+        unsigned long long first, unsigned long long last);
+
 /** Creates an event.
  *  @param edge the edge of the event
  *  @param signal the signal of the event */

data/ext/hruby_sim/hruby_sim_calc.c

@@ -2449,7 +2449,7 @@ static int same_content_value_range_numeric(Value value0,
 Value read_range_numeric(Value value,
         unsigned long long first, unsigned long long last,
         Type base, Value dst) {
-    /* printf("read_range_numeric with value=%llx and first=%llu and last=%llu\n",value->data_int,first,last); */
+    // printf("read_range_numeric with value=%llx and first=%llu and last=%llu\n",value->data_int,first,last); 
     /* Ensure first is the smaller. */
     if (first > last) {
         long long tmp = last;
@@ -2465,7 +2465,7 @@ Value read_range_numeric(Value value,
     first *= bw;
     last  *= bw;
     length *= bw;
-    /* printf("first=%lld last=%lld bw=%llu length=%lld\n",first,last,bw,length); */
+    // printf("first=%lld last=%lld bw=%llu length=%lld\n",first,last,bw,length); */
 
     /* Set the type and size of the destination from the type of the source.*/
     dst->type = make_type_vector(get_type_bit(),length);
@@ -3427,6 +3427,7 @@ unsigned long long value2integer(Value value) {
 Value read_range(Value value,
         unsigned long long first, unsigned long long last, 
         Type base, Value dst) {
+    // printf("Read range with first=%d, last=%d\n",first,last);
     /* Is the value numeric? */
     if (value->numeric) {
         /* Yes, do a numeric range read. */

data/ext/hruby_sim/hruby_sim_core.c

@@ -735,18 +735,35 @@ void transmit_to_signal_seq(Value value, SignalI signal) {
  *  @param value the value to transmit
  *  @param ref the reference to the range in the signal to transmit the
  *         value to. */
+void transmit_to_signal_range_num_seq(Value value, SignalI signal,
+        unsigned long long first, unsigned long long last) {
+    // printf("Tansmit to signal range seq: %s(%p) [%llu,%llu]\n",signal->name,signal,first,last);
+    /* The base type is stored here to avoid allocating a new type each time.
+     * It have an arbitrary base size a single element. */
+    static TypeS baseT = { 1, 1 };
+    baseT.base = signal->f_value->type->base;
+    // printf("Tansmit to signal range: %s(%p) [%lld:%lld]\n",signal->name,signal,first,last);
+    /* Can transmit, copy the content. */
+    if (signal->fading)
+        signal->f_value = write_range(value,first,last,&baseT,
+                signal->f_value);
+    else
+        signal->f_value = write_range_no_z(value,first,last,&baseT,
+                signal->f_value);
+    /* And touch the signal. */
+    touch_signal_seq(signal);
+}
+
+/** Transmit a value to a range given with by first and last values, within a signal in case of sequential
+ *  execution model.
+ *  @param value the value to transmit
+ *  @param ref the reference to the range in the signal to transmit the
+ *         value to. */
 void transmit_to_signal_range_seq(Value value, RefRangeS ref) {
     SignalI signal = ref.signal;
     unsigned long long first = ref.first;
     unsigned long long last = ref.last;
     // printf("Tansmit to signal range seq: %s(%p) [%llu,%llu]\n",signal->name,signal,first,last);
-    // /* Can transmit, copy the content. */
-    // if (signal->fading)
-    //     // write_range(value,first,last,signal->f_value->type,signal->f_value);
-    //     write_range(value,first,last,ref.type,signal->f_value);
-    // else
-    //     // write_range_no_z(value,first,last,signal->f_value->type,signal->f_value);
-    //     write_range_no_z(value,first,last,ref.type,signal->f_value);
     /* The base type is stored here to avoid allocating a new type each time.
      * It have an arbitrary base size a single element. */
     static TypeS baseT = { 1, 1 };

data/lib/HDLRuby/hdr_samples/ruby_program/with_sw_hruby_function.rb

@@ -0,0 +1,31 @@
+require 'HDLRuby/std/sequencer_sw'
+
+include RubyHDL::High
+using RubyHDL::High
+
+# Sequencer for testing arithmetic computations.
+
+sdef(:truc) do |m,n|
+  sreturn(n+m*2)
+end
+
+signed[32].inner :x,:y, :result
+signed[32].inner :clk
+
+my_seq = sequencer(clk) do
+  x <= 0
+  y <= 0
+  100.stimes do
+    x <= x + 1
+    10.times do
+      y <= truc(x,y)
+    end
+  end
+  result <= y
+end
+
+puts "code=" + my_seq.source
+
+my_seq.()
+
+puts "result=#{result}"

data/lib/HDLRuby/hdr_samples/with_program_ruby_array.rb

@@ -0,0 +1,48 @@
+
+# A benchmark for testing the use of Ruby software code with array ports.
+system :with_ruby_prog do
+  inner :clk
+  bit[8][-8].inner ar: [ _h00, _h01, _h04, _h09, _h10, _h19, _h24, _h31 ]
+
+  program(:ruby,:show) do
+    actport clk.posedge
+    arrayport arP: ar
+    code(proc do
+      def show
+        8.times do |i|
+          val = RubyHDL.arP[i]
+          puts "# ar[#{i}]=#{val}"
+          RubyHDL.arP[i] = i+i
+        end
+      end
+    end)
+  end
+
+
+  timed do
+    clk <= 0
+    hprint("ar[0]=",ar[0],"\n")
+    hprint("ar[1]=",ar[1],"\n")
+    hprint("ar[2]=",ar[2],"\n")
+    hprint("ar[3]=",ar[3],"\n")
+    hprint("ar[4]=",ar[4],"\n")
+    hprint("ar[5]=",ar[5],"\n")
+    hprint("ar[6]=",ar[6],"\n")
+    hprint("ar[7]=",ar[7],"\n")
+    !10.ns
+    repeat(8) do
+      clk <= ~clk
+      !10.ns
+    end
+    !10.ns
+    hprint("ar[0]=",ar[0],"\n")
+    hprint("ar[1]=",ar[1],"\n")
+    hprint("ar[2]=",ar[2],"\n")
+    hprint("ar[3]=",ar[3],"\n")
+    hprint("ar[4]=",ar[4],"\n")
+    hprint("ar[5]=",ar[5],"\n")
+    hprint("ar[6]=",ar[6],"\n")
+    hprint("ar[7]=",ar[7],"\n")
+    !10.ns
+  end
+end

data/lib/HDLRuby/hdr_samples/with_program_ruby_sequencer.rb

@@ -0,0 +1,49 @@
+
+# A benchmark for testing the use of Ruby software code including a
+# sequencer.
+#
+system :with_ruby_prog_seq do
+    inner :clk
+    [8].inner :count, :echo
+
+    program(:ruby,:echo) do
+        actport clk.posedge
+        inport  inP: count
+        outport outP: echo
+        code(proc do
+          activate_sequencer_sw(binding)
+
+          $my_seq = nil
+
+          def echo
+            unless $my_seq then
+              [32].input :inP
+              [32].output :outP
+              $my_seq = sequencer do
+                sloop do
+                  outP <= inP
+                  sync
+                end
+              end
+            end
+            $my_seq.()
+          end
+        end)
+    end
+
+
+    timed do
+        clk <= 0
+        count <= 0
+        !10.ns
+        repeat(10) do
+            clk <= 1
+            hprint("echo=",echo,"\n")
+            !10.ns
+            count <= count + 1
+            clk <= 0
+            !10.ns
+        end
+
+    end
+end

data/lib/HDLRuby/hruby_high.rb

@@ -2584,6 +2584,8 @@ module HDLRuby::High
             self.each_inport  { |p| progL.add_inport(p[0],p[1].to_low) }
             # Add the output signals references.
             self.each_outport { |p| progL.add_outport(p[0],p[1].to_low) }
+            # Add the array signals references.
+            self.each_arrayport { |p| progL.add_arrayport(p[0],p[1].to_low) }
             # Return the resulting program.
             return progL
         end
@@ -2607,6 +2609,11 @@ module HDLRuby::High
         def outport(ports = {})
           ports.each { |k,v| self.add_outport(k,v) }
         end
+
+        # Adds new array ports.
+        def arrayport(ports = {})
+          ports.each { |k,v| self.add_arrayport(k,v) }
+        end
     end
 
 
@@ -5555,4 +5562,20 @@ def self.configure_high
     def self.booting?
         false
     end
+
+
+end
+
+
+
+
+# Activate the software sequencer for Ruby code embedded in HDLRuby
+def activate_sequencer_sw(binding_context)
+  eval <<~RUBY, binding_context
+    alias require_ruby require
+    require_ruby 'HDLRuby/std/sequencer_sw'
+    include RubyHDL::High
+    using RubyHDL::High
+  RUBY
 end
+

data/lib/HDLRuby/hruby_low.rb

@@ -3019,6 +3019,7 @@ module HDLRuby::Low
             @codes    = [] # The code files.
             @inports  = {} # The input ports.
             @outports = {} # The output ports.
+            @arrayports ={}# The array ports.
         end
 
         # Add a new activation port.
@@ -3063,6 +3064,20 @@ module HDLRuby::Low
             @outports[name] = sig
         end
 
+        # Add a new array port.
+        def add_arrayport(name, sig)
+            # Ensure name is a symbol.
+            unless name.is_a?(Symbol) then
+                name = name.to_s.to_sym
+            end
+            # Ensure sig is a signal.
+            unless sig.is_a?(SignalI) then
+                raise AnyError, "Invalid class for a signal: #{sig.class}"
+            end
+            # Add the new port.
+            @arrayports[name] = sig
+        end
+
 
         # Iterates over each activation event.
         #
@@ -3104,6 +3119,16 @@ module HDLRuby::Low
             @outports.each(&ruby_block)
         end
 
+        # Iterate over each array port.
+        #
+        # Returns an enumerator if no ruby block is given.
+        def each_arrayport(&ruby_block)
+            # No block? Return an enumerator.
+            return to_enum(:each_arrayport) unless ruby_block
+            # A block is given, apply it.
+            @arrayports.each(&ruby_block)
+        end
+
     end
 
 

data/lib/HDLRuby/hruby_rcsim.rb

@@ -572,6 +572,10 @@ module HDLRuby::High
                 self.each_outport do |sym, sig|
                     RubyHDL.outport(sym,sig.rcsignalI)
                 end
+                # Add the array ports.
+                self.each_arrayport do |sym, sig|
+                    RubyHDL.arrayport(sym,sig.rcsignalI)
+                end
             elsif self.language == :c then
                 # Loads the code file: only the last one remains.
                 self.each_code do |code|
@@ -601,6 +605,10 @@ module HDLRuby::High
                 self.each_outport do |sym, sig|
                     RCSim::CPorts[sym] = sig.rcsignalI
                 end
+                # Add the array ports.
+                self.each_arrayport do |sym, sig|
+                    RCSim::CPorts[sym] = sig.rcsignalI
+                end
             end
 
 

data/lib/HDLRuby/std/sequencer.rb

@@ -315,6 +315,11 @@ module HDLRuby::High::Std
             expr.seach.with_index(&ruby_block)
         end
 
+        # Does nothing: just for compatibility with the software
+        # implementation of sequencers.
+        def sync
+        end
+
         # Tell if the sequencer ends it execution.
         def alive?
           return @fsm.cur_state_sig != self.end_state_value