HDLRuby 3.1.0 → 3.2.0

data/lib/HDLRuby/hruby_verilog.rb

@@ -169,7 +169,17 @@ module HDLRuby::Low
 
         # Converts the system to Verilog code.
         def to_verilog
-            return "(#{self.left.to_verilog} #{self.operator} #{self.right.to_verilog})"
+            # In HDLRuby if on term is signed and the other is not, the
+            # computation is signed.
+            if self.left.type.signed? and self.right.type.unsigned? then
+                return "(#{self.left.to_verilog} #{self.operator} " +
+                    "$signed({1'b0,#{self.right.to_verilog}}))"
+            elsif self.left.type.unsigned? and right.type.signed? then
+                return "($signed({1'b0,#{self.left.to_verilog}})" +
+                    " #{self.operator} #{self.right.to_verilog})"
+            else
+                return "(#{self.left.to_verilog} #{self.operator} #{self.right.to_verilog})"
+            end
         end
 
         # Method called when two or more expression terms are present.
@@ -262,7 +272,6 @@ module HDLRuby::Low
             # Declaration of "inner" part within "always".
             block.each_inner do |inner|
                 if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
-                    # code << "      reg"
                     code << "#{" " * (spc+3)}reg"
                 else
                     code << "#{" " * (spc+3)}wire"
@@ -1501,7 +1510,14 @@ module HDLRuby::Low
 
         # Converts the system to Verilog code using +renamer+ for producing Verilog-compatible names.
         def to_verilog
-            vname = name_to_verilog(self.name)
+            if (self.ref.is_a?(RefThis)) then
+                # End reference.
+                vname = name_to_verilog(self.name)
+            else
+                # Not end reference, recurse.
+                # vname = name_to_verilog(self.name) + "." + self.ref.to_verilog 
+                vname = self.ref.to_verilog + "." + name_to_verilog(self.name)
+            end
             # self.properties[:verilog_name] = vname
             return "#{vname}"
         end
@@ -1565,8 +1581,11 @@ module HDLRuby::Low
                 return "#{self.ref.to_verilog}[#{self.range.first.to_getrange}:#{self.range.last.to_getrange}]"
             else
                 # No a pure signal, need to use a function for accessing.
-                sr = self.range.first.to_i..self.range.last.to_i
-                cr = (self.type.width-1)..0
+                # sr = self.range.first.to_i..self.range.last.to_i
+                # cr = (self.type.width-1)..0
+                sr = (self.range.first.to_i+1)*self.ref.type.base.width-1..
+                    self.range.last.to_i*self.ref.type.base.width
+                cr = (self.ref.type.width-1)..0
                 TruncersI.add(cr,sr)
                 return "#{TruncersI.truncer_name(cr,sr)}(#{self.ref.to_verilog})"
             end
@@ -1735,9 +1754,11 @@ module HDLRuby::Low
             if self.default then
                 result << " " * (spc+3) + "default: "
                 if self.default.each_statement.count >= 1 then
+                    result << "begin\n"
                     result << self.default.each_statement.map do |stmnt|
-                        stmnt.to_verilog(spc+3)
+                        stmnt.to_verilog(spc+6)
                     end.join("\n") << "\n"
+                    result << " " * (spc+3) + "end\n"
                 else
                     result << ";\n"
                 end
@@ -2027,11 +2048,60 @@ module HDLRuby::Low
         end
 
 
+        # Get the signals that can be declared as reg.
+        # If +vname+ is given, use as base for reference name.
+        def self.get_regs(expr,vname = nil)
+            if expr.is_a?(RefConcat) then
+                return expr.each_ref.map {|ref| self.get_regs(ref,vname) }.flatten
+            elsif expr.is_a?(RefName) then
+                if vname then
+                    puts "vname=#{vname} expr.name=#{expr.name}"
+                    if expr.ref && name_to_verilog(expr.name) == vname then
+                        return get_regs(expr.ref)
+                    else
+                        return []
+                    end
+                else
+                    return [expr]
+                end
+            else
+                return get_regs(expr.ref,vname)
+            end
+        end
+
+        # Get signals indirectly refered that have to become reg in
+        # a sub system. +vname+ is the name of the system whose signals
+        # are to be processed.
+        def self.get_indirect_verilog_regs(systemI,vname)
+            # Get the sub systemT.
+            sub_systemT = systemI.systemT
+            # Get the indirect reg inside it.
+            sub_systemT.each_behavior do |behavior|
+                behavior.each_block_deep do |block|
+                    block.each_statement do |statement|
+                        if statement.is_a?(Transmit) &&
+                                statement.left.to_verilog.include?(vname + ".")
+                            puts "hierachical=#{statement.left.to_verilog}"
+                            # HDLRuby::Low::VERILOG_REGS << SystemT.get_regs(statement.left.ref).to_verilog
+                            HDLRuby::Low::VERILOG_REGS.concat( SystemT.get_regs(statement.left,vname).map(&:to_verilog))
+                        end
+                    end
+                end
+            end
+            # And recurse on its systemIs.
+            sub_systemT.each_systemI do |sub_systemI|
+                SystemT.get_indirect_verilog_regs(sub_systemI,vname)
+            end
+        end
+
 
         # Converts the system to Verilog code.
         # NOTE: if +vcd+ is true, generate verilog code whose simulation
         #       produces a vcd file.
         def to_verilog(vcd = false)
+            # Create the name of the module.
+            vname = name_to_verilog(self.name)
+            # puts "Processing systemT named=#{vname}"
             # Detect the registers
             HDLRuby::Low::VERILOG_REGS.clear
             # The left values.
@@ -2039,11 +2109,15 @@ module HDLRuby::Low
                 behavior.each_block_deep do |block|
                     block.each_statement do |statement|
                         if statement.is_a?(Transmit)
-                            HDLRuby::Low::VERILOG_REGS << statement.left.to_verilog
+                            # HDLRuby::Low::VERILOG_REGS << SystemT.get_regs(statement.left).to_verilog
+                            HDLRuby::Low::VERILOG_REGS.concat(SystemT.get_regs(statement.left).map(&:to_verilog))
                         end
                     end
                 end
             end
+            self.each_systemI do |systemI|
+                SystemT.get_indirect_verilog_regs(systemI,vname)
+            end
             # And the initialized signals.
             self.each_output do |output|
                 # regs << output.to_verilog if output.value
@@ -2053,17 +2127,18 @@ module HDLRuby::Low
                 # regs << inner.to_verilog if inner.value
                 HDLRuby::Low::VERILOG_REGS << inner.to_verilog if inner.value
             end
-            # And the array types signals.
-            self.each_signal do |sig|
-                if sig.type.vector? && sig.type.base.vector? then
-                    HDLRuby::Low::VERILOG_REGS << sig.to_verilog
-                end
-            end
-            self.each_inner do |sig|
-                if sig.type.vector? && sig.type.base.vector? then
-                    HDLRuby::Low::VERILOG_REGS << sig.to_verilog
-                end
-            end
+            # Actual NOT...
+            # # And the array types signals.
+            # self.each_signal do |sig|
+            #     if sig.type.vector? && sig.type.base.vector? then
+            #         HDLRuby::Low::VERILOG_REGS << sig.to_verilog
+            #     end
+            # end
+            # self.each_inner do |sig|
+            #     if sig.type.vector? && sig.type.base.vector? then
+            #         HDLRuby::Low::VERILOG_REGS << sig.to_verilog
+            #     end
+            # end
 
             # Code generation
             inputs = 0
@@ -2077,7 +2152,6 @@ module HDLRuby::Low
             # Spelling necessary for simulation.
             code = "`timescale 1ps/1ps\n\n"
 
-            vname = name_to_verilog(self.name)
             # self.properties[:verilog_name] = vname
             # Output the module name.
             code << "module #{vname}("
@@ -2315,7 +2389,7 @@ module HDLRuby::Low
                     codeC << "   initial "
                 else
                     # Generate a standard process.
-                    codeC << "   always @( "
+                    codeC << "\n   always @( "
                     # If there is no "always" condition, it is always @("*").
                     if behavior.each_event.to_a.empty? then
                         codeC << "*"

data/lib/HDLRuby/hruby_verilog_name.rb

@@ -8,26 +8,11 @@ module HDLRuby::Verilog
   # puts n            
   # name = n.split("")
 
-  @@hdr2verilog = {}
+  @@hdr2verilog = { "buf" => "_v0_buf", "table" => "_v1_table", "time" => "_v2_time" }
 
   # Since it is possible to use $ and numbers other than the beginning of the character string, it is divided.
   def name_to_verilog(name)
-      # name = name.to_s
-      # # Convert special characters.
-      # name = name.each_char.map do |c|
-      #     if c=~ /[a-z0-9]/ then
-      #         c
-      #     elsif c == "_" then
-      #         "__"
-      #     else
-      #         "_" + c.ord.to_s
-      #     end
-      # end.join
-      # # First character: only letter is possible.
-      # unless name[0] =~ /[a-z_]/ then
-      #     name = "_" + name
-      # end
-      # return name
+      # puts "name_to_verilog with name=#{name}"
       name = name.to_s
       vname = @@hdr2verilog[name]
       unless vname then
@@ -41,6 +26,7 @@ module HDLRuby::Verilog
           end
           @@hdr2verilog[name] = vname
       end
+      # puts "result vname=#{vname}"
       return vname
   end
 

data/lib/HDLRuby/std/fixpoint.rb

@@ -53,9 +53,9 @@ module HDLRuby::High::Std
                         # Redefine the multiplication and division for fixed point.
                         typ.define_operator(:*) do |left,right|
                             if (typ.signed?) then
-                                (left.as(signed[isize+fsize*2])*right) >> fsize
+                                ((left.as(signed[isize+fsize*2])*right) >> fsize).as(typ)
                             else
-                                (left.as(bit[isize+fsize*2])*right) >> fsize
+                                ((left.as(bit[isize+fsize*2])*right) >> fsize).as(typ)
                             end
                         end
                         typ.define_operator(:/) do |left,right|

data/lib/HDLRuby/std/function_generator.rb

@@ -75,7 +75,7 @@ module HDLRuby::High::Std
         base <= lut[address]
 
         # Assign the next_data discrete value.
-        next_data <= lut[address+_b1.as(address.type)]
+        next_data <= mux(address < lut_size-1,lut[address],lut[address+_b1.as(address.type)])
     end
 
 

data/lib/HDLRuby/std/linear.rb

@@ -16,7 +16,7 @@ module HDLRuby::High::Std
     # - +ruby_block+: the code of the linear computation kernel, it takes
     #                 as argument +ev+, and its own req and ack signals
     #                 (resp. +req_ker+ +ack_ker+).
-    function :linearun do |num,ev,req,ack,ruby_block|
+    hdef :linearun do |num,ev,req,ack,ruby_block|
         # Ensure ev is really an event.
         ev = ev.posedge unless ev.is_a?(Event)
 
@@ -57,7 +57,7 @@ module HDLRuby::High::Std
     # Delcares a vector product by a scalar value.
     #
     # Can be used for scaling a vector.
-    function :scale do |typ,ev,req,ack,left,rights,prods,
+    hdef :scale do |typ,ev,req,ack,left,rights,prods,
                         mul = proc { |x,y| x*y }|
         # Ensure ev is really an event.
         ev = ev.posedge unless ev.is_a?(Event)
@@ -101,7 +101,7 @@ module HDLRuby::High::Std
     # Declares a 1-dimension vector adder.
     #
     # Can be used for the sum of two vectors.
-    function :add_n do |typ,ev,req,ack,lefts, rights, sums,
+    hdef :add_n do |typ,ev,req,ack,lefts, rights, sums,
                         add = proc { |x,y| x+y }|
         # Ensure ev is really an event.
         ev = ev.posedge unless ev.is_a?(Event)
@@ -143,7 +143,7 @@ module HDLRuby::High::Std
     end
 
     # Declares a 1-dimension vector element-wise multiplier.
-    function :mul_n do |typ,ev,req,ack,lefts, rights, prods,
+    hdef :mul_n do |typ,ev,req,ack,lefts, rights, prods,
                         mul = proc { |x,y| x*y }|
         add_n(typ,ev,req,ack,lefts,rights,prods,mul)
     end
@@ -152,7 +152,7 @@ module HDLRuby::High::Std
     # Declares a simple multiplier accumulator.
     #
     # Can be used for the scalar product of two vectors.
-    function :mac do |typ,ev,req,ack,left, right, acc,
+    hdef :mac do |typ,ev,req,ack,left, right, acc,
         mul = proc { |x,y| x*y }, add = proc { |x,y| x+y }|
         # Ensure ev is really an event.
         ev = ev.posedge unless ev.is_a?(Event)
@@ -193,7 +193,7 @@ module HDLRuby::High::Std
     # Declares a simple multiple mac with single right data.
     #
     # Can be used for the product of a martix-vector product.
-    function :mac_n1 do |typ,ev,req,ack,lefts, right, accs,
+    hdef :mac_n1 do |typ,ev,req,ack,lefts, right, accs,
         mul = proc { |x,y| x*y }, add = proc { |x,y| x+y }|
         # Ensure ev is really an event.
         ev = ev.posedge unless ev.is_a?(Event)
@@ -262,7 +262,7 @@ module HDLRuby::High::Std
     # Declares a simple pipelined multiple mac with single right data.
     #
     # Can be used for the product of a martix-vector product.
-    function :mac_np do |typ,ev,req,ack,lefts, rights, last,
+    hdef :mac_np do |typ,ev,req,ack,lefts, rights, last,
         mul = proc { |x,y| x*y }, add = proc { |x,y| x+y }|
         # Ensure ev is really an event.
         ev = ev.posedge unless ev.is_a?(Event)