HDLRuby 3.1.0 → 3.2.0

data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb

@@ -11,7 +11,7 @@ system :bram_stach_test do
     depth = 16
 
 
-    input :clk, :rst, :ce
+    inner :clk, :rst, :ce
     [2].inner :cmd
     { frame: bit[depth.width], offset: bit[size.width] }.inner :loc
     [size.width].inner :frame_size

data/lib/HDLRuby/hdr_samples/with_bram_stack.rb

@@ -10,7 +10,7 @@ system :bram_stach_test do
     widthD = 8
 
 
-    input :clk, :rst, :ce
+    inner :clk, :rst, :ce
     inner :cmd
     [widthD].inner  :din,:dout
     inner :empty, :full

data/lib/HDLRuby/hdr_samples/with_channel.rb

@@ -1,5 +1,7 @@
 require 'std/channel.rb'
 
+raise "std/channel.rb is deprecated."
+
 include HDLRuby::High::Std
 
 # Implementation of a handshaker channel transmitting generic values

data/lib/HDLRuby/hdr_samples/with_channel_other.rb

@@ -1,6 +1,8 @@
 require 'std/channel.rb'
 require 'std/hruby_unit.rb'
 
+raise "std/channel.rb is deprecated."
+
 include HDLRuby::High::Std
 
 # A clocked handshake channel for testing purpuse.

data/lib/HDLRuby/hdr_samples/with_class.rb

@@ -1,5 +1,7 @@
 # A class for a handshake transmission.
 
+raise "Deprecated code."
+
 class Handshaker
 
     ## Create a new handshaker for transmitting +type+ data.
@@ -179,7 +181,7 @@ end
 
 # A system testing the producer/consumer.
 system :hs_test do
-    input :clk,:rst
+    inner :clk,:rst
 
     # Declares the handshaker
     hs = Handshaker.new([8])

data/lib/HDLRuby/hdr_samples/with_connector.rb

@@ -1,6 +1,8 @@
 require 'std/channel.rb'
 require 'std/connector.rb'
 
+raise "std/channel.rb is deprecated."
+
 include HDLRuby::High::Std
 
 # Sample for testing the connectors of channels.

data/lib/HDLRuby/hdr_samples/with_connector_memory.rb

@@ -3,6 +3,8 @@ require "std/fixpoint.rb"
 require 'std/channel.rb'
 require 'std/connector.rb'
 
+raise "std/channel.rb is deprecated."
+
 include HDLRuby::High::Std
 
 system :channel_connector do

data/lib/HDLRuby/hdr_samples/with_fixpoint.rb

@@ -11,6 +11,12 @@ system :fix_test do
     bit[3..0,3..0].inner :x,:y,:z
     # Declare three 8-bit integer part 8-bit fractional part
     signed[3..0,3..0].inner :a,:b,:c,:d
+    # Declare the comparison results.
+    bit.inner :cmpU, :cmpS
+
+    cmpU <= (x >= y)
+    cmpS <= (a >= b)
+
 
     # Performs calculation between then
     timed do

data/lib/HDLRuby/hdr_samples/with_fixpoint_adv.rb

@@ -0,0 +1,73 @@
+# Sample for testing advanced expressions with fixpoint.
+
+system :with_fixpoint_adv do
+    inner :clk,:rst
+    signed[8,8].inner :x,:y,:z,:u,:v,:w,:a,:b,:c,:d
+    bit.inner :cmp
+
+    cmp <= (x >= y)
+    u   <= (x >= y)
+
+    sequencer(clk,rst) do
+        hif(5>4) { w <= _hFFFF }
+        helse    { w <= _h0000 }
+        swhile(w<_h0000) do
+            hif(5>6) { w <= _hFFFF }
+            helse    { w <= _h0000 }
+        end
+        5.stimes do
+            x <= _h0100
+            y <= _hFF34
+            a <= _h0100
+            b <= _h0100
+            c <= _h0100
+            step
+            x <= x*a
+            hif(x>=y) { z <= _hFFFF }
+            helse     { z <= _h0000 }
+            v <= mux(x>=y,_h0000,_hFFFF)
+            hif(10>0) { w <= _hFFFF }
+            helse     { w <= _h0000 }
+            d <= a*b*c
+            step
+            x <= _h0000
+            x <= x*a
+            y <= _hFE68
+            hif(x>=y) { z <= _hFFFF }
+            helse     { z <= _h0000 }
+            v <= mux(x>=y,_h0000,_hFFFF)
+            hif(1>20) { w <= _hFFFF }
+            helse     { w <= _h0000 }
+            a <= _h0200
+            d <= a*b*c
+            step
+            x <= _hFE00
+            x <= x*a
+            y <= _hFE02
+            hif(x>=y) { z <= _hFFFF }
+            helse     { z <= _h0000 }
+            v <= mux(x>=y,_h0000,_hFFFF)
+            b <= _h0200
+            d <= a*b*c
+        end
+    end
+
+    def cstep(n=1)
+        n.times do
+            clk <= ~clk
+            !10.ns
+        end
+    end
+
+    timed do
+        clk <= 0
+        rst <= 0
+        !10.ns
+        cstep(2)
+        rst <= 1
+        cstep(2)
+        rst <= 0
+        cstep(40)
+    end
+    
+end

data/lib/HDLRuby/hdr_samples/with_leftright.rb

@@ -3,7 +3,7 @@
 system :leftright_bench do
     [8].inner :l,:r0,:r1,:lr
 
-    par do
+    seq do
         lr <= r0*2
         l <= [lr[7],lr[6..0]].to_expr + r1
     end

data/lib/HDLRuby/hdr_samples/with_sequencer.rb

@@ -16,6 +16,7 @@ include HDLRuby::High::Std
 # - One sequencer puts the sum of two arrays in a third one.
 # - One sequencer iterates over two arrays.
 # - One sequencer iterates downward.
+# - One sequencer checks sub iterators (HDLRuby special).
 system :my_seqencer do
 
     inner :clk,:rst
@@ -161,6 +162,22 @@ system :my_seqencer do
         # hprint(")2 res6=",res6,"\n")
     end
 
+    [8].inner :res7,:res8
+
+    sequencer(clk.posedge,rst) do
+        res7 <= 0
+        res8 <= 0
+        ar0.seach_range(0..3) do |elem|
+            res7 <= elem
+        end
+        ar0.seach_range(4..9) do |elem|
+            res7 <= elem
+        end
+        (_h00.._h07).seach_range(1..4) do |elem|
+            res8 <= elem
+        end
+    end
+
 
     timed do
         clk <= 0

data/lib/HDLRuby/hdr_samples/with_sequencer_channel.rb

@@ -0,0 +1,58 @@
+require 'std/sequencer.rb'
+
+include HDLRuby::High::Std
+
+# Checking the usage of sequencers' channels.
+system :my_seqencer do
+
+    inner :clk,:rst,filled: 0
+    bit[16][-16].inner :mem
+    [16].inner :res0, :res1, :res2, :res3
+
+    ch_read = schannel(bit[16],16) do |i|
+        mem[i]
+    end
+
+    ch_write = schannel(bit[16],16) do |i,val|
+        mem[i] <= val
+    end
+
+    sequencer(clk.posedge,rst) do
+        16.stimes { |i| ch_write.snext!(i) }
+        filled <= 1
+        16.stimes do |i| 
+            res0 <= ch_read.snext 
+            res1 <= ch_read[15-i]
+        end
+    end
+
+    sequencer(clk.posedge,rst) do
+        swhile(~filled);
+        16.stimes do |i| 
+            res2 <= ch_read.snext 
+            res3 <= ch_read[15-i]
+        end
+    end
+
+
+    timed do
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        repeat(100) do
+            !10.ns
+            clk <= ~clk
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_sequencer_enumerable.rb

@@ -34,6 +34,7 @@ include HDLRuby::High::Std
 # - The twenty nineth sequencer checks stake and stake_while
 # - The thirtieth sequencer checks suniq
 # - The thirty first sequencer checks szip
+# - The thirty second sequnecer checks seach_nexts (HDLRuby special)
 #
 # __WARNING__: All the operations on enumerators generate their own result
 #              signal. Therefore, in a real circuit, there is no need to
@@ -414,6 +415,15 @@ system :my_seqencer do
         # hprint("}1 res52=",res52," res53=",res53,"\n")
     end
 
+    [8].inner :res54,:res55
+
+    sequencer(clk.posedge,rst) do
+        res54 <= 0
+        res55 <= 0
+        vals.seach_nexts(6) { |i| res54 <= i }
+        res55 <= vals.seach_nexts(4).ssum
+    end
+
 
 
     timed do

data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb

@@ -52,16 +52,30 @@ system :my_seqencer do
 
     data <= mem[addr]
 
-    mem_enum = senumerator(bit[8],8) do |i|
-        addr <= i
-        step
-        data
+    mem_enum = senumerator(bit[8],8) do |i,val|
+        if val then
+            # Write
+            mem[i] <= val
+            step
+            val
+        else 
+            # Read
+            addr <= i
+            step
+            data
+        end
     end
 
     sequencer(clk.posedge,rst) do
         # hprint("~0\n")
         res6 <= 0
         res6 <= mem_enum.ssum
+        mem_enum.srewind
+        mem_enum.snext!(_hAA)
+        mem_enum.snext!(_hBB)
+        mem_enum.srewind
+        res6 <= mem_enum.snext
+        res6 <= mem_enum.snext
         # hprint("~1 res6=",res6,"\n")
     end
 

data/lib/HDLRuby/hdr_samples/with_sequencer_sync.rb

@@ -13,7 +13,8 @@ system :my_seqencer do
     arbiter(:arbiter0).(x1)
 
     par(clk.posedge) do
-        x0.select <= x0.select + 1
+        hif(rst) { x0.select(0) }
+        helse { x0.select(x0.select + 1) }
     end
 
     sequencer(clk.posedge,rst) do

data/lib/HDLRuby/hdrcc.rb

@@ -84,6 +84,10 @@ require 'HDLRuby/backend/hruby_c_allocator'
 
 require 'HDLRuby/version.rb'
 
+# Global flags
+$sim = false     # Tells if hdrcc is in simulation mode
+$gen = false     # Tells if hdrcc is in hardware generation mode
+
 
 ##
 # HDLRuby compiler interface program
@@ -373,19 +377,23 @@ $optparse = OptionParser.new do |opts|
     opts.on("-S","--sim","Default simulator (hybrid C-Ruby)") do |v|
         $options[:rcsim] = v
         $options[:multiple] = v
+        $sim = true
     end
     opts.on("--csim","Standalone C-based simulator") do |v|
         $options[:clang] = v
         $options[:multiple] = v
         $options[:csim] = v
+        $sim = true
     end
     opts.on("--rsim","Ruby-based simulator") do |v|
         $options[:rsim] = v
         $options[:multiple] = v
+        $sim = true
     end
     opts.on("--rcsim","Hybrid C-Ruby-based simulator") do |v|
         $options[:rcsim] = v
         $options[:multiple] = v
+        $sim = true
     end
     opts.on("--mute", "The simulator will not generate any output") do |v|
         $options[:mute] = v
@@ -396,12 +404,14 @@ $optparse = OptionParser.new do |opts|
     opts.on("-v", "--verilog","Output in Verlog HDL format") do |v|
         $options[:verilog] = v
         $options[:multiple] = v
+        $gen = true
     end
     opts.on("-V", "--vhdl","Output in VHDL format") do |v|
         HDLRuby::Low::Low2VHDL.vhdl08 = false
         $options[:vhdl] = v
         $options[:multiple] = v
         $options[:vhdl08] = false
+        $gen = true
     end
     opts.on("-A", "--alliance","Output in Alliance-compatible VHDL format") do |v|
         HDLRuby::Low::Low2VHDL.vhdl08 = false
@@ -410,12 +420,14 @@ $optparse = OptionParser.new do |opts|
         $options[:alliance] = v
         $options[:multiple] = v
         $options[:vhdl08] = false
+        $gen = true
     end
     opts.on("-U", "--vhdl08","Output in VHDL'08 format") do |v|
         HDLRuby::Low::Low2VHDL.vhdl08 = true
         $options[:vhdl] = v
         $options[:multiple] = v
         $options[:vhdl08] = true
+        $gen = true
     end
     opts.on("-s", "--syntax","Output the Ruby syntax tree") do |s|
         $options[:syntax] = s

data/lib/HDLRuby/hruby_high.rb

@@ -880,9 +880,11 @@ module HDLRuby::High
                       "Cannot convert a system without a name to HDLRuby::Low."
             end
             # Create the resulting low system type.
-            # systemTL = HDLRuby::Low::SystemT.new(High.names_create(name),
-            systemTL = HDLRuby::Low::SystemT.new(HDLRuby.uniq_name(name),
-                                                   self.scope.to_low)
+            # systemTL = HDLRuby::Low::SystemT.new(HDLRuby.uniq_name(name),
+            #                                        self.scope.to_low)
+            systemTLN = HDLRuby.uniq_name(name)
+            systemTL = HDLRuby::Low::SystemT.new(systemTLN,
+                                                   self.scope.to_low(systemTLN))
             # puts "New low from system #{self.name}: #{systemTL.name}"
             # # For debugging: set the source high object 
             # systemTL.properties[:low2high] = self.hdr_id
@@ -1168,6 +1170,17 @@ module HDLRuby::High
             self.parent.inout(*names)
         end
 
+        # Declares a program in language +lang+ with start function named +func+
+        # and accessed expressions an code given in +args+.
+        def program(lang, func, *args)
+            # Create the program.
+            prog = Program.new(lang, func, *args)
+            # Adds the resulting program to the current scope.
+            HDLRuby::High.top_user.add_program(prog)
+            # Return the resulting program
+            return prog
+        end
+
         # Declares a non-HDLRuby set of code chunks described by +content+ and
         # completed from +ruby_block+ execution result.
         # NOTE: content includes the events to activate the code on and
@@ -1512,6 +1525,8 @@ module HDLRuby::High
                     scopeL.add_systemT(systemI_low.systemT)
                 }
             end
+            # Adds the programs.
+            self.each_program { |prog| scopeL.add_program(prog.to_low) }
             # Adds the code chunks.
             self.each_code { |code| scopeL.add_code(code.to_low) }
             # Adds the connections.
@@ -1526,10 +1541,15 @@ module HDLRuby::High
         end
 
         # Converts the scope to HDLRuby::Low.
-        def to_low()
+        # +name+ is the name of the system containing the new low scope in case
+        # of top scope, should be used as name for it.
+        # NOTE: by convention, the name of the top scope is the name of the
+        # system.
+        def to_low(low_name = nil)
             # Create the resulting low scope.
             # scopeL = HDLRuby::Low::Scope.new()
-            scopeL = HDLRuby::Low::Scope.new(self.name)
+            low_name = self.name unless low_name
+            scopeL = HDLRuby::Low::Scope.new(low_name)
             # # For debugging: set the source high object 
             # scopeL.properties[:low2high] = self.hdr_id
             # self.properties[:high2low] = scopeL
@@ -1974,7 +1994,7 @@ module HDLRuby::High
                 raise AnyError, "Generic type #{self.name} did not produce a valid type: #{gtype.class}"
             end
             # Create a new type definition from it.
-            gtype = TypeDef.new(self.name.to_s + "_#{args.join(":")}",
+            gtype = TypeDef.new(self.name.to_s + "_#{args.join(':')}",
                                    gtype)
             # Adds the possible overloaded operators.
             self.each_overload do |op,ruby_block|
@@ -2168,6 +2188,7 @@ module HDLRuby::High
 
     # Methods for declaring systems
 
+
     # Declares a high-level system type named +name+, with +includes+ mixins
     # system types and using +ruby_block+ for instantiating.
     def system(name = :"", *includes, &ruby_block)
@@ -2294,24 +2315,8 @@ module HDLRuby::High
                 # Performs the connections.
                 connects.each do |key,value|
                     # Gets the signal corresponding to connect.
-                    # signal = self.get_signal(key)
-                    # unless signal then
-                    #     # Look into the included systems.
-                    #     self.systemT.scope.each_included do |included|
-                    #         signal = included.get_signal(key)
-                    #         break if signal
-                    #     end
-                    # end
                     signal = self.systemT.get_signal_with_included(key)
                     # Check if it is an output.
-                    # isout = self.get_output(key)
-                    # unless isout then
-                    #     # Look into the inlucded systems.
-                    #     self.systemT.scope.each_included do |included|
-                    #         isout = included.get_output(key)
-                    #         break if isout
-                    #     end
-                    # end
                     isout = self.systemT.get_output_with_included(key)
                     # Convert it to a reference.
                     # puts "key=#{key} value=#{value} signal=#{signal}"
@@ -2441,7 +2446,6 @@ module HDLRuby::High
 
         # Gets the private namespace.
         def namespace
-            # self.systemT.scope.namespace
             self.systemT.namespace
         end
 
@@ -2492,6 +2496,25 @@ module HDLRuby::High
         end
     end
 
+
+
+
+    ##
+    # Describes a program.
+    class Program < HDLRuby::Low::Program
+        # Converts the if to HDLRuby::Low.
+        def to_low
+            # Create the resulting program.
+            progL = HDLRuby::Low::Program.new(self.lang,self.function,
+                                            *self.each_expression.map(&:to_low),
+                                            *self.each_event.map(&:to_low),
+                                            *self.each_code)
+            # Return the resulting program.
+            return progL
+        end
+    end
+
+
     ##
     # Decribes a set of non-HDLRuby code chunks.
     class Code < HDLRuby::Low::Code
@@ -3336,6 +3359,24 @@ module HDLRuby::High
                 include HExpression
                 include HArrow
 
+                # Update the initialize to handle struct types accesses if
+                # it is not a RefObject, this latter being a proxy to a
+                # real component.
+                if klass != RefObject then
+                    original_initialize = instance_method(:initialize)
+                    define_method(:initialize) do |*args, &block|
+                        original_initialize.bind(self).call(*args,&block)
+                        # Now process it if it is a structured type.
+                        if self.type.struct? then
+                            self.type.each do |name,typ|
+                                self.define_singleton_method(name) do
+                                    RefName.new(typ,self,name)
+                                end
+                            end
+                        end
+                    end
+                end
+
                 # Converts to a new expression.
                 def to_expr
                     self.to_ref
@@ -3436,15 +3477,22 @@ module HDLRuby::High
         # Converts the name reference to a HDLRuby::Low::RefName.
         def to_low
             # puts "to_low with base=#{@base} @object=#{@object}"
-            # puts "@object.name=#{@object.name}"
+            # puts "@object.name=#{@object.name} @object.parent=#{@object.parent.name}"
             if @base.is_a?(RefThis) && 
                     (@object.parent != High.top_user) &&
                     (@object.parent != High.cur_system) &&
+                    (@object.parent != High.cur_system.scope) &&
                     (!@object.parent.name.empty?) then
                 # Need to have a hierachical access.
-                # puts "Indirect access for #{self.object.name}: #{self.object.parent.name}(#{self.object.parent.class}) != #{High.cur_system.name}(#{High.top_user.class})"
-                refNameL = HDLRuby::Low::RefName.new(self.type.to_low,
+                if @object.respond_to?(:low_object) && @object.low_object then
+                    # There where already a low object, create the ref from it.
+                    # puts "absolute ref!"
+                    refNameL = @object.low_object.absolute_ref
+                else
+                    # No create the indirect reference.
+                    refNameL = HDLRuby::Low::RefName.new(self.type.to_low,
                                                      @object.parent.to_ref.to_low,@object.name)
+                end
             else
                 # Direct access is enough.
                 refNameL = HDLRuby::Low::RefName.new(self.type.to_low,
@@ -3972,11 +4020,19 @@ module HDLRuby::High
             return [obj,self.to_expr]
         end
 
+        # Get the low version off the object.
+        # NOTE: only useful for Signals and SystemIs since they can be accessed
+        # from outside the module they have been defined in.
+        def low_object
+            return @low_object
+        end
+
         # Converts the system to HDLRuby::Low and set its +name+.
         def to_low(name = self.name)
             # return HDLRuby::Low::SignalI.new(name,self.type.to_low)
             valueL = self.value ? self.value.to_low : nil
             signalIL = HDLRuby::Low::SignalI.new(name,self.type.to_low,valueL)
+            @low_object = signalIL
             # Recurse on the sub signals if any.
             self.each_signal do |sig|
                 signalIL.add_signal(sig.to_low)