HDLRuby 2.4.27 → 2.6.2
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- checksums.yaml +4 -4
- data/lib/HDLRuby/drivers/xcd.rb +79 -0
- data/lib/HDLRuby/drivers/xcd/dummy.xcd +4 -0
- data/lib/HDLRuby/hdr_samples/adder.rb +1 -1
- data/lib/HDLRuby/hdr_samples/adder_bench.rb +1 -1
- data/lib/HDLRuby/hdr_samples/adder_gen.rb +1 -1
- data/lib/HDLRuby/hdr_samples/constant_in_function.rb +27 -0
- data/lib/HDLRuby/hdr_samples/dff_properties.rb +19 -0
- data/lib/HDLRuby/hdr_samples/dff_unit.rb +54 -0
- data/lib/HDLRuby/hdr_samples/huge_rom.rb +25 -0
- data/lib/HDLRuby/hdr_samples/logic_bench.rb +21 -0
- data/lib/HDLRuby/hdr_samples/mei8_bench.rb +1 -1
- data/lib/HDLRuby/hdr_samples/music.rb +79 -0
- data/lib/HDLRuby/hdr_samples/named_sub.rb +42 -0
- data/lib/HDLRuby/hdr_samples/rom.rb +16 -0
- data/lib/HDLRuby/hdr_samples/seqpar_bench.rb +59 -0
- data/lib/HDLRuby/hdr_samples/with_function_generator.rb +25 -0
- data/lib/HDLRuby/hdrcc.rb +140 -24
- data/lib/HDLRuby/hruby_decorator.rb +250 -0
- data/lib/HDLRuby/hruby_high.rb +468 -91
- data/lib/HDLRuby/hruby_low.rb +913 -45
- data/lib/HDLRuby/hruby_low2c.rb +189 -168
- data/lib/HDLRuby/hruby_low2hdr.rb +738 -0
- data/lib/HDLRuby/hruby_low2high.rb +331 -549
- data/lib/HDLRuby/hruby_low2vhd.rb +39 -2
- data/lib/HDLRuby/hruby_low_bool2select.rb +29 -0
- data/lib/HDLRuby/hruby_low_casts_without_expression.rb +27 -0
- data/lib/HDLRuby/hruby_low_fix_types.rb +25 -0
- data/lib/HDLRuby/hruby_low_mutable.rb +70 -0
- data/lib/HDLRuby/hruby_low_resolve.rb +28 -0
- data/lib/HDLRuby/hruby_low_without_connection.rb +6 -3
- data/lib/HDLRuby/hruby_low_without_namespace.rb +7 -4
- data/lib/HDLRuby/hruby_low_without_parinseq.rb +151 -0
- data/lib/HDLRuby/hruby_low_without_select.rb +13 -0
- data/lib/HDLRuby/hruby_tools.rb +11 -1
- data/lib/HDLRuby/hruby_verilog.rb +1602 -1629
- data/lib/HDLRuby/sim/hruby_sim.h +25 -2
- data/lib/HDLRuby/sim/hruby_sim_calc.c +63 -6
- data/lib/HDLRuby/sim/hruby_sim_vcd.c +5 -1
- data/lib/HDLRuby/sim/hruby_sim_vizualize.c +22 -6
- data/lib/HDLRuby/std/fixpoint.rb +9 -0
- data/lib/HDLRuby/std/function_generator.rb +139 -0
- data/lib/HDLRuby/std/hruby_unit.rb +75 -0
- data/lib/HDLRuby/template_expander.rb +61 -0
- data/lib/HDLRuby/version.rb +1 -1
- metadata +22 -5
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 8611332c824fad3b8ad75436070b940389c1d8cf75c66be0842cd5f4efd22340
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data.tar.gz: 71f3633a674d50a2b4014654d6af82066bc9e8e399e6cdddb733827411ea2787
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 8316f77bab49fc0899074915a18292f357b45c5e5415b3045f74b80f67260566797e8ffc0edf8b6eaca86340c32adfde49650edddfaa91cad03efd1e6e9f729c
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data.tar.gz: 117236582bbca17d1ee75a2e3fb4c601ef53b1988f4175a7f77632f9c85a79e5af3e3474463f654c05a48ecdcabd73967d447b90f7640451f1bc3a24d99fd2ec
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@@ -0,0 +1,79 @@
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require "HDLRuby/template_expander"
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##
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# XCD file generator from 'xcd' properties
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##########################################
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# Generates a xcd file from the HDLRuby objects from +top+ using
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# their 'xcd' properties.
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# The file is saved in +path+ directory.
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def xcd_generator(top, path)
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# Ensure top is a system.
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if top.is_a?(HDLRuby::Low::SystemI) then
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top = top.systemT
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15
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+
elsif !top.is_a?(HDLRuby::Low::SystemT) then
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raise "The 'xcd_generator' driver can only be applied on SystemT objects."
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+
end
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# Get the name of the resulting file if any.
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if (top.properties.key?(:xcd_file)) then
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xcd_file = top.properties[:xcd_file].join
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else
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# Default file name.
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xcd_file = "default.xcd"
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end
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# Get the target template.
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xcd_target = top.properties[:xcd_target].join
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xcd_target_name = xcd_target
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xcd_target_name += ".xcd" unless xcd_target_name.end_with?(".xcd")
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xcd_target_tries = [ xcd_target_name,
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File.join(path,xcd_target_name),
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File.join(File.dirname(__FILE__),"xcd",xcd_target_name) ]
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xcd_target_file = xcd_target_tries.find { |fname| File.exist?(fname) }
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unless xcd_target_file then
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raise "XCD target template not found for #{xcd_target}."
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+
end
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# Load the template.
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template = File.read(xcd_target_file)
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+
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# Gather the signals by xcd key.
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xcd2sig = top.each_signal.reduce([]) do |ar,sig|
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ar += sig.properties.each_with_key(:xcd).map do |val|
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[val,sig.name.to_s]
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end
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end
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+
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# Create the template expander that will generate the xcd file.
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expander = TemplateExpander.new([
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[ /^\?.*(\n|\z)/, proc do |str| # Signal link to port
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if xcd2sig.any? do |match,rep|
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if str.include?(match) then
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str = str.gsub("<>",rep)[1..-1]
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else
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false
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end
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end then
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str
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else
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""
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end
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end ]
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])
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# # Generate the xcd file.
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# File.open(File.join(path,xcd_file),"w") do |file|
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# # Generate the signals mapping.
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# top.each_signal do |signal|
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# signal.properties.each_with_key(:xcd) do |value|
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# file << "#{value}\n"
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# end
|
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# end
|
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# end
|
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|
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# Generate the xcd file.
|
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File.open(File.join(path,xcd_file),"w") do |file|
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expander.expand(template,file)
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end
|
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end
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@@ -0,0 +1,27 @@
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# Sample for testing constant declaration in function.
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function :func do |addr|
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bit[4][-4].constant tbl: [ _0000, _0001, _0010, _0011 ]
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tbl[addr]
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end
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system :with_func do
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[4].inner :addr, :val
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val <= func(addr)
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# val <= 1
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timed do
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addr <= 0
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!10.ns
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addr <= 1
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!10.ns
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addr <= 2
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!10.ns
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addr <= 3
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!10.ns
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end
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end
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@@ -0,0 +1,19 @@
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# A simple D-FF
|
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system :dff do
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input :clk, :rst, :d
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output :q, :qb
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qb <= ~q
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par(clk.posedge) { q <= d & ~rst }
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clk.properties[:xcd] = "CLK"
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rst.properties[:xcd] = "RST"
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d.properties[:xcd] = "PORT0"
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q.properties[:xcd] = "PORT1"
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14
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qb.properties[:xcd] = "PORT2"
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cur_system.properties[:xcd_target] = "dummy"
|
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cur_system.properties[:xcd_file] = "dff.xcd"
|
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cur_system.properties[:post_driver] = "drivers/xcd.rb", :xcd_generator
|
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end
|
19
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@@ -0,0 +1,54 @@
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# Testing HDLRuby unit test.
|
2
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# require 'std/hruby_unit.rb'
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+
|
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# Declare multiple simple dff-systems and their corresponding test.
|
5
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3.times do |i|
|
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+
|
8
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# A simple D-FF
|
9
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system:"dff#{i}" do
|
10
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input :clk, :rst, :d
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output :q, :qb
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12
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qb <= ~q
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14
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par(clk.posedge) { q <= d & ~rst }
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end
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17
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+
|
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# Code for testing it.
|
19
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Unit.system :"test_dff#{i}" do
|
20
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inner :clk, :rst, :d, :q, :qb
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send(:"dff#{i}",:dffI).(clk,rst,d,q,qb)
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test do
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25
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clk <= 0
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rst <= 0
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d <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 1
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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d <= 1
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!10.ns
|
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clk <= 1
|
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!10.ns
|
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clk <= 0
|
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d <= 0
|
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!10.ns
|
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clk <= 1
|
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!10.ns
|
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end
|
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end
|
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end
|
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@@ -0,0 +1,25 @@
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# Describes an 8-bit data 16-bit address ROM.
|
2
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system :huge_rom do
|
3
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[15..0].input :addr
|
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[7..0].output :data
|
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+
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bit[7..0][-65536].constant content: 65536.times.to_a
|
7
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|
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data <= content[addr]
|
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end
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11
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|
13
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system :test_rom do
|
14
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[15..0].inner :addr
|
15
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[7..0].inner :data
|
16
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+
|
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huge_rom(:my_rom).(addr,data)
|
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+
|
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timed do
|
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8.times do |i|
|
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addr <= i
|
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!10.ns
|
23
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end
|
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end
|
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end
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@@ -0,0 +1,21 @@
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# A benchmark for the logic operations.
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system :logic_bench do
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4
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[3].inner :x,:y
|
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[3].inner :s_not, :s_and, :s_or, :s_xor, :s_nxor
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timed do
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8
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8.times do |i|
|
9
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8.times do |j|
|
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x <= i
|
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y <= j
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s_not <= ~x
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s_and <= x & y
|
14
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s_or <= x | y
|
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s_xor <= x ^ y
|
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s_nxor <= (x == y)
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!10.ns
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end
|
19
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end
|
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end
|
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end
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@@ -28,7 +28,7 @@ system :mei8 do |prog_file = "./prog.obj"|
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28
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bit[7..0][-256].constant mem: # The content of the memory
|
29
29
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( File.readlines(prog_file).map {|l| l.split[0] }.select do |l|
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30
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["0","1"].include?(l[2])
|
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-
end.map {|l| l[2..9] } )
|
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end.map {|l| l[2..9].to_i(2) } )
|
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32
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instr <= mem[addr] # The access procedure
|
33
33
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end
|
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34
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@@ -0,0 +1,79 @@
|
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1
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# require "std/fixpoint.rb"
|
2
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# require_relative "activation_function.rb"
|
3
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require 'std/function_generator.rb'
|
4
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+
|
5
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include HDLRuby::High::Std
|
6
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+
|
7
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system :music do
|
8
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+
|
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input :clk, :rst
|
10
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[24].output :sound
|
11
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+
|
12
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# func_sin = proc { |i| Math.sin(i) }
|
13
|
+
# More efficient:
|
14
|
+
func_sin = Math.method(:sin)
|
15
|
+
|
16
|
+
# bit[8,8].inner :time
|
17
|
+
# signed[2,22].inner :sin_val0
|
18
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# signed[2,22].inner :sin_val1
|
19
|
+
bit[8].inner :time
|
20
|
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signed[24].inner :sin_val0
|
21
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signed[24].inner :sin_val1
|
22
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+
|
23
|
+
# activation_function(func_sin,signed[2,22],8,8,16).(:func_sin0_generator).(time,sin_val0)
|
24
|
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# activation_function(func_sin,signed[2,22],8,8,16).(:func_sin1_generator).(time/2,sin_val1)
|
25
|
+
function_generator(func_sin,bit[8],signed[24],4,-Math::PI..Math::PI,-2..2).(:func_sin0_generator).(time,sin_val0)
|
26
|
+
function_generator(func_sin,bit[8],signed[24],4,-Math::PI*2..Math::PI*2,-2..2).(:func_sin1_generator).(time/2,sin_val1)
|
27
|
+
|
28
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# signed[2,22].inner :sound0
|
29
|
+
signed[48].inner :sound0
|
30
|
+
|
31
|
+
sound0 <= sin_val0.as(signed[24]) * sin_val1
|
32
|
+
|
33
|
+
sound <= sound0[47..24]
|
34
|
+
|
35
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par(clk.posedge) do
|
36
|
+
hif(rst) { time <= 0 }
|
37
|
+
helse do
|
38
|
+
# time <= time + _0000000000000001
|
39
|
+
time <= time + _00000001
|
40
|
+
end
|
41
|
+
end
|
42
|
+
|
43
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+
end
|
44
|
+
|
45
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+
|
46
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+
|
47
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+
|
48
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+
system :music_test do
|
49
|
+
|
50
|
+
inner :clk,:rst
|
51
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+
[24].inner :sound
|
52
|
+
|
53
|
+
music(:my_music).(clk,rst,sound)
|
54
|
+
|
55
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+
timed do
|
56
|
+
clk <= 0
|
57
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+
rst <= 0
|
58
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+
!10.ns
|
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+
clk <= 1
|
60
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+
!10.ns
|
61
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+
clk <= 0
|
62
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+
rst <= 1
|
63
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+
!10.ns
|
64
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+
clk <= 1
|
65
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+
!10.ns
|
66
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+
clk <= 0
|
67
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+
!10.ns
|
68
|
+
clk <= 1
|
69
|
+
!10.ns
|
70
|
+
clk <= 0
|
71
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+
rst <= 0
|
72
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+
256.times do
|
73
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+
!10.ns
|
74
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+
clk <= 1
|
75
|
+
!10.ns
|
76
|
+
clk <= 0
|
77
|
+
end
|
78
|
+
end
|
79
|
+
end
|
@@ -0,0 +1,42 @@
|
|
1
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##
|
2
|
+
# Sample testing named sub
|
3
|
+
#######################################
|
4
|
+
|
5
|
+
|
6
|
+
# A simple circuit with named sub
|
7
|
+
system :named_sub do
|
8
|
+
input :x, :y
|
9
|
+
output :s
|
10
|
+
|
11
|
+
sub :somesub do
|
12
|
+
inner :sig
|
13
|
+
end
|
14
|
+
|
15
|
+
seq do
|
16
|
+
somesub.sig <= x | y
|
17
|
+
s <= ~somesub.sig
|
18
|
+
end
|
19
|
+
|
20
|
+
end
|
21
|
+
|
22
|
+
# A benchmark for the circuit.
|
23
|
+
system :named_sub_bench do
|
24
|
+
inner :x, :y, :s
|
25
|
+
|
26
|
+
named_sub(:my_named_sub).(x,y,s)
|
27
|
+
|
28
|
+
timed do
|
29
|
+
x <= 0
|
30
|
+
y <= 0
|
31
|
+
!10.ns
|
32
|
+
x <= 1
|
33
|
+
y <= 0
|
34
|
+
!10.ns
|
35
|
+
x <= 0
|
36
|
+
y <= 1
|
37
|
+
!10.ns
|
38
|
+
x <= 1
|
39
|
+
y <= 1
|
40
|
+
!10.ns
|
41
|
+
end
|
42
|
+
end
|
@@ -14,3 +14,19 @@ system :rom4_8 do
|
|
14
14
|
data1 <= content1[addr]
|
15
15
|
data2 <= content2[addr]
|
16
16
|
end
|
17
|
+
|
18
|
+
|
19
|
+
|
20
|
+
system :test_rom do
|
21
|
+
[2..0].inner :addr
|
22
|
+
[7..0].inner :data0,:data1,:data2
|
23
|
+
|
24
|
+
rom4_8(:my_rom).(addr,data0,data1,data2)
|
25
|
+
|
26
|
+
timed do
|
27
|
+
8.times do |i|
|
28
|
+
addr <= i
|
29
|
+
!10.ns
|
30
|
+
end
|
31
|
+
end
|
32
|
+
end
|
@@ -0,0 +1,59 @@
|
|
1
|
+
# require "../hruby_low2c.rb"
|
2
|
+
|
3
|
+
|
4
|
+
|
5
|
+
# A system for testing the execution of par block in seq block.
|
6
|
+
system :seqpar_bench do
|
7
|
+
|
8
|
+
inner :rst, :clk
|
9
|
+
signed[8].inner :a, :b, :c, :d
|
10
|
+
signed[8].inner :out
|
11
|
+
|
12
|
+
seq(clk.posedge) do
|
13
|
+
hif(rst) do
|
14
|
+
a <= 0
|
15
|
+
b <= 0
|
16
|
+
c <= 0
|
17
|
+
d <= 0
|
18
|
+
end
|
19
|
+
helse do
|
20
|
+
a <= a + 1
|
21
|
+
b <= a + 2
|
22
|
+
par do
|
23
|
+
c <= b + 3
|
24
|
+
d <= c + 4
|
25
|
+
end
|
26
|
+
a <= d + 5
|
27
|
+
end
|
28
|
+
end
|
29
|
+
|
30
|
+
out <= a
|
31
|
+
|
32
|
+
timed do
|
33
|
+
clk <= 0
|
34
|
+
rst <= 0
|
35
|
+
!20.ns
|
36
|
+
clk <= 1
|
37
|
+
!20.ns
|
38
|
+
clk <= 0
|
39
|
+
rst <= 1
|
40
|
+
!20.ns
|
41
|
+
clk <= 1
|
42
|
+
!20.ns
|
43
|
+
clk <= 0
|
44
|
+
rst <= 0
|
45
|
+
!20.ns
|
46
|
+
clk <= 1
|
47
|
+
!20.ns
|
48
|
+
clk <= 0
|
49
|
+
!20.ns
|
50
|
+
clk <= 1
|
51
|
+
!20.ns
|
52
|
+
clk <= 0
|
53
|
+
!20.ns
|
54
|
+
clk <= 1
|
55
|
+
!20.ns
|
56
|
+
clk <= 0
|
57
|
+
!20.ns
|
58
|
+
end
|
59
|
+
end
|