HDLRuby 2.4.27 → 2.6.2

checksums.yaml

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data/lib/HDLRuby/drivers/xcd.rb

@@ -0,0 +1,79 @@
+require "HDLRuby/template_expander"
+
+##
+# XCD file generator from 'xcd' properties
+##########################################
+
+
+# Generates a xcd file from the HDLRuby objects from +top+ using
+# their 'xcd' properties.
+# The file is saved in +path+ directory.
+def xcd_generator(top, path)
+    # Ensure top is a system.
+    if top.is_a?(HDLRuby::Low::SystemI) then
+        top = top.systemT
+    elsif !top.is_a?(HDLRuby::Low::SystemT) then
+        raise "The 'xcd_generator' driver can only be applied on SystemT objects."
+    end
+
+    # Get the name of the resulting file if any.
+    if (top.properties.key?(:xcd_file)) then
+        xcd_file = top.properties[:xcd_file].join
+    else
+        # Default file name.
+        xcd_file = "default.xcd"
+    end
+
+    # Get the target template.
+    xcd_target       = top.properties[:xcd_target].join
+    xcd_target_name  = xcd_target
+    xcd_target_name += ".xcd" unless xcd_target_name.end_with?(".xcd")
+    xcd_target_tries = [ xcd_target_name,
+                         File.join(path,xcd_target_name),
+                         File.join(File.dirname(__FILE__),"xcd",xcd_target_name) ]
+    xcd_target_file = xcd_target_tries.find { |fname| File.exist?(fname) }
+    unless xcd_target_file then
+        raise "XCD target template not found for #{xcd_target}."
+    end
+    # Load the template.
+    template = File.read(xcd_target_file)
+
+    # Gather the signals by xcd key.
+    xcd2sig = top.each_signal.reduce([]) do |ar,sig|
+        ar += sig.properties.each_with_key(:xcd).map do |val|
+            [val,sig.name.to_s]
+        end
+    end
+
+    # Create the template expander that will generate the xcd file.
+    expander = TemplateExpander.new([
+        [ /^\?.*(\n|\z)/, proc do |str| # Signal link to port
+            if xcd2sig.any? do |match,rep|
+                if str.include?(match) then
+                    str = str.gsub("<>",rep)[1..-1]
+                else
+                    false
+                end
+            end then
+            str
+            else
+                ""
+            end
+        end ]
+    ])
+
+    # # Generate the xcd file.
+    # File.open(File.join(path,xcd_file),"w") do |file|
+    #     # Generate the signals mapping.
+    #     top.each_signal do |signal|
+    #         signal.properties.each_with_key(:xcd) do |value|
+    #             file << "#{value}\n"
+    #         end
+    #     end
+    # end
+    
+    # Generate the xcd file.
+    File.open(File.join(path,xcd_file),"w") do |file|
+        expander.expand(template,file)
+    end
+end

data/lib/HDLRuby/drivers/xcd/dummy.xcd

@@ -0,0 +1,4 @@
+<Dummy xcd template>
+?<PORT <> CLK>
+?<PORT <> RST>
+

data/lib/HDLRuby/hdr_samples/adder.rb

@@ -3,5 +3,5 @@ system :adder do
     [15..0].input :x,:y
     [16..0].output :s
 
-    s <= x + y
+    s <= x.as(bit[17]) + y
 end

data/lib/HDLRuby/hdr_samples/adder_bench.rb

@@ -3,7 +3,7 @@ system :adder do
     [15..0].input :x,:y
     [16..0].output :s
 
-    s <= x + y
+    s <= x.as(bit[17]) + y
 end
 
 # A benchmark for the adder.

data/lib/HDLRuby/hdr_samples/adder_gen.rb

@@ -3,5 +3,5 @@ system :adder do |w|
     [(w-1)..0].input :x,:y
     [w..0].output :s
 
-    s <= x + y
+    s <= x.as(bit[w+1]) + y
 end

data/lib/HDLRuby/hdr_samples/constant_in_function.rb

@@ -0,0 +1,27 @@
+# Sample for testing constant declaration in function.
+
+
+function :func do |addr|
+    bit[4][-4].constant tbl: [ _0000, _0001, _0010, _0011 ]
+    
+    tbl[addr]
+end
+
+
+system :with_func do
+    [4].inner :addr, :val
+
+    val <= func(addr)
+    # val <= 1
+
+    timed do
+        addr <= 0
+        !10.ns
+        addr <= 1
+        !10.ns
+        addr <= 2
+        !10.ns
+        addr <= 3
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/dff_properties.rb

@@ -0,0 +1,19 @@
+# A simple D-FF
+system :dff do
+    input :clk, :rst, :d
+    output :q, :qb
+
+    qb <= ~q
+
+    par(clk.posedge) { q <= d & ~rst }
+
+    clk.properties[:xcd] = "CLK"
+    rst.properties[:xcd] = "RST"
+    d.properties[:xcd]   = "PORT0"
+    q.properties[:xcd]   = "PORT1"
+    qb.properties[:xcd]  = "PORT2"
+    cur_system.properties[:xcd_target] = "dummy"
+    cur_system.properties[:xcd_file] = "dff.xcd"
+    cur_system.properties[:post_driver] = "drivers/xcd.rb", :xcd_generator
+end
+

data/lib/HDLRuby/hdr_samples/dff_unit.rb

@@ -0,0 +1,54 @@
+# Testing HDLRuby unit test.
+# require 'std/hruby_unit.rb' 
+
+# Declare multiple simple dff-systems and their corresponding test.
+
+3.times do |i|
+
+    # A simple D-FF
+    system:"dff#{i}" do
+        input :clk, :rst, :d
+        output :q, :qb
+
+        qb <= ~q
+
+        par(clk.posedge) { q <= d & ~rst }
+    end
+
+    # Code for testing it.
+    Unit.system :"test_dff#{i}" do
+        inner :clk, :rst, :d, :q, :qb
+
+        send(:"dff#{i}",:dffI).(clk,rst,d,q,qb)
+
+        test do
+            clk <= 0
+            rst <= 0
+            d   <= 0
+            !10.ns
+            clk <= 1
+            !10.ns
+            clk <= 0
+            rst <= 1
+            !10.ns
+            clk <= 1
+            !10.ns
+            clk <= 0
+            rst <= 0
+            !10.ns
+            clk <= 1
+            !10.ns
+            clk <= 0
+            d   <= 1
+            !10.ns
+            clk <= 1
+            !10.ns
+            clk <= 0
+            d   <= 0
+            !10.ns
+            clk <= 1
+            !10.ns
+        end
+    end
+end
+

data/lib/HDLRuby/hdr_samples/huge_rom.rb

@@ -0,0 +1,25 @@
+# Describes an 8-bit data 16-bit address ROM.
+system :huge_rom do
+    [15..0].input :addr
+    [7..0].output :data
+
+    bit[7..0][-65536].constant content: 65536.times.to_a
+
+    data <= content[addr]
+end
+
+
+
+system :test_rom do
+    [15..0].inner :addr
+    [7..0].inner :data
+
+    huge_rom(:my_rom).(addr,data)
+
+    timed do
+        8.times do |i|
+            addr <= i
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/logic_bench.rb

@@ -0,0 +1,21 @@
+
+# A benchmark for the logic operations.
+system :logic_bench do
+    [3].inner :x,:y
+    [3].inner :s_not, :s_and, :s_or, :s_xor, :s_nxor
+
+    timed do
+        8.times do |i|
+            8.times do |j|
+                x      <= i
+                y      <= j
+                s_not  <= ~x
+                s_and  <= x & y
+                s_or   <= x | y
+                s_xor  <= x ^ y
+                s_nxor <= (x == y)
+                !10.ns
+            end
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/mei8_bench.rb

@@ -28,7 +28,7 @@ system :mei8 do |prog_file = "./prog.obj"|
         bit[7..0][-256].constant mem: # The content of the memory
             ( File.readlines(prog_file).map {|l| l.split[0] }.select do |l|
             ["0","1"].include?(l[2])
-        end.map {|l| l[2..9] } )
+        end.map {|l| l[2..9].to_i(2) } )
         instr <= mem[addr]       # The access procedure
     end
 

data/lib/HDLRuby/hdr_samples/music.rb

@@ -0,0 +1,79 @@
+# require "std/fixpoint.rb"
+# require_relative "activation_function.rb"
+require 'std/function_generator.rb'
+
+include HDLRuby::High::Std
+
+system :music do
+
+   input :clk, :rst
+   [24].output :sound 
+   
+   # func_sin = proc { |i| Math.sin(i) }
+   # More efficient:
+   func_sin = Math.method(:sin)
+
+   # bit[8,8].inner :time
+   # signed[2,22].inner :sin_val0
+   # signed[2,22].inner :sin_val1
+   bit[8].inner :time
+   signed[24].inner :sin_val0
+   signed[24].inner :sin_val1
+
+   # activation_function(func_sin,signed[2,22],8,8,16).(:func_sin0_generator).(time,sin_val0)
+   # activation_function(func_sin,signed[2,22],8,8,16).(:func_sin1_generator).(time/2,sin_val1)
+   function_generator(func_sin,bit[8],signed[24],4,-Math::PI..Math::PI,-2..2).(:func_sin0_generator).(time,sin_val0)
+   function_generator(func_sin,bit[8],signed[24],4,-Math::PI*2..Math::PI*2,-2..2).(:func_sin1_generator).(time/2,sin_val1)
+
+   # signed[2,22].inner :sound0
+   signed[48].inner :sound0
+
+   sound0 <= sin_val0.as(signed[24]) * sin_val1
+
+   sound <= sound0[47..24]
+
+   par(clk.posedge) do
+      hif(rst) { time <= 0 }
+      helse do
+        # time <= time + _0000000000000001
+        time <= time + _00000001
+      end
+   end
+
+end
+
+
+
+
+system :music_test do
+
+    inner :clk,:rst
+    [24].inner :sound
+
+    music(:my_music).(clk,rst,sound)
+
+    timed do
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        256.times do
+            !10.ns
+            clk <= 1
+            !10.ns
+            clk <= 0
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/named_sub.rb

@@ -0,0 +1,42 @@
+## 
+#  Sample testing named sub
+#######################################
+
+
+# A simple circuit with named sub
+system :named_sub do
+    input  :x, :y
+    output :s
+
+    sub :somesub do
+        inner :sig
+    end
+
+    seq do
+        somesub.sig <= x | y
+        s <= ~somesub.sig
+    end
+
+end
+
+# A benchmark for the circuit.
+system :named_sub_bench do
+    inner :x, :y, :s
+
+    named_sub(:my_named_sub).(x,y,s)
+
+    timed do
+        x <= 0
+        y <= 0
+        !10.ns
+        x <= 1
+        y <= 0
+        !10.ns
+        x <= 0
+        y <= 1
+        !10.ns
+        x <= 1
+        y <= 1
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/rom.rb

@@ -14,3 +14,19 @@ system :rom4_8 do
     data1 <= content1[addr]
     data2 <= content2[addr]
 end
+
+
+
+system :test_rom do
+    [2..0].inner :addr
+    [7..0].inner :data0,:data1,:data2
+
+    rom4_8(:my_rom).(addr,data0,data1,data2)
+
+    timed do
+        8.times do |i|
+            addr <= i
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/seqpar_bench.rb

@@ -0,0 +1,59 @@
+# require "../hruby_low2c.rb"
+
+
+
+# A system for testing the execution of par block in seq block.
+system :seqpar_bench do
+
+    inner :rst, :clk
+    signed[8].inner :a, :b, :c, :d
+    signed[8].inner :out
+
+    seq(clk.posedge) do
+        hif(rst) do
+            a <= 0
+            b <= 0
+            c <= 0
+            d <= 0
+        end
+        helse do
+            a <= a + 1
+            b <= a + 2
+            par do
+                c <= b + 3
+                d <= c + 4
+            end
+            a <= d + 5
+        end
+    end
+
+    out <= a
+
+    timed do
+        clk <= 0
+        rst <= 0
+        !20.ns
+        clk <= 1
+        !20.ns
+        clk <= 0
+        rst <= 1
+        !20.ns
+        clk <= 1
+        !20.ns
+        clk <= 0
+        rst <= 0
+        !20.ns
+        clk <= 1
+        !20.ns
+        clk <= 0
+        !20.ns
+        clk <= 1
+        !20.ns
+        clk <= 0
+        !20.ns
+        clk <= 1
+        !20.ns
+        clk <= 0
+        !20.ns
+    end
+end