HDLRuby 2.4.21 → 2.4.28

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Files changed (14) hide show
  1. checksums.yaml +4 -4
  2. data/lib/HDLRuby/hdr_samples/rom.rb +4 -2
  3. data/lib/HDLRuby/hdr_samples/seqpar_bench.rb +59 -0
  4. data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +1 -0
  5. data/lib/HDLRuby/hdrcc.rb +4 -0
  6. data/lib/HDLRuby/hruby_low.rb +11 -1
  7. data/lib/HDLRuby/hruby_low_casts_without_expression.rb +326 -0
  8. data/lib/HDLRuby/hruby_low_without_parinseq.rb +151 -0
  9. data/lib/HDLRuby/hruby_verilog.rb +308 -133
  10. data/lib/HDLRuby/std/channel.rb +59 -18
  11. data/lib/HDLRuby/std/linear.rb +0 -5
  12. data/lib/HDLRuby/std/memory.rb +68 -17
  13. data/lib/HDLRuby/version.rb +1 -1
  14. metadata +5 -2
data/lib/HDLRuby/std/channel.rb CHANGED
@@ -778,15 +778,30 @@ module HDLRuby::High::Std
778
778
  # Port in same system as the channel case.
779
779
  # Add them to the current system.
780
780
  HDLRuby::High.cur_system.open do
781
- locs.each do |name,sig|
782
- port_pairs << [sig, sig.type.inner(name)]
781
+ # locs.each do |name,sig|
782
+ # port_pairs << [sig, sig.type.inner(name)]
783
+ # end
784
+ loc_inputs.each do |name,sig|
785
+ port_pairs << [sig, sig.type.inner(name),:input]
786
+ end
787
+ loc_outputs.each do |name,sig|
788
+ port_pairs << [sig, sig.type.inner(name),:output]
789
+ end
790
+ loc_inouts.each do |name,sig|
791
+ port_pairs << [sig, sig.type.inner(name),:inout]
783
792
  end
784
793
  end
785
794
  obj = self
786
795
  # Make the inner connection
787
- port_pairs.each do |sig, port|
796
+ # port_pairs.each do |sig, port|
797
+ port_pairs.each do |sig, port, dir|
788
798
  sig.parent.open do
789
- port.to_ref <= sig
799
+ # port.to_ref <= sig
800
+ if dir == :input then
801
+ port.to_ref <= sig
802
+ else
803
+ sig <= port.to_ref
804
+ end
790
805
  end
791
806
  end
792
807
  else
@@ -796,23 +811,28 @@ module HDLRuby::High::Std
796
811
  # The inputs
797
812
  loc_inputs.each do |name,sig|
798
813
  # puts "name=#{name} sig.name=#{sig.name}"
799
- port_pairs << [sig, sig.type.input(name)]
814
+ port_pairs << [sig, sig.type.input(name),:input]
800
815
  end
801
816
  # The outputs
802
817
  loc_outputs.each do |name,sig|
803
- port_pairs << [sig, sig.type.output(name)]
818
+ port_pairs << [sig, sig.type.output(name),:output]
804
819
  end
805
820
  # The inouts
806
821
  loc_inouts.each do |name,sig|
807
- port_pairs << [sig, sig.type.inout(name)]
822
+ port_pairs << [sig, sig.type.inout(name),:inout]
808
823
  end
809
824
  end
810
825
  obj = self
811
826
  # Make the connection of the instance.
812
827
  HDLRuby::High.cur_system.on_instance do |inst|
813
828
  obj.scope.open do
814
- port_pairs.each do |sig, port|
815
- RefObject.new(inst,port.to_ref) <= sig
829
+ port_pairs.each do |sig, port, dir|
830
+ # RefObject.new(inst,port.to_ref) <= sig
831
+ if dir == :input then
832
+ RefObject.new(inst,port.to_ref) <= sig
833
+ else
834
+ sig <= RefObject.new(inst,port.to_ref)
835
+ end
816
836
  end
817
837
  end
818
838
  end
@@ -870,15 +890,30 @@ module HDLRuby::High::Std
870
890
  # Port in same system as the channel case.
871
891
  # Add them to the current system.
872
892
  HDLRuby::High.cur_system.open do
873
- locs.each do |name,sig|
874
- port_pairs << [sig, sig.type.inner(name)]
893
+ # locs.each do |name,sig|
894
+ # port_pairs << [sig, sig.type.inner(name)]
895
+ # end
896
+ loc_inputs.each do |name,sig|
897
+ port_pairs << [sig, sig.type.inner(name),:input]
898
+ end
899
+ loc_outputs.each do |name,sig|
900
+ port_pairs << [sig, sig.type.inner(name),:output]
901
+ end
902
+ loc_inouts.each do |name,sig|
903
+ port_pairs << [sig, sig.type.inner(name),:inout]
875
904
  end
876
905
  end
877
906
  obj = self
878
907
  # Make the inner connection
879
- port_pairs.each do |sig, port|
908
+ # port_pairs.each do |sig, port|
909
+ port_pairs.each do |sig, port, dir|
880
910
  sig.parent.open do
881
- port.to_ref <= sig
911
+ # port.to_ref <= sig
912
+ if dir == :input then
913
+ port.to_ref <= sig
914
+ else
915
+ sig <= port.to_ref
916
+ end
882
917
  end
883
918
  end
884
919
  else
@@ -887,23 +922,29 @@ module HDLRuby::High::Std
887
922
  HDLRuby::High.cur_system.open do
888
923
  # The inputs
889
924
  loc_inputs.each do |name,sig|
890
- port_pairs << [sig, sig.type.input(name)]
925
+ port_pairs << [sig, sig.type.input(name),:input]
891
926
  end
892
927
  # The outputs
893
928
  loc_outputs.each do |name,sig|
894
- port_pairs << [sig, sig.type.output(name)]
929
+ port_pairs << [sig, sig.type.output(name),:output]
895
930
  end
896
931
  # The inouts
897
932
  loc_inouts.each do |name,sig|
898
- port_pairs << [sig, sig.type.inout(name)]
933
+ port_pairs << [sig, sig.type.inout(name),:inout]
899
934
  end
900
935
  end
901
936
  obj = self
902
937
  # Make the connection of the instance.
903
938
  HDLRuby::High.cur_system.on_instance do |inst|
904
939
  obj.scope.open do
905
- port_pairs.each do |sig, port|
906
- RefObject.new(inst,port.to_ref) <= sig
940
+ port_pairs.each do |sig, port, dir|
941
+ # RefObject.new(inst,port.to_ref) <= sig
942
+ # RefObject.new(inst,port.to_ref) <= sig
943
+ if dir == :input then
944
+ RefObject.new(inst,port.to_ref) <= sig
945
+ else
946
+ sig <= RefObject.new(inst,port.to_ref)
947
+ end
907
948
  end
908
949
  end
909
950
  end
data/lib/HDLRuby/std/linear.rb CHANGED
@@ -229,7 +229,6 @@ module HDLRuby::High::Std
229
229
  hif(~rvok) { right.read(rv) { rvok <= 1 } }
230
230
  lefts.each_with_index do |left,i|
231
231
  hif(~lvoks[i]) { left.read(lvs[i]) { lvoks[i] <= 1 } }
232
- # accs[i].read(avs[i])
233
232
  hif(lvoks[i] & rvok & ~woks[i]) do
234
233
  ack <= 1
235
234
  run <= 0
@@ -237,10 +236,6 @@ module HDLRuby::High::Std
237
236
  avs[i] <= add.(avs[i],mul.(lvs[i],rv))
238
237
  accs[i].write(avs[i]) do
239
238
  woks[i] <= 1
240
- # seq do
241
- # lvoks[i] <= 0
242
- # rvok <= lvoks.reduce(:|)
243
- # end
244
239
  end
245
240
  end
246
241
  end
data/lib/HDLRuby/std/memory.rb CHANGED
@@ -326,7 +326,8 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
326
326
  helse do
327
327
  # Prepare the read.
328
328
  # abus_r <= abus_r + 1
329
- if 2**size.width != size then
329
+ # if 2**size.width != size then
330
+ if 2**awidth != size then
330
331
  abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
331
332
  else
332
333
  abus_r <= abus_r + 1
@@ -392,7 +393,8 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
392
393
  helse do
393
394
  # Prepare the read.
394
395
  # abus_r <= abus_r - 1
395
- if 2**size.width != size then
396
+ # if 2**size.width != size then
397
+ if 2**awidth != size then
396
398
  abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
397
399
  else
398
400
  abus_r <= abus_r - 1
@@ -609,7 +611,8 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
609
611
  helse do
610
612
  # Prepare the read.
611
613
  # abus_r <= abus_r + 1
612
- if 2**size.width != size then
614
+ # if 2**size.width != size then
615
+ if 2**awidth != size then
613
616
  abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
614
617
  else
615
618
  abus_r <= abus_r + 1
@@ -651,7 +654,8 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
651
654
  blk.call if blk
652
655
  # Prepare the write.
653
656
  # abus_w <= abus_w + 1
654
- if 2**size.width != size then
657
+ # if 2**size.width != size then
658
+ if 2**awidth != size then
655
659
  abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
656
660
  else
657
661
  abus_w <= abus_w + 1
@@ -718,7 +722,8 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
718
722
  helse do
719
723
  # Prepare the read.
720
724
  # abus_r <= abus_r - 1
721
- if 2**size.width != size then
725
+ # if 2**size.width != size then
726
+ if 2**awidth != size then
722
727
  abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
723
728
  else
724
729
  abus_r <= abus_r - 1
@@ -760,7 +765,8 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
760
765
  blk.call if blk
761
766
  # Prepare the write.
762
767
  # abus_w <= abus_w - 1
763
- if 2**size.width != size then
768
+ # if 2**size.width != size then
769
+ if 2**awidth != size then
764
770
  abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
765
771
  else
766
772
  abus_w <= abus_w - 1
@@ -841,9 +847,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
841
847
 
842
848
  # Defines the ports of the memory as branchs of the channel.
843
849
 
844
- # The number branch (accesser).
850
+ # # The number branch (accesser).
851
+ # The number branch (reader/writer).
845
852
  brancher(:anum) do
846
- size.times { |i| accesser_inout :"reg_#{i}" }
853
+ # size.times { |i| accesser_inout :"reg_#{i}" }
854
+ size.times { |i| reader_input :"reg_#{i}" }
855
+ size.times { |i| writer_output :"reg_#{i}" }
847
856
 
848
857
  # Defines the read procedure of register number +num+
849
858
  # using +target+ as target of access result.
@@ -886,6 +895,39 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
886
895
 
887
896
  end
888
897
 
898
+ # The number read branch (reader).
899
+ brancher(:rnum) do
900
+ size.times { |i| reader_input :"reg_#{i}" }
901
+
902
+ # Defines the read procedure of register number +num+
903
+ # using +target+ as target of access result.
904
+ reader do |blk,num,target|
905
+ regs = size.times.map {|i| send(:"reg_#{i}") }
906
+ # The read procedure.
907
+ par do
908
+ # No reset, so can perform the read.
909
+ target <= regs[num]
910
+ blk.call if blk
911
+ end
912
+ end
913
+ end
914
+
915
+ # The number write branch (writer).
916
+ brancher(:wnum) do
917
+ size.times { |i| writer_output :"reg_#{i}" }
918
+
919
+ # Defines the read procedure of register number +num+
920
+ # using +target+ as target of access result.
921
+ writer do |blk,num,target|
922
+ regs = size.times.map {|i| send(:"reg_#{i}") }
923
+ # The write procedure.
924
+ par do
925
+ regs[num] <= target
926
+ blk.call if blk
927
+ end
928
+ end
929
+ end
930
+
889
931
 
890
932
  # The address branches.
891
933
  # Read with address
@@ -961,7 +1003,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
961
1003
  awidth = (size-1).width
962
1004
  awidth = 1 if awidth == 0
963
1005
  [awidth].inner :abus_r
964
- reader_inout :abus_r
1006
+ # reader_inout :abus_r
1007
+ reader_output :abus_r
965
1008
 
966
1009
  # Defines the read procedure at address +addr+
967
1010
  # using +target+ as target of access result.
@@ -984,7 +1027,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
984
1027
  blk.call if blk
985
1028
  # Prepare the next read.
986
1029
  # abus_r <= abus_r + 1
987
- if 2**size.width != size then
1030
+ # if 2**size.width != size then
1031
+ if 2**awidth != size then
988
1032
  abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
989
1033
  else
990
1034
  abus_r <= abus_r + 1
@@ -1030,7 +1074,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
1030
1074
  blk.call if blk
1031
1075
  # Prepare the next write.
1032
1076
  # abus_w <= abus_w + 1
1033
- if 2**size.width != size then
1077
+ # if 2**size.width != size then
1078
+ if 2**awidth != size then
1034
1079
  abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
1035
1080
  else
1036
1081
  abus_w <= abus_w + 1
@@ -1078,7 +1123,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
1078
1123
  blk.call if blk
1079
1124
  # Prepare the next read.
1080
1125
  # abus_r <= abus_r - 1
1081
- if 2**size.width != size then
1126
+ # if 2**size.width != size then
1127
+ if 2**awidth != size then
1082
1128
  abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
1083
1129
  else
1084
1130
  abus_r <= abus_r - 1
@@ -1124,7 +1170,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
1124
1170
  blk.call if blk
1125
1171
  # Prepare the next write.
1126
1172
  # abus_w <= abus_w - 1
1127
- if 2**size.width != size then
1173
+ # if 2**size.width != size then
1174
+ if 2**awidth != size then
1128
1175
  abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
1129
1176
  else
1130
1177
  abus_w <= abus_w - 1
@@ -1340,7 +1387,8 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
1340
1387
  end
1341
1388
  # Prepare the read.
1342
1389
  # abus_r <= abus_r + 1
1343
- if 2**size.width != size then
1390
+ # if 2**size.width != size then
1391
+ if 2**awidth != size then
1344
1392
  abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
1345
1393
  else
1346
1394
  abus_r <= abus_r + 1
@@ -1381,7 +1429,8 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
1381
1429
  blk.call if blk
1382
1430
  # Prepare the write.
1383
1431
  # abus_w <= abus_w + 1
1384
- if 2**size.width != size then
1432
+ # if 2**size.width != size then
1433
+ if 2**awidth != size then
1385
1434
  abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
1386
1435
  else
1387
1436
  abus_w <= abus_w + 1
@@ -1427,7 +1476,8 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
1427
1476
  end
1428
1477
  # Prepare the read.
1429
1478
  # abus_r <= abus_r - 1
1430
- if 2**size.width != size then
1479
+ # if 2**size.width != size then
1480
+ if 2**awidth != size then
1431
1481
  abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
1432
1482
  else
1433
1483
  abus_r <= abus_r - 1
@@ -1468,7 +1518,8 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
1468
1518
  blk.call if blk
1469
1519
  # Prepare the write.
1470
1520
  abus_w <= abus_w - 1
1471
- if 2**size.width != size then
1521
+ # if 2**size.width != size then
1522
+ if 2**awidth != size then
1472
1523
  abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
1473
1524
  else
1474
1525
  abus_w <= abus_w - 1
data/lib/HDLRuby/version.rb CHANGED
@@ -1,3 +1,3 @@
1
1
  module HDLRuby
2
- VERSION = "2.4.21"
2
+ VERSION = "2.4.28"
3
3
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: HDLRuby
3
3
  version: !ruby/object:Gem::Version
4
- version: 2.4.21
4
+ version: 2.4.28
5
5
  platform: ruby
6
6
  authors:
7
7
  - Lovic Gauthier
8
8
  autorequire:
9
9
  bindir: exe
10
10
  cert_chain: []
11
- date: 2020-12-10 00:00:00.000000000 Z
11
+ date: 2021-01-10 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: bundler
@@ -116,6 +116,7 @@ files:
116
116
  - lib/HDLRuby/hdr_samples/register_with_code_bench.rb
117
117
  - lib/HDLRuby/hdr_samples/rom.rb
118
118
  - lib/HDLRuby/hdr_samples/ruby_fir_hw.rb
119
+ - lib/HDLRuby/hdr_samples/seqpar_bench.rb
119
120
  - lib/HDLRuby/hdr_samples/struct.rb
120
121
  - lib/HDLRuby/hdr_samples/sumprod.rb
121
122
  - lib/HDLRuby/hdr_samples/sw_encrypt_bench.rb
@@ -207,6 +208,7 @@ files:
207
208
  - lib/HDLRuby/hruby_low2sym.rb
208
209
  - lib/HDLRuby/hruby_low2vhd.rb
209
210
  - lib/HDLRuby/hruby_low_bool2select.rb
211
+ - lib/HDLRuby/hruby_low_casts_without_expression.rb
210
212
  - lib/HDLRuby/hruby_low_cleanup.rb
211
213
  - lib/HDLRuby/hruby_low_fix_types.rb
212
214
  - lib/HDLRuby/hruby_low_mutable.rb
@@ -220,6 +222,7 @@ files:
220
222
  - lib/HDLRuby/hruby_low_without_connection.rb
221
223
  - lib/HDLRuby/hruby_low_without_namespace.rb
222
224
  - lib/HDLRuby/hruby_low_without_outread.rb
225
+ - lib/HDLRuby/hruby_low_without_parinseq.rb
223
226
  - lib/HDLRuby/hruby_low_without_select.rb
224
227
  - lib/HDLRuby/hruby_serializer.rb
225
228
  - lib/HDLRuby/hruby_tools.rb