HDLRuby 2.4.21 → 2.4.28

data/lib/HDLRuby/hruby_low_without_parinseq.rb

@@ -0,0 +1,151 @@
+require 'HDLRuby'
+require 'HDLRuby/hruby_tools'
+require 'HDLRuby/hruby_low_mutable'
+
+
+module HDLRuby::Low
+
+
+##
+# Converts par blocks within seq blocks to seq blocks.
+# For matching the executing model of Verilog.
+#
+########################################################################
+    
+
+    ## Extends the SystemT class with functionality for converting par blocks
+    #  within seq blocks to seq blocks.
+    class SystemT
+
+        # Converts par blocks within seq blocks to seq blocks.
+        def par_in_seq2seq!
+            self.scope.par_in_seq2seq!
+        end
+    end
+
+    ## Extends the Scope class with functionality for breaking assingments
+    #  to concats.
+    class Scope
+        # Converts par blocks within seq blocks to seq blocks.
+        def par_in_seq2seq!
+            # Recruse on the sub scopes.
+            self.each_scope(&:par_in_seq2seq!)
+            # Recurse on the block.
+            self.each_behavior do |behavior|
+                behavior.block.par_in_seq2seq!
+            end
+        end
+    end
+
+
+    ## Extends the Statement class with functionality for breaking assingments
+    #  to concats.
+    class Statement
+        # Converts par blocks within seq blocks to seq blocks.
+        def par_in_seq2seq!
+            # By default nothing to do.
+            return self
+        end
+
+        # Convert the block to seq.
+        def to_seq!
+            # By default nothing to do.
+            return self
+        end
+    end
+
+
+    ## Extends the If class with functionality for breaking assingments
+    #  to concats.
+    class If
+        # Converts par blocks within seq blocks to seq blocks.
+        def par_in_seq2seq!
+            self.yes.par_in_seq2seq!
+            self.each_noif do |cond,blk|
+                blk.par_in_seq2seq!
+            end
+            self.no.par_in_seq2seq! if self.no
+        end
+
+        # Convert the block to seq.
+        def to_seq!
+            self.to_seq!
+            self.each_noif do |cond,blk|
+                blk.to_seq!
+            end
+            self.no.to_seq! if self.no
+        end
+    end
+
+
+    ## Extends the Case class with functionality for breaking assingments
+    #  to concats.
+    class Case
+        # Converts par blocks within seq blocks to seq blocks.
+        def par_in_seq2seq!
+            self.each_when do |w|
+                w.statement.par_in_seq2seq!
+            end
+            self.default.par_in_seq2seq! if self.default
+        end
+
+        # Convert the block to seq.
+        def to_seq!
+            self.each_when do |w|
+                w.statement.to_seq!
+            end
+            self.default.to_seq! if self.default
+        end
+    end
+
+
+    ## Extends the Block class with functionality for breaking assingments
+    #  to concats.
+    class Block
+        # Converts par blocks within seq blocks to seq blocks.
+        def par_in_seq2seq!
+            # Recurse on the sub blocks.
+            self.each_statement(&:par_in_seq2seq!)
+            # Is the current block a seq block?
+            if self.mode == :seq then
+                # Yes, convert its inner par blocks to seq blocks.
+                self.each_statement do |statement|
+                    if (statement.is_a?(Block)) then
+                        statement.to_seq! if statement.mode == :par
+                    end
+                end
+            end
+            return self
+        end
+
+        # Convert the block to seq.
+        def to_seq!
+            if self.mode == :par then
+                # Need to convert.
+                # First recurse on the sub blocks.
+                self.each_statement(&:to_seq!)
+                # Now replace each left value by a new signal for
+                # differed assingment in seq.
+                differeds = []
+                self.each_statement do |statement|
+                    left = statement.left
+                    if statement.is_a?(Transmit) then
+                        sig = SignalI.new(HDLRuby.uniq_name,left.type)
+                        self.add_inner(sig)
+                        diff = RefName.new(left.type,RefThis.new,sig.name)
+                        differeds << [left,diff]
+                        statement.set_left!(diff)
+                    end
+                end
+                # Adds the differed assignments.
+                differeds.each do |left,diff|
+                    self.add_statement(Transmit.new(left.clone,diff.clone))
+                end
+                # Change the mode.
+                self.set_mode!(:seq)
+            end
+            return self
+        end
+    end
+
+end

data/lib/HDLRuby/hruby_verilog.rb

@@ -11,6 +11,13 @@ include HDLRuby::Verilog
 module HDLRuby::Low
 
 
+    # The list of base types used both in verilog and HDLRuby
+    VERILOG_BASE_TYPES = ["signed"]
+
+    # The list of signals that are actually verilog regs.
+    VERILOG_REGS = []
+
+
 # Sample of very handy for programming.
 # puts "class=#{self.yes.class}"       # Confirm class of self.yes.
 # puts "methods=#{self.right.methods}" # Confirm method of self.right.
@@ -21,7 +28,7 @@ module HDLRuby::Low
 # end
 
 # Global variable used for indentation and structure (temporary).
-$space_count = 0   # Count used for increasing indent by if statement. (temporary)
+# $space_count = 0   # Count used for increasing indent by if statement. (temporary)
 $vector_reg = ""   # For storing signal type at structure declaration. (temporary)
 $vector_cnt = 0    # For allocating numbers at structure declaration.  (temporary)
 
@@ -97,9 +104,11 @@ end
 # Enhance Transmit with generation of verilog code.
 class Transmit
     # Converts the system to Verilog code.
-    def to_verilog(mode = nil)
+    # def to_verilog(mode = nil)
+    def to_verilog(spc = 3)
         # Determine blocking assignment or nonblocking substitution from mode and return it.
-        code = "#{self.left.to_verilog} #{mode == "seq" ? "=" : "<="} #{self.right.to_verilog};\n"
+        # code = "#{self.left.to_verilog} #{mode == "seq" ? "=" : "<="} #{self.right.to_verilog};\n"
+        code = "#{" " * spc}#{self.left.to_verilog} #{self.block.mode == :seq ? "=" : "<="} #{self.right.to_verilog};"
         return code
     end
 end
@@ -107,12 +116,68 @@ end
 # To scheduling to the Block.
 # Enhance Block with generation of verilog code.
 class Block
-    # Converts the system to Verilog code.
-    def to_verilog(mode = nil)
-        # No translation is done in this class.
-        puts "Block to_verilog not found" # For debugging
+    # # Converts the system to Verilog code.
+    # def to_verilog(mode = nil)
+    #     # No translation is done in this class.
+    #     puts "Block to_verilog not found" # For debugging
+    # end
+
+    # Converts the system to Verilog code adding 'spc' spaces at the begining
+    # of each line.
+    def to_verilog(spc = 3)
+            code = "begin"
+            code << " : #{name_to_verilog(self.name)}" if self.name && !self.name.empty?
+            code << "\n" if block.each_inner.any?
+            # Declaration of "inner" part within "always".
+            block.each_inner do |inner|
+                # if regs.include?(inner.name) then
+                if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
+                    # code << "      reg"
+                    code << "#{" " * (spc+3)}reg"
+                else
+                    code << "#{" " * (spc+3)}wire"
+                end
+
+                # Variable has "base", but if there is width etc, it is not in "base".
+                # It is determined by an if.
+                if inner.type.base? 
+                    if inner.type.base.base? 
+                        # code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
+                        code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
+                    else
+                        # code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
+                        code << "#{inner.type.to_verilog} #{inner.to_verilog}"
+                    end
+                else
+                    # code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
+                    code << " #{inner.type.to_verilog}#{inner.to_verilog}"
+                end
+                if inner.value then
+                    # There is an initial value.
+                    code << " = #{inner.value.to_verilog}"
+                end
+                code << ";\n"
+            end
+
+            # Translate the block that finished scheduling.
+            block.each_statement do |statement|
+                #code  << "\n      #{statement.to_verilog(behavior.block.mode.to_s)}"
+                # code  << "\n#{" "*spc}#{statement.to_verilog(behavior.block.mode.to_s)}"
+                if statement.is_a?(Block) then
+                    code << "\n#{" " * (spc+3)}#{statement.to_verilog(spc+3)}"
+                else
+                    code  << "\n#{statement.to_verilog(spc+3)}"
+                end
+            end
+            # Close the block."
+            code << "\n#{" "*spc}end"
+            return code
     end
 
+
+
+
+
     # Extract and convert to verilog the TimeRepeat statements.
     # NOTE: work only on the current level of the block (should be called
     # through each_block_deep).
@@ -132,7 +197,7 @@ class Block
             # Declaration of "inner" part within "always".
             block.each_inner do |inner|
                 # if regs.include?(inner.name) then
-                if regs.include?(inner.to_verilog) then
+                if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
                     code << "      reg"
                 else
                     code << "      wire"
@@ -456,7 +521,10 @@ class Block
                             $fm.fm_par["#{tmt.left.to_verilog}"] = tmt.right
                         end
                         new_block.add_statement(tmt.clone)           
-                    end         
+                    end
+                else
+                    # Other statements are simply added as is.
+                    new_block.add_statement(statement.clone)
                 end
             end
 
@@ -1349,7 +1417,8 @@ end
 class TypeVector
     # Converts the system to Verilog code.
     def to_verilog
-        if self.base.name.to_s != "bit"
+        # if self.base.name.to_s != "bit"
+        if VERILOG_BASE_TYPES.include?(self.base.name.to_s)
             return " #{self.base.name.to_s}[#{self.range.first}:#{self.range.last}]"
         end
         return " [#{self.range.first}:#{self.range.last}]"
@@ -1423,66 +1492,82 @@ class Value
     end
 end
 
+
 # Used to transrate if.
 # Enhance If with generation of verilog code.
 class If
-    # Converts the system to Verilog code.
-    def to_verilog(mode = nil)
+    # # Converts the system to Verilog code.
+    # def to_verilog(mode = nil)
+    # Converts to Verilog code, checking adding 'spc' spaces at the begining
+    # of each line.
+    def to_verilog(spc = 3)
 
         $blocking = false
 
-        if ($space_count == 0) then
-            result = "   " * ($space_count)  # Indented based on space_count.
-        else
-            result = ""
-        end
-        $space_count += 1                  # Add count to be used for indentation.
+        # if ($space_count == 0) then
+        #     result = "   " * ($space_count)  # Indented based on space_count.
+        # else
+        #     result = ""
+        # end
+        # $space_count += 1                  # Add count to be used for indentation.
+        result = " " * spc  # Indented based on space_count.
 
-        result << "if (#{self.condition.to_verilog}) begin\n"
+        # result << "if (#{self.condition.to_verilog}) begin\n"
+        result << "if (#{self.condition.to_verilog}) "
 
 
         # Check if there is yes (if) and output yes or less.
         if self.respond_to? (:yes)
-            self.yes.each_statement do |statement|
-                result << "#{"   " * $space_count}      #{statement.to_verilog(mode)}"
-            end
-            result << "#{"   " * $space_count}   end\n"
+            # self.yes.each_statement do |statement|
+            #     result << "#{"   " * $space_count}      #{statement.to_verilog(mode)}"
+            # end
+            # result << "#{"   " * $space_count}   end\n"
+            result << self.yes.to_verilog(spc)
         end
 
         # If noif (else if) exists, it outputs it.
         # Since noif is directly under, respond_to is unnecessary.
         self.each_noif do |condition, block|
-            result << "#{"   " * $space_count}   else if (#{condition.to_verilog}) begin\n"
-            block.each_statement do |statement|
-                result << "#{"   " * $space_count}      #{statement.to_verilog(mode)}"
-            end
-            result << "#{"   "* $space_count}   end\n"
+            # result << "#{"   " * $space_count}   else if (#{condition.to_verilog}) begin\n"
+            result << "\n#{" "*spc}else if (#{condition.to_verilog}) "
+            # block.each_statement do |statement|
+            #     result << "#{"   " * $space_count}      #{statement.to_verilog(mode)}"
+            # end
+            # result << "#{"   "* $space_count}   end\n"
+            result << block.to_verilog(spc)
         end
 
         # Check if there is no (else) and output no or less.
-        if self.no.respond_to? (:mode)
-            result << "#{"   " * $space_count}   else begin\n"
-            self.no.each_statement do |statement|
-                result << "#{"   " * $space_count}      #{statement.to_verilog(mode)}"
-            end
-            result << "#{"   " * $space_count}   end\n"
+        if self.no.respond_to?(:mode)
+            # result << "#{"   " * $space_count}   else begin\n"
+            result << "\n#{" " * spc}else "
+            # self.no.each_statement do |statement|
+            #     result << "#{"   " * $space_count}      #{statement.to_verilog(mode)}"
+            # end
+            # result << "#{"   " * $space_count}   end\n"
+            result << self.no.to_verilog(spc)
         end
 
-        $space_count -= 1 # Since the output ends, reduce the count.
+        # $space_count -= 1 # Since the output ends, reduce the count.
         return result
     end
 end
 
 # Used to translate case
 class Case
-    def to_verilog(mode = nil)
+    # def to_verilog(mode = nil)
+    #
+    # Converts to Verilog code, checking if variables are register
+    # or wire adding 'spc' spaces at the begining of each line.
+    def to_verilog(spc = 3)
 
-        if ($space_count == 0) then
-            result = "   " * ($space_count) # Indented based on space_count.
-        else
-            result = ""
-        end
-        $space_count += 1                 # Add count to be used for indentation.
+        # if ($space_count == 0) then
+        #     result = "   " * ($space_count) # Indented based on space_count.
+        # else
+        #     result = ""
+        # end
+        # $space_count += 1                 # Add count to be used for indentation.
+        result = " " * spc # Indented based on space_count.
 
         result = ""
         result << "case(#{self.value.to_verilog})\n"
@@ -1490,40 +1575,55 @@ class Case
         # n the case statement, each branch is partitioned by when. Process each time when.
         self.each_when do |whens| 
             # Reads and stores the numbers and expressions stored in when.
-            result << "      " + "   " *$space_count + "#{whens.match.to_verilog}: "
-            if whens.statement.each_statement.count > 1 then
-                result << "begin\n"
-                whens.statement.each_statement do |statement|
-                    result << "                  "+ "   " *$space_count +"#{statement.to_verilog}"
-                end
-                result << "             " + "   " *$space_count + "end\n"
-            elsif whens.statement.each_statement.count == 1 then
-                whens.statement.each_statement do |statement|
-                    result << "#{statement.to_verilog}"
-                end
+            # result << "      " + "   " *$space_count + "#{whens.match.to_verilog}: "
+            result << " " * (spc+3) + "#{whens.match.to_verilog}: "
+            
+            # if whens.statement.each_statement.count > 1 then
+            #     result << "begin\n"
+            #     whens.statement.each_statement do |statement|
+            #         result << "                  "+ "   " *$space_count +"#{statement.to_verilog}"
+            #     end
+            #     result << "             " + "   " *$space_count + "end\n"
+            # elsif whens.statement.each_statement.count == 1 then
+            #     whens.statement.each_statement do |statement|
+            #         result << "#{statement.to_verilog}"
+            #     end
+            # else
+            #     # Empty statement case.
+            #     result << "\n"
+            # end
+            if whens.statement.each_statement.count >= 1 then
+                result << whens.statement.to_verilog(spc+3)
             else
-                # Empty statement case.
                 result << "\n"
             end
         end
-        # The default part is stored in default instead of when. Reads and processes in the same way as when.
+        # # The default part is stored in default instead of when. Reads and processes in the same way as when.
+        # if self.default then
+        #     if self.default.each_statement.count > 1 then
+        #         result << "      " + "   " *$space_count + "default: begin\n"
+        #         self.default.each_statement do |statement|
+        #             result << "                  " + "   " *$space_count + "#{statement.to_verilog}"
+        #         end
+        #         result << "                  end\n"
+        #     elsif self.default.each_statement.count == 1 then
+        #         result << "      " + "   " *$space_count + "default: "
+        #         self.default.each_statement do |statement|
+        #             result << "#{statement.to_verilog}"
+        #         end
+        #     end  
+        # end
         if self.default then
-            if self.default.each_statement.count > 1 then
-                result << "      " + "   " *$space_count + "default: begin\n"
-                self.default.each_statement do |statement|
-                    result << "                  " + "   " *$space_count + "#{statement.to_verilog}"
-                end
-                result << "                  end\n"
-            elsif self.default.each_statement.count == 1 then
-                result << "      " + "   " *$space_count + "default: "
-                self.default.each_statement do |statement|
-                    result << "#{statement.to_verilog}"
-                end
-            end  
+            if self.default.each_statement.count >= 1 then
+                result << self.default.each_statement.to_verilog(spc+3)
+            else
+                result << "\n"
+            end
         end
-        result << "   " + "   " *$space_count + "endcase\n" # Conclusion.
+        # result << "   " + "   " *$space_count + "endcase\n" # Conclusion.
+        result << " " * spc + "endcase\n" # Conclusion.
 
-        $space_count -= 1           # Since the output ends, reduce the count.
+        # $space_count -= 1           # Since the output ends, reduce the count.
         return result               # Return case after translation.
     end
 end
@@ -1598,7 +1698,7 @@ end
 class Unary
     # Converts the system to Verilog code.
     def to_verilog
-        return "#{self.operator}#{self.child.to_verilog}"
+        return "#{self.operator[0]}#{self.child.to_verilog}"
     end
 end
 
@@ -1609,10 +1709,37 @@ class Cast
     #       by traditional verilog.
     def to_verilog
         # return "#{self.type.to_verilog}'(#{self.child.to_verilog})"
+        if self.child.is_a?(Value) then
+            return self.child.to_verilog
+        end
+        # Get the type widths, used for computing extensions or truncations.
+        cw = self.child.type.width
+        sw = self.type.width
         if self.type.signed? then
-            return "$signed(#{self.child.to_verilog})"
+            # return "$signed(#{self.child.to_verilog})"
+            if (sw>cw) then
+                # Need to sign extend.
+                return "$signed({{#{sw-cw}{#{self.child.to_verilog}[#{cw-1}]}}," +
+                  "#{self.child.to_verilog}})"
+            elsif (sw<cw) then
+                # Need to truncate
+                return "$signed(#{self.child.to_verilog}[#{sw-1}:0])"
+            else
+                # Only enforce signed.
+                return "$signed(#{self.child.to_verilog})"
+            end
         else
-            return "$unsigned(#{self.child.to_verilog})"
+            # return "$unsigned(#{self.child.to_verilog})"
+            if (sw>cw) then
+                # Need to extend.
+                return "$unsigned({{#{sw-cw}{1'b0}},#{self.child.to_verilog}})"
+            elsif (sw<cw) then
+                # Need to truncate
+                return "$unsigned(#{self.child.to_verilog}[#{sw-1}:0])"
+            else
+                # Only enforce signed.
+                return "$unsigned(#{self.child.to_verilog})"
+            end
         end
     end
 end
@@ -1662,23 +1789,24 @@ end
 # Look at the unit of time, convert the time to ps and output it.
 # One of two people, TimeWait and Delay.
 class TimeWait
-    def to_verilog(mode=nil)
-        return self.delay.to_verilog + "\n"
+    # def to_verilog(mode=nil)
+    def to_verilog(spc = 3)
+        return (" " * spc) + self.delay.to_verilog + "\n"
     end
 end
 class Delay
     def to_verilog
         time = self.value.to_s
         if(self.unit.to_s == "ps") then
-            return "##{time}"
+            return "##{time};"
         elsif(self.unit.to_s == "ns")
-            return "##{time}000"
+            return "##{time}000;"
         elsif(self.unit.to_s == "us")
-            return "##{time}000000"
+            return "##{time}000000;"
         elsif(self.unit.to_s == "ms")
-            return "##{time}000000000"
+            return "##{time}000000000;"
         elsif(self.unit.to_s == "s")
-            return "##{time}000000000000"
+            return "##{time}000000000000;"
         end
     end
 end
@@ -1690,6 +1818,20 @@ end
 
 # Enhance SystemT with generation of verilog code.
 class SystemT
+    
+    ## Tells if a connection is actually a port connection.
+    def port_output_connection?(connection)
+        return self.each_systemI.find do |systemI|
+            if connection.right.is_a?(RefName) && 
+            connection.right.ref.is_a?(RefName) &&
+            systemI.name == connection.right.ref.name
+                puts "port_connection for right=#{connection.right.name} and systemI=#{systemI.name}"
+                true
+            else
+                false
+            end
+        end
+    end
 
     ## Tells if an expression is a reference to port +systemI.signal+.
     def port_assign?(expr, systemI, signal)
@@ -1727,9 +1869,9 @@ class SystemT
 
     # Converts the system to Verilog code.
     def to_verilog
-        # Preprocessing
         # Detect the registers
-        regs = []
+        # regs = []
+        HDLRuby::Low::VERILOG_REGS.clear
         # The left values.
         self.each_behavior do |behavior|
             # behavior.block.each_statement do |statement|
@@ -1737,23 +1879,46 @@ class SystemT
             # end
             behavior.each_block_deep do |block|
                 block.each_statement do |statement|
-                    regs << statement.left.to_verilog if statement.is_a?(Transmit)
+                    if statement.is_a?(Transmit)
+                        HDLRuby::Low::VERILOG_REGS << statement.left.to_verilog
+                    end
                 end
             end
         end
+        # # puts "regs has clk?: #{regs.include?("clk")}"
+        # # puts "for system #{self.name}"
+        # # Remove the left values of connection, they do not count.
+        # self.scope.each_connection do |connection|
+        #     # Skip port connections.
+        #     next if !self.port_output_connection?(connection) 
+        #     # puts "Not counting left in connection: #{connection.to_verilog}"
+        #     # puts "i.e.: #{connection.left.to_verilog}"
+        #     regs.delete(connection.left.to_verilog)
+        # end
+        # # puts "Now regs has clk?: #{regs.include?("clk")}"
         # And the initialized signals.
         self.each_output do |output|
-            regs << output.to_verilog if output.value
+            # regs << output.to_verilog if output.value
+            HDLRuby::Low::VERILOG_REGS << output.to_verilog if output.value
         end
         self.each_inner do |inner|
-            regs << inner.to_verilog if inner.value
+            # regs << inner.to_verilog if inner.value
+            HDLRuby::Low::VERILOG_REGS << inner.to_verilog if inner.value
         end
         # And the array types signals.
         self.each_signal do |sig|
-            regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            # # regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            # regs << sig.to_verilog if sig.type.vector? && sig.type.base.vector?
+            if sig.type.vector? && sig.type.base.vector? then
+                HDLRuby::Low::VERILOG_REGS << sig.to_verilog
+            end
         end
         self.each_inner do |sig|
-            regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            # # regs << sig.to_verilog if sig.type.is_a?(TypeVector) && sig.type.base.is_a?(TypeVector)
+            # regs << sig.to_verilog if sig.type.vector? && sig.type.base.vector?
+            if sig.type.vector? && sig.type.base.vector? then
+                HDLRuby::Low::VERILOG_REGS << sig.to_verilog
+            end
         end
 
         # Code generation
@@ -1822,7 +1987,8 @@ class SystemT
                 $vector_reg = "#{output.to_verilog}"
                 $vector_cnt = 0
                 output.type.each_type do |type|
-                    if regs.include?(type.name) then
+                    # if regs.include?(type.name) then
+                    if HDLRuby::Low::VERILOG_REGS.include?(type.name) then
                         code << "   output reg"
                     else
                         code << "   output"
@@ -1838,7 +2004,8 @@ class SystemT
                 end        
             else
                 # if regs.include?(output.name) then
-                if regs.include?(output.to_verilog) then
+                # if regs.include?(output.to_verilog) then
+                if HDLRuby::Low::VERILOG_REGS.include?(output.to_verilog) then
                     code << "   output reg"
                 else
                     code << "   output"
@@ -1869,8 +2036,9 @@ class SystemT
 
         # Declare "inner".
         self.each_inner do |inner|
-            # if regs.include?(inner.name) then
-            if regs.include?(inner.to_verilog) then
+            # # if regs.include?(inner.name) then
+            # if regs.include?(inner.to_verilog) then
+            if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
                 code << "   reg"
             else
                 code << "   wire"
@@ -1898,8 +2066,9 @@ class SystemT
         # If there is scope in scope, translate it.
         self.each_scope do |scope|
             scope.each_inner do |inner|
-                # if regs.include?(inner.name) then
-                if regs.include?(inner.to_verilog) then
+                # # if regs.include?(inner.name) then
+                # if regs.include?(inner.to_verilog) then
+                if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
                     code << "   reg "
                 else
                     code << "   wire "
@@ -1932,9 +2101,11 @@ class SystemT
 
         code << "\n"
 
+        # puts "For system=#{self.name}"
         # transliation of the instantiation part.
         # Generate the instances connections.
         self.each_systemI do |systemI| 
+            # puts "Processing systemI = #{systemI.name}"
             # Its Declaration.
             code << " " * 3
             systemT = systemI.systemT
@@ -1988,7 +2159,8 @@ class SystemT
                     code << blk.repeat_to_verilog!
                 end
                 # And generate an initial block.
-                code << "   initial begin\n"
+                # code << "   initial begin\n"
+                code << "   initial "
             else
                 # Generate a standard process.
                 code << "   always @( "
@@ -2013,54 +2185,57 @@ class SystemT
                         code << "#{event.last.type.to_s} #{event.last.ref.to_verilog}"
                     end
                 end
-                code << " ) begin\n"
+                # code << " ) begin\n"
+                code << " ) "
             end
 
-            # Perform "scheduling" using the method "flatten".
-            block = behavior.block.flatten(behavior.block.mode.to_s)
-
-            # Declaration of "inner" part within "always".
-            block.each_inner do |inner|
-                # if regs.include?(inner.name) then
-                if regs.include?(inner.to_verilog) then
-                    code << "      reg"
-                else
-                    code << "      wire"
-                end
-
-                # Variable has "base", but if there is width etc, it is not in "base".
-                # It is determined by an if.
-                if inner.type.base? 
-                    if inner.type.base.base? 
-                        # code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
-                        code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
-                    else
-                        # code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
-                        code << "#{inner.type.to_verilog} #{inner.to_verilog}"
-                    end
-                else
-                    # code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
-                    code << " #{inner.type.to_verilog}#{inner.to_verilog}"
-                end
-                if inner.value then
-                    # There is an initial value.
-                    code << " = #{inner.value.to_verilog}"
-                end
-                code << ";\n"
-            end
+            # # Perform "scheduling" using the method "flatten".
+            # block = behavior.block.flatten(behavior.block.mode.to_s)
+            # code << block.to_verilog(regs)
+            code << behavior.block.to_verilog
+
+            # # Declaration of "inner" part within "always".
+            # block.each_inner do |inner|
+            #     # if regs.include?(inner.name) then
+            #     if regs.include?(inner.to_verilog) then
+            #         code << "      reg"
+            #     else
+            #         code << "      wire"
+            #     end
+
+            #     # Variable has "base", but if there is width etc, it is not in "base".
+            #     # It is determined by an if.
+            #     if inner.type.base? 
+            #         if inner.type.base.base? 
+            #             # code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog};\n"
+            #             code << "#{inner.type.base.to_verilog} #{inner.to_verilog} #{inner.type.to_verilog}"
+            #         else
+            #             # code << "#{inner.type.to_verilog} #{inner.to_verilog};\n"
+            #             code << "#{inner.type.to_verilog} #{inner.to_verilog}"
+            #         end
+            #     else
+            #         # code << " #{inner.type.to_verilog}#{inner.to_verilog};\n"
+            #         code << " #{inner.type.to_verilog}#{inner.to_verilog}"
+            #     end
+            #     if inner.value then
+            #         # There is an initial value.
+            #         code << " = #{inner.value.to_verilog}"
+            #     end
+            #     code << ";\n"
+            # end
 
-            # Translate the block that finished scheduling.
-            block.each_statement do |statement|
-                code  << "\n      #{statement.to_verilog(behavior.block.mode.to_s)}"
-            end
+            # # Translate the block that finished scheduling.
+            # block.each_statement do |statement|
+            #     code  << "\n      #{statement.to_verilog(behavior.block.mode.to_s)}"
+            # end
 
-            $fm.fm_par.clear()
+            # $fm.fm_par.clear()
 
-            code << "\n   end\n\n"
+            # code << "\n   end\n\n"
         end
 
         # Conclusion.
-        code << "endmodule"
+        code << "\nendmodule"
         return code
     end
 end