HDLRuby 2.4.18 → 2.4.19
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- checksums.yaml +4 -4
- data/lib/HDLRuby/hdr_samples/with_connector_memory.rb +98 -0
- data/lib/HDLRuby/std/connector.rb +4 -2
- data/lib/HDLRuby/version.rb +1 -1
- metadata +3 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 98f251acca7748335f7f60586eddb75a2b8efb9773225d3776bdb585b6d05060
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data.tar.gz: 689f2d3b0c2332e2877c3dcfd273b43c3b7deb44853f21aeffdd2e60d7e1d74c
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 3732704b0a83a69ccf1796772c25d70a453adf5b0d4d795d2c9741fdb2e6e9ba5b086348983012a6ff68415de2327e22e7a7eed6bdff647da98e37406410869a
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data.tar.gz: b01e94018fb612dfae8cbce2076a19829fe44f9301a5f4969d153323981b889c8b9d434ffc4b6f91e27830c312ef1108decc28c275be7a65997d74123488480d
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@@ -0,0 +1,98 @@
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require 'std/memory.rb'
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require "std/fixpoint.rb"
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require 'std/channel.rb'
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require 'std/connector.rb'
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include HDLRuby::High::Std
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system :channel_connector do
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# データ型の宣言
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integer_width = 4 # 整数部のビット幅
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decimal_width = 4 # 実数部のビット幅
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address_width = 4 # lutのアドレスのビット幅
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typ = signed[integer_width + decimal_width] # データ型
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inputs_x = _00010011
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inputs_h = _10100001
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columns = [2, 2, 1]
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inner :clk, # clock
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:rst, # reset
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:req, # request
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:fill # 入力値のメモリへの書き込み
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# inputs_x = quantize(inputs_x, typ, decimal_width)
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# inputs_h = quantize(inputs_h, typ, decimal_width)
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mem_rom(typ, columns[0], clk, rst, inputs_x, rinc: :rst, winc: :rst).(:rom_inputs_x) # 入力値を格納するrom(x)
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mem_rom(typ, columns[0], clk, rst, inputs_h, rinc: :rst, winc: :rst).(:rom_inputs_h) # 入力値を格納するrom(h)
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mem_dual(typ, columns[0], clk, rst, rinc: :rst, winc: :rst).(:ram_inputs_serializer) #
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mem_dual(typ, columns[0]*2, clk, rst, rinc: :rst, winc: :rst).(:ram_inputs_merger) #
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reader_inputs_x = rom_inputs_x.branch(:rinc) #入力値xの読みだし用branch
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reader_inputs_h = rom_inputs_h.branch(:rinc) #入力値hの読みだし用branch
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writer_inputs_serializer = ram_inputs_serializer.branch(:winc) #入力値を合成した値の書き込み用branch
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writer_inputs_meger = ram_inputs_merger.branch(:winc) #入力値を合成した値の書き込み用branch
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serializer(typ,clk.negedge,[reader_inputs_x,reader_inputs_h],writer_inputs_serializer)
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# merger([typ]*2,clk.negedge,[reader_inputs_x,reader_inputs_h], writer_inputs_meger)
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# duplicator(typ,clk.negedge,reader_inputs_r,[])
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timed do
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# リセット
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clk <= 0
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rst <= 0
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req <= 0
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fill <= 0
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!10.ps
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# メモリ読み出し位置の初期化
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rst <= 1
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!10.ps
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clk <= 1
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!10.ps
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clk <= 0
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!10.ps
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clk <= 1
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!10.ps
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# パラメータのメモリへの書き込み
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clk <= 0
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rst <= 0
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fill <= 1
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!10.ps
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10.times do |i|
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clk <= 1
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!10.ps
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clk <= 0
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!10.ps
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end
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fill <= 0
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clk <= 1
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!10.ps
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# 計算の実行
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clk <= 0
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req <= 1
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!10.ps
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clk <= 1
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!10.ps
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clk <= 0
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!10.ps
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30.times do
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clk <= 1
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!10.ps
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clk <= 0
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!10.ps
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end
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end
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end
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@@ -82,7 +82,7 @@ module HDLRuby::High::Std
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idx <= 0
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reading <= 0
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out_ack <= 0
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-
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hif(idx == size-1) { in_acks.each { |ack| ack <= 0 } }
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# hif((idx == 0) & (in_reqs.reduce(_1) { |sum,req| req & sum })) do
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hif(idx == 0) do
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hif(~reading) do
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@@ -90,7 +90,9 @@ module HDLRuby::High::Std
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end
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reading <= 1
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in_chs.each_with_index do |ch,i|
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hif(~in_acks[i]) do
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ch.read(datas[i]) { in_acks[i] <= 1 }
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end
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end
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end
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hif(in_acks.reduce(_1) { |sum,req| req & sum }) do
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data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
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--- !ruby/object:Gem::Specification
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name: HDLRuby
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version: !ruby/object:Gem::Version
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-
version: 2.4.
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version: 2.4.19
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platform: ruby
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authors:
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- Lovic Gauthier
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autorequire:
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bindir: exe
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cert_chain: []
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-
date: 2020-12-
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date: 2020-12-06 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: bundler
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@@ -126,6 +126,7 @@ files:
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- lib/HDLRuby/hdr_samples/with_channel.rb
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- lib/HDLRuby/hdr_samples/with_class.rb
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- lib/HDLRuby/hdr_samples/with_connector.rb
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- lib/HDLRuby/hdr_samples/with_connector_memory.rb
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- lib/HDLRuby/hdr_samples/with_decoder.rb
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- lib/HDLRuby/hdr_samples/with_fixpoint.rb
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- lib/HDLRuby/hdr_samples/with_fsm.rb
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