HDLRuby 2.4.18 → 2.4.19

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
checksums.yaml CHANGED
@@ -1,7 +1,7 @@
1
1
  ---
2
2
  SHA256:
3
- metadata.gz: 84f01afb241f5e5e208e4fc47e12e9f1ae8e63e759181280500c2a591999c28d
4
- data.tar.gz: 4ae5e9c2eecc25f26803da8c4b70e0bcfa57e7979759d9a194bb6effd515788d
3
+ metadata.gz: 98f251acca7748335f7f60586eddb75a2b8efb9773225d3776bdb585b6d05060
4
+ data.tar.gz: 689f2d3b0c2332e2877c3dcfd273b43c3b7deb44853f21aeffdd2e60d7e1d74c
5
5
  SHA512:
6
- metadata.gz: f721bbbbbddd9328444b446a882623428e638cdacc3d09c41a86b7c7e260e662e43df7747f91c7eeb3e498b335495722268869f151cff64aaf0d953385285d6b
7
- data.tar.gz: 48e48595def6334b972eec991ae83a44876e30994101dd336a7036608c7da47799eafa7fdfb955e11d6f12f7b9728cafdea5fde1d933d6d3c165ef1ba1cdd375
6
+ metadata.gz: 3732704b0a83a69ccf1796772c25d70a453adf5b0d4d795d2c9741fdb2e6e9ba5b086348983012a6ff68415de2327e22e7a7eed6bdff647da98e37406410869a
7
+ data.tar.gz: b01e94018fb612dfae8cbce2076a19829fe44f9301a5f4969d153323981b889c8b9d434ffc4b6f91e27830c312ef1108decc28c275be7a65997d74123488480d
@@ -0,0 +1,98 @@
1
+ require 'std/memory.rb'
2
+ require "std/fixpoint.rb"
3
+ require 'std/channel.rb'
4
+ require 'std/connector.rb'
5
+
6
+ include HDLRuby::High::Std
7
+
8
+ system :channel_connector do
9
+ # データ型の宣言
10
+ integer_width = 4 # 整数部のビット幅
11
+ decimal_width = 4 # 実数部のビット幅
12
+ address_width = 4 # lutのアドレスのビット幅
13
+ typ = signed[integer_width + decimal_width] # データ型
14
+
15
+ inputs_x = _00010011
16
+ inputs_h = _10100001
17
+ columns = [2, 2, 1]
18
+
19
+ inner :clk, # clock
20
+ :rst, # reset
21
+ :req, # request
22
+ :fill # 入力値のメモリへの書き込み
23
+
24
+ # inputs_x = quantize(inputs_x, typ, decimal_width)
25
+ # inputs_h = quantize(inputs_h, typ, decimal_width)
26
+
27
+ mem_rom(typ, columns[0], clk, rst, inputs_x, rinc: :rst, winc: :rst).(:rom_inputs_x) # 入力値を格納するrom(x)
28
+
29
+ mem_rom(typ, columns[0], clk, rst, inputs_h, rinc: :rst, winc: :rst).(:rom_inputs_h) # 入力値を格納するrom(h)
30
+
31
+ mem_dual(typ, columns[0], clk, rst, rinc: :rst, winc: :rst).(:ram_inputs_serializer) #
32
+
33
+ mem_dual(typ, columns[0]*2, clk, rst, rinc: :rst, winc: :rst).(:ram_inputs_merger) #
34
+
35
+ reader_inputs_x = rom_inputs_x.branch(:rinc) #入力値xの読みだし用branch
36
+ reader_inputs_h = rom_inputs_h.branch(:rinc) #入力値hの読みだし用branch
37
+ writer_inputs_serializer = ram_inputs_serializer.branch(:winc) #入力値を合成した値の書き込み用branch
38
+ writer_inputs_meger = ram_inputs_merger.branch(:winc) #入力値を合成した値の書き込み用branch
39
+
40
+
41
+ serializer(typ,clk.negedge,[reader_inputs_x,reader_inputs_h],writer_inputs_serializer)
42
+
43
+ # merger([typ]*2,clk.negedge,[reader_inputs_x,reader_inputs_h], writer_inputs_meger)
44
+
45
+ # duplicator(typ,clk.negedge,reader_inputs_r,[])
46
+
47
+
48
+ timed do
49
+ # リセット
50
+ clk <= 0
51
+ rst <= 0
52
+ req <= 0
53
+ fill <= 0
54
+ !10.ps
55
+
56
+ # メモリ読み出し位置の初期化
57
+ rst <= 1
58
+ !10.ps
59
+ clk <= 1
60
+ !10.ps
61
+ clk <= 0
62
+ !10.ps
63
+ clk <= 1
64
+ !10.ps
65
+
66
+ # パラメータのメモリへの書き込み
67
+ clk <= 0
68
+ rst <= 0
69
+ fill <= 1
70
+
71
+ !10.ps
72
+ 10.times do |i|
73
+ clk <= 1
74
+ !10.ps
75
+ clk <= 0
76
+ !10.ps
77
+ end
78
+
79
+ fill <= 0
80
+ clk <= 1
81
+ !10.ps
82
+
83
+ # 計算の実行
84
+ clk <= 0
85
+ req <= 1
86
+ !10.ps
87
+ clk <= 1
88
+ !10.ps
89
+ clk <= 0
90
+ !10.ps
91
+ 30.times do
92
+ clk <= 1
93
+ !10.ps
94
+ clk <= 0
95
+ !10.ps
96
+ end
97
+ end
98
+ end
@@ -82,7 +82,7 @@ module HDLRuby::High::Std
82
82
  idx <= 0
83
83
  reading <= 0
84
84
  out_ack <= 0
85
- # hif(idx == size) { in_reqs.each { |req| req <= 0 } }
85
+ hif(idx == size-1) { in_acks.each { |ack| ack <= 0 } }
86
86
  # hif((idx == 0) & (in_reqs.reduce(_1) { |sum,req| req & sum })) do
87
87
  hif(idx == 0) do
88
88
  hif(~reading) do
@@ -90,7 +90,9 @@ module HDLRuby::High::Std
90
90
  end
91
91
  reading <= 1
92
92
  in_chs.each_with_index do |ch,i|
93
- ch.read(datas[i]) { in_acks[i] <= 1 }
93
+ hif(~in_acks[i]) do
94
+ ch.read(datas[i]) { in_acks[i] <= 1 }
95
+ end
94
96
  end
95
97
  end
96
98
  hif(in_acks.reduce(_1) { |sum,req| req & sum }) do
@@ -1,3 +1,3 @@
1
1
  module HDLRuby
2
- VERSION = "2.4.18"
2
+ VERSION = "2.4.19"
3
3
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: HDLRuby
3
3
  version: !ruby/object:Gem::Version
4
- version: 2.4.18
4
+ version: 2.4.19
5
5
  platform: ruby
6
6
  authors:
7
7
  - Lovic Gauthier
8
8
  autorequire:
9
9
  bindir: exe
10
10
  cert_chain: []
11
- date: 2020-12-04 00:00:00.000000000 Z
11
+ date: 2020-12-06 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: bundler
@@ -126,6 +126,7 @@ files:
126
126
  - lib/HDLRuby/hdr_samples/with_channel.rb
127
127
  - lib/HDLRuby/hdr_samples/with_class.rb
128
128
  - lib/HDLRuby/hdr_samples/with_connector.rb
129
+ - lib/HDLRuby/hdr_samples/with_connector_memory.rb
129
130
  - lib/HDLRuby/hdr_samples/with_decoder.rb
130
131
  - lib/HDLRuby/hdr_samples/with_fixpoint.rb
131
132
  - lib/HDLRuby/hdr_samples/with_fsm.rb