HDLRuby 2.4.14 → 2.4.20

data/lib/HDLRuby/hdr_samples/make_multi_channels_v.rb

@@ -0,0 +1,24 @@
+#!/usr/bin/ruby
+# Script for generating the vcd files.
+
+# The configuration scenarii
+$scenarii = [
+              [:_clk2_clk2,      :register],    #  0
+              [:_clk2_nclk2,     :register],    #  1
+              [:_clk2_clk3,      :register],    #  2
+              [:_clk3_clk2,      :register],    #  3
+              [:_clk2_clk2,      :handshake],   #  4
+              [:_clk2_nclk2,     :handshake],   #  5
+              [:_clk2_clk3,      :handshake],   #  6
+              [:_clk3_clk2,      :handshake],   #  7
+              [:clk2_clk2_clk2,  :queue],       #  8
+              [:clk2_clk2_nclk2, :queue],       #  9
+              [:clk1_clk2_clk3,  :queue],       # 10
+              [:clk3_clk2_clk1,  :queue],       # 11
+              [:clk2_clk3_clk1,  :queue],       # 12
+              [:clk2_clk1_clk3,  :queue],       # 13
+            ]
+$scenarii.each_with_index do |scenarii,i|
+    puts "scenario: [#{i}] #{scenarii}"
+    `bundle exec ../hdrcc.rb --verilog with_multi_channels.rb WithMultiChannelPaper.V#{i} #{i}`
+end

data/lib/HDLRuby/hdr_samples/with_connector.rb

@@ -125,20 +125,45 @@ end
 # Module for testing the connector.
 system :with_connectors do
     inner :clk, :rst
-    [4].inner :counter, :res_0,:res_1,:res_2,:res_3
+
+    # First tester.
+    [4].inner :counter
+    [4*4].inner :res
     inner :ack_in, :ack_out
+    inner :dup_req, :dup_ack
 
     # The input queue.
     queue(bit[4],4,clk,rst).(:in_qu)
 
-    # The first output queue.
-    queue(bit[4],4,clk,rst).(:out_qu0)
-    queue(bit[4],4,clk,rst).(:out_qu1)
-    queue(bit[4],4,clk,rst).(:out_qu2)
-    queue(bit[4],4,clk,rst).(:out_qu3)
+    # The middle queues.
+    mid_qus = 4.times.map do |i|
+        queue(bit[4],4,clk,rst).(:"mid_qu#{i}")
+    end
+
+    # The output queue.
+    queue(bit[4*4],4,clk,rst).(:out_qu)
+
+    # Connect the input queue to the middle queues.
+    duplicator(bit[4],clk.negedge,in_qu,mid_qus,dup_req,dup_ack)
+
+    # Connect the middle queues to the output queue.
+    merger([bit[4]]*4,clk.negedge,mid_qus,out_qu)
 
-    # Connect them
-    duplicator([4],clk.negedge,in_qu,[out_qu0,out_qu1,out_qu2,out_qu3])
+
+    # Second tester.
+    [4].inner :counterb
+    [4].inner :resb
+    inner :ack_inb0, :ack_inb1, :ack_outb
+
+    # The input queues.
+    queue(bit[4],4,clk,rst).(:in_qub0)
+    queue(bit[4],4,clk,rst).(:in_qub1)
+
+    # The output queue.
+    queue(bit[4],4,clk,rst).(:out_qub)
+
+    # Connect then with a serializer.
+    serializer(bit[4],clk.negedge,[in_qub0,in_qub1],out_qub)
 
     # # Slow version, always work
     # par(clk.posedge) do
@@ -154,10 +179,10 @@ system :with_connectors do
     #             end
     #         end
     #         hif(ack_in) do
-    #             out_qu0.read(res_0)
-    #             out_qu1.read(res_1)
-    #             out_qu2.read(res_2)
-    #             out_qu3.read(res_3) { ack_out <= 1 }
+    #             mid_qu0.read(res_0)
+    #             mid_qu1.read(res_1)
+    #             mid_qu2.read(res_2)
+    #             mid_qu3.read(res_3) { ack_out <= 1 }
     #         end
     #     end
     # end
@@ -165,17 +190,31 @@ system :with_connectors do
     # Fast version but assumes connected channels are blocking
     par(clk.posedge) do
         ack_in <= 0
-        hif(rst) { counter <= 0 }
+        ack_inb0 <= 0
+        ack_inb1 <= 0
+        hif(rst) { counter <= 0; counterb <= 0 }
         helse do
             in_qu.write(counter)  do
                 ack_in <= 1
                 counter <= counter + 1
             end
             hif(ack_in) do
-                out_qu0.read(res_0)
-                out_qu1.read(res_1)
-                out_qu2.read(res_2)
-                out_qu3.read(res_3)
+                out_qu.read(res)
+            end
+            hif(~ack_inb0) do
+                in_qub0.write(counterb) do
+                    ack_inb0 <= 1
+                    counterb <= counterb + 1
+                end
+            end
+            helse do
+                in_qub1.write(counterb) do
+                    ack_inb1 <= 1
+                    counterb <= counterb + 1
+                end
+            end
+            hif(ack_inb0 | ack_inb1) do
+                out_qub.read(resb)
             end
         end
     end
@@ -183,6 +222,7 @@ system :with_connectors do
     timed do
         clk <= 0
         rst <= 0
+        dup_req <= 0
         !10.ns
         clk <= 1
         !10.ns
@@ -197,6 +237,13 @@ system :with_connectors do
         !10.ns
         clk <= 0
         rst <= 0
+        4.times do
+            !10.ns
+            clk <= 1
+            !10.ns
+            clk <= 0
+        end
+        dup_req <= 1
         16.times do
             !10.ns
             clk <= 1

data/lib/HDLRuby/hdr_samples/with_connector_memory.rb

@@ -0,0 +1,98 @@
+require 'std/memory.rb'
+require "std/fixpoint.rb"
+require 'std/channel.rb'
+require 'std/connector.rb'
+
+include HDLRuby::High::Std
+
+system :channel_connector do
+    # データ型の宣言
+    integer_width = 4 # 整数部のビット幅
+    decimal_width = 4 # 実数部のビット幅
+    address_width = 4 # lutのアドレスのビット幅
+    typ = signed[integer_width + decimal_width] # データ型
+    
+    inputs_x = _00010011
+    inputs_h = _10100001
+    columns = [2, 2, 1]
+
+    inner :clk,   # clock
+          :rst,   # reset
+          :req,   # request
+          :fill   # 入力値のメモリへの書き込み
+
+    # inputs_x = quantize(inputs_x, typ, decimal_width)
+    # inputs_h = quantize(inputs_h, typ, decimal_width)
+
+    mem_rom(typ, columns[0], clk, rst, inputs_x, rinc: :rst, winc: :rst).(:rom_inputs_x) # 入力値を格納するrom(x)
+
+    mem_rom(typ, columns[0], clk, rst, inputs_h, rinc: :rst, winc: :rst).(:rom_inputs_h) # 入力値を格納するrom(h)
+
+    mem_dual(typ, columns[0], clk, rst, rinc: :rst, winc: :rst).(:ram_inputs_serializer) #
+
+    mem_dual(typ, columns[0]*2, clk, rst, rinc: :rst, winc: :rst).(:ram_inputs_merger) #
+
+    reader_inputs_x = rom_inputs_x.branch(:rinc) #入力値xの読みだし用branch
+    reader_inputs_h = rom_inputs_h.branch(:rinc) #入力値hの読みだし用branch
+    writer_inputs_serializer = ram_inputs_serializer.branch(:winc) #入力値を合成した値の書き込み用branch
+    writer_inputs_meger = ram_inputs_merger.branch(:winc) #入力値を合成した値の書き込み用branch
+  
+
+    serializer(typ,clk.negedge,[reader_inputs_x,reader_inputs_h],writer_inputs_serializer)
+
+    # merger([typ]*2,clk.negedge,[reader_inputs_x,reader_inputs_h], writer_inputs_meger)
+
+    # duplicator(typ,clk.negedge,reader_inputs_r,[])
+
+
+    timed do
+      # リセット
+      clk <= 0
+      rst <= 0
+      req <= 0
+      fill <= 0
+      !10.ps
+
+      # メモリ読み出し位置の初期化
+      rst <= 1
+      !10.ps
+      clk <= 1
+      !10.ps
+      clk <= 0
+      !10.ps
+      clk <= 1
+      !10.ps
+
+      # パラメータのメモリへの書き込み
+      clk <= 0
+      rst <= 0
+      fill <= 1
+
+      !10.ps
+      10.times do |i|
+        clk <= 1
+        !10.ps
+        clk <= 0
+        !10.ps
+      end
+
+      fill <= 0
+      clk <= 1
+      !10.ps
+
+      # 計算の実行
+      clk <= 0
+      req <= 1
+      !10.ps
+      clk <= 1
+      !10.ps
+      clk <= 0
+      !10.ps
+      30.times do
+        clk <= 1
+        !10.ps
+        clk <= 0
+        !10.ps
+      end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_multi_channels.rb

@@ -23,12 +23,6 @@ channel(:queue) do |typ,depth,clk,rst|
     par(clk.posedge) do
         hif(rst) { rptr <= 0; wptr <= 0 }
         helse do
-            # hif(rsync) do
-            #     hif(rptr != wptr) do
-            #         rdata <= buffer[rptr]
-            #     end
-            # end
-            # helse do
             hif(~rsync) do
                 hif (~rreq) { rack <= 0 }
                 hif(rreq & (~rack) & (rptr != wptr)) do
@@ -38,10 +32,6 @@ channel(:queue) do |typ,depth,clk,rst|
                 end
             end
 
-            # hif(wsync) do
-            #     buffer[wptr] <= wdata
-            # end
-            # helse do
             hif(~wsync) do
                 hif (~wreq) { wack <= 0 }
                 hif(wreq & (~wack) & (((wptr+1) % depth) != rptr)) do
@@ -67,7 +57,6 @@ channel(:queue) do |typ,depth,clk,rst|
             end
             seq do
                 hif(rptr != wptr) do
-                    # target <= rdata
                     target <= buffer[rptr]
                     rptr <= (rptr + 1) % depth
                     blk.call if blk
@@ -102,7 +91,6 @@ channel(:queue) do |typ,depth,clk,rst|
                 wreq <= 0
             end
             hif(((wptr+1) % depth) != rptr) do
-                # wdata <= target
                 buffer[wptr] <= target
                 wptr <= (wptr + 1) % depth
                 blk.call if blk

data/lib/HDLRuby/hruby_tools.rb

@@ -29,8 +29,14 @@ module HDLRuby
     class ::Integer
 
         # Gets the bit width
+        # NOTE: returns infinity if the number is negative.
         def width
-            return Math.log2(self+1).ceil
+            return self >= 0 ? Math.log2(self+1).ceil : 1.0/0.0
+        end
+
+        # Tells if the value is a power of 2.
+        def pow2?
+            return self > 0 && (self & (self - 1) == 0)
         end
     end
 

data/lib/HDLRuby/sim/hruby_sim_calc.c

@@ -1223,6 +1223,8 @@ static Value concat_value_bitstring_array(int num, int dir,
     }
     /* Resize the destination accordignly. */
     resize_value(dst,width);
+    /* Ensure it is not numeric. */
+    dst->numeric = 0;
 
     /* Access the data of the destination. */
     char* dst_data = dst->data_str;
@@ -1233,7 +1235,7 @@ static Value concat_value_bitstring_array(int num, int dir,
         unsigned int idx = dir ? (num-i-1) : i;
         Value value = args[idx];
         unsigned long long cw = type_width(value->type);
-        // printf("value=%s cw=%llu\n",value->data_str,cw);
+        // printf("value=%s cw=%llu pos=%llu\n",value->data_str,cw,pos);
         memcpy(dst_data+pos,value->data_str,cw);
         pos += cw;
     }

data/lib/HDLRuby/std/connector.rb

@@ -6,37 +6,124 @@ module HDLRuby::High::Std
 ########################################################################
 
     # Function for generating a connector that duplicates the output of
-    # channel +inch+ and connect it to channels +outchs+ with data of
+    # channel +in_ch+ and connect it to channels +out_chs+ with data of
     # +typ+.
     # The duplication is done according to event +ev+.
-    function :duplicator do |typ, ev, inch, outchs|
+    # The optional req and ack arguments are the signals for controlling the
+    # duplicator using a handshake protocol. If set to nil, the duplicator
+    # runs automatically.
+    function :duplicator do |typ, ev, in_ch, out_chs, req = nil, ack = nil|
         ev = ev.poswedge unless ev.is_a?(Event)
-        inner :in_ack, :in_req
-        out_chacks = outchs.map.with_index do |ch,i|
-            [ ch, inner(:"out_ack#{i}") ]
-        end
+        inner :in_ack
+        inner :in_req
+        out_acks = out_chs.size.times.map { |i| inner(:"out_ack#{i}") }
         typ.inner :data
         par(ev) do
-            in_req <= 1
-            out_chacks.each { |ch,ack| ack <= 0 }
-            out_chacks.each do |ch,ack| 
+            if (ack) then
+                # Output ack mode.
+                ack <= 0
+            end
+            if (req) then
+                # Input request mode.
+                in_req <= 0
+                hif(req) { in_req <= 1 }
+            else
+                # Automatic mode.
+                in_req <= 1
+            end
+            out_acks.each { |ack| ack <= 0 }
+            out_acks.each do |ack| 
                 hif(ack == 1) { in_req <= 0 }
             end
             hif(in_req) do
                 in_ack <= 0
-                inch.read(data) { in_ack <= 1 }
+                in_ch.read(data) { in_ack <= 1 }
             end
             hif(in_ack) do
-                out_chacks.each do |ch,ack|
+                out_chs.zip(out_acks).each do |ch,ack|
                     hif(ack == 0) { ch.write(data) { ack <= 1 } }
                 end
-                hif (out_chacks.reduce(_1) { |sum,(ch,ack)| ack & sum }) do
-                    out_chacks.each { |ch,ack| ack <= 0 }
+                hif (out_acks.reduce(_1) { |sum,ack| ack & sum }) do
+                    out_acks.each { |ack| ack <= 0 }
+                    if (ack) then
+                        # Output ack mode.
+                        ack <= 1
+                    end
+                end
+            end
+        end
+    end
+
+    # Function for generating a connector that merges the output of
+    # channels +in_chs+ and connects the result to channel +out_ch+ with
+    # data of types from +typs+.
+    # The merge is done according to event +ev+.
+    function :merger do |typs, ev, in_chs, out_ch|
+        ev = ev.posedge unless ev.is_a?(Event)
+        inner :out_ack
+        in_reqs = in_chs.size.times.map { |i| inner(:"in_req#{i}") }
+        in_acks = in_chs.size.times.map { |i| inner(:"in_ack#{i}") }
+        datas =   typs.map.with_index { |typ,i| typ.inner(:"data#{i}") }
+        par(ev) do
+            in_reqs.each { |req| req <= 1 }
+            out_ack <= 0
+            hif(out_ack == 1) { in_reqs.each { |req| req <= 0 } }
+            hif(in_reqs.reduce(_1) { |sum,req| req & sum }) do
+                in_chs.each_with_index do |ch,i|
+                    in_acks[i] <= 0
+                    ch.read(datas[i]) { in_acks[i] <= 1 }
                 end
             end
+            hif(in_acks.reduce(_1) { |sum,req| req & sum }) do
+                hif(out_ack == 0) { out_ch.write(datas) { out_ack <= 1 } }
+                hif (out_ack == 1) { out_ack <= 0 }
+            end
         end
     end
 
 
+    # Function for generating a connector that serialize to the output of
+    # channels +in_chs+ and connects the result to channel +out_ch+ with
+    # data of +typ+.
+    # The merge is done according to event +ev+.
+    function :serializer do |typ, ev, in_chs, out_ch|
+        ev = ev.posedge unless ev.is_a?(Event)
+        size = in_chs.size
+        inner :out_ack
+        # in_reqs = size.times.map { |i| inner(:"in_req#{i}") }
+        in_acks = size.times.map { |i| inner(:"in_ack#{i}") }
+        datas =   size.times.map { |i| typ.inner(:"data#{i}") }
+        # The inpt channel selector
+        [size.width].inner :idx
+        inner :reading
+        par(ev) do
+            # in_reqs.each { |req| req <= 1 }
+            idx <= 0
+            reading <= 0
+            out_ack <= 0
+            hif(idx == size-1) { in_acks.each { |ack| ack <= 0 } }
+            # hif((idx == 0) & (in_reqs.reduce(_1) { |sum,req| req & sum })) do
+            hif(idx == 0) do
+                hif(~reading) do
+                    size.times { |i| in_acks[i] <= 0 }
+                end
+                reading <= 1
+                in_chs.each_with_index do |ch,i|
+                    hif(~in_acks[i]) do
+                        ch.read(datas[i]) { in_acks[i] <= 1 }
+                    end
+                end
+            end
+            hif(in_acks.reduce(_1) { |sum,req| req & sum }) do
+                hcase(idx)
+                datas.each_with_index do |data,i|
+                    hwhen(i) do
+                        out_ch.write(data) { idx <= idx + 1; out_ack <= 1 }
+                    end
+                end
+            end
+        end
+    end
+
 
 end