HDLRuby 2.4.11 → 2.4.12

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: cbfb36d00f3809e50b2470308d24b09b413918ee4a78ab5f6cfc85c16af8ff50
-  data.tar.gz: e2883c6628972cb353fcf7438f1af07ba2c6700c4fdbddcf26ba9b3a00a5cdec
+  metadata.gz: 83c18b423b30c97938839cb341f03a35cf41a11ddedf90a2ec9609fe0da1b087
+  data.tar.gz: 39bd0518a77431e8b15dec7631f37bb6f0ff8e95639d107c71569cfe73c6630b
 SHA512:
-  metadata.gz: 2fa905701cad381e3d352524b1fd85f21ee3340e0eaa2b7d5579b93c6126d302bc35e407d10561a2e81a70b94137dda0a6398a49de1790fddeba1434a99ba467
-  data.tar.gz: 5d04403133e3ed080eef1f4494bcfc7694bcdd66ccace555361383c9f15a83c71f1994826171c4eaf5c20d5f059b9148c2e5cdfce7ba3d4b08691e57abf09395
+  metadata.gz: '0639d240f7f297771065b7781f3a78cab4628540b9616b2b3b28f64a044698f7030413cecaadeb038f816311bbb247ad7f7be715f12cc1893c0fcc3095bfe5bd'
+  data.tar.gz: d71455388840152cfbd8dc8a07743ed0970f8b319316e929c42576eb50757a70577fbeab737b6f8ea87d7f0bd9c6fbb1a3836dacbaa9dc869394798f2e1189d6

data/lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb

@@ -0,0 +1,25 @@
+#!/usr/bin/ruby
+# Script for generating the vcd files.
+
+# The configuration scenarii
+$scenarii = [
+              [:sync,  :register],     # 00
+              [:sync,  :handshake],    # 01
+              [:sync,  :queue],        # 02
+              [:nsync, :register],     # 03
+              [:nsync, :handshake],    # 04
+              [:nsync, :queue],        # 05
+              [:async, :register],     # 06
+              [:async, :handshake],    # 07
+              [:async, :queue],        # 08
+              [:proco, :register],     # 09
+              [:proco, :handshake],    # 10
+              [:proco, :queue],        # 11
+              [:double,:register],     # 12
+              [:double,:handshake],    # 13 
+              [:double,:queue]         # 14
+            ]
+(0..11).each do |i|
+    `bundle exec ../hdrcc.rb -S --vcd with_multi_channels.rb WithMultiChannelPaper #{i}`
+    `mv WithMultiChannelPaper/hruby_simulator.vcd WithMultiChannelPaper/#{i.to_s.to_s.rjust(2,"0")}_#{$scenarii[i][0]}_#{$scenarii[i][1]}.vcd`
+end

data/lib/HDLRuby/hdr_samples/mei8_bench.rb

@@ -5,7 +5,7 @@ include HDLRuby::High::Std
 # A simple implementation of the MEI8 processor.
 #
 # In this implementation, the program is hard-coded in an internal ROM
-system :mei8 do |prog_file = "./prog_encrypt.obj"|
+system :mei8 do |prog_file = "./prog.obj"|
     # Clock and reset.
     input :clk, :rst
     # Bus.

data/lib/HDLRuby/hdr_samples/with_fixpoint.rb

@@ -32,6 +32,18 @@ system :fix_test do
         !10.ns
         d <= d + c 
         !10.ns
+        d <= d / c
+        !10.ns
+        d <= d / 3.to_fix(4)
+        !10.ns
+        d <= 1.to_fix(4) - d
+        !10.ns
+        d <= -d
+        !10.ns
+        d <= d * 3.to_fix(4)
+        !10.ns
+        d <= -d
+        !10.ns
         a <= -0.375.to_fix(4)
         b <= 1.625.to_fix(4)
         !10.ns

data/lib/HDLRuby/hdr_samples/with_multi_channels.rb

@@ -60,12 +60,16 @@ channel(:queue) do |typ,depth,clk,rst|
             top_block.unshift do
                 rcmd <= 0
                 hrack <= 0
-            end
-            seq do
                 hif(rack) do
                     blk.call if blk
                 end
-                helse do
+            end
+            seq do
+                # hif(rack) do
+                #     blk.call if blk
+                # end
+                # helse do
+                hif(rack==0) do
                     rcmd <= 1 
                     target <= rdata
                 end
@@ -92,12 +96,16 @@ channel(:queue) do |typ,depth,clk,rst|
             top_block.unshift do
                 wcmd <= 0
                 hwack <= 0
-            end
-            seq do
                 hif(wack) do
                     blk.call if blk
                 end
-                helse { wcmd <= 1 }
+            end
+            seq do
+                # hif(wack) do
+                #     blk.call if blk
+                # end
+                # helse 
+                hif(wack==0) { wcmd <= 1 }
                 wdata <= target
             end
         end
@@ -173,48 +181,116 @@ channel(:handshake) do |typ|
     end
 end
 
+# Channel describing a handshake for transmitting data of +typ+ type, reset
+# by +rst+
+channel(:handshake2) do |typ|
+    # The data signal.
+    typ.inner :data
+    # The request and acknowledge.
+    inner :req, :ack
+    # The write flag
+    inner :wf
+
+    reader_input :ack, :data
+    reader_output :req
+
+    # The read primitive.
+    reader do |blk,target|
+        top_block.unshift do
+            req <= 0
+            hif(ack & req == 1) do
+                target <= data
+                req <= 0
+                blk.call if blk
+            end
+        end
+        hif(ack == 0) do
+            req <= 1
+        end
+    end
+
+    writer_input :req
+    writer_output :ack, :data
+    writer_inout :wf
+
+    # The read primitive.
+    writer do |blk,target|
+        top_block.unshift do
+            ack <= 0
+            hif(wf & req & ~ack == 1) do
+                data <= target
+                ack <= 1
+                blk.call if blk
+            end
+            hif(~req) { wf <= 0 }
+        end
+        hif(~ack) do
+            wf <= 1
+        end
+    end
+end
+
 
 # $mode = :sync
 # $mode = :nsync
 # $mode = :async
-# $mode = :proco  # Producter / Consummer
+# $mode = :proco  # Producer / Consummer
+# $mode = :double # Producer and Consummer with double channels.
 # $channel = :register
 # $channel = :handshake
 # $channel = :queue
 
 # The configuration scenarii
-$scenarii = [ [:sync,  :register], [:sync,  :handshake], [:sync,  :queue],
-              [:nsync, :register], [:nsync, :handshake], [:nsync, :queue],
-              [:async, :register], [:async, :handshake], [:async, :queue],
-              [:proco, :register], [:proco, :handshake], [:proco, :queue] ]
+$scenarii = [
+              [:sync,  :register],     #  0
+              [:sync,  :handshake],    #  1
+              [:sync,  :queue],        #  3
+              [:nsync, :register],     #  4
+              [:nsync, :handshake],    #  5
+              [:nsync, :queue],        #  6
+              [:async, :register],     #  7
+              [:async, :handshake],    #  8
+              [:async, :queue],        #  9
+              [:proco, :register],     # 10
+              [:proco, :handshake],    # 11
+              [:proco, :queue],        # 12
+              [:double,:register],     # 13
+              [:double,:handshake],    # 14
+              [:double,:queue]         # 15
+            ]
 
 # The configuration
-$mode, $channel = $scenarii[11]
+# $mode, $channel = $scenarii[11]
+$mode, $channel = $scenarii[ARGV[-1].to_i]
+puts "scenario: #{$scenarii[ARGV[-1].to_i]}"
 
 # Testing the queue channel.
 system :test_queue do
     inner :clk, :rst, :clk2, :clk3
-    [8].inner :idata, :odata
+    [8].inner :idata, :odata, :odata2
     [4].inner :counter
 
     if $channel == :register then
         register(bit[8]).(:my_ch)
+        register(bit[8]).(:my_ch2)
     elsif $channel == :handshake then
         handshake(bit[8],rst).(:my_ch)
+        handshake(bit[8],rst).(:my_ch2)
     elsif $channel == :queue then
         queue(bit[8],5,clk,rst).(:my_ch)
+        queue(bit[8],5,clk,rst).(:my_ch2)
     end
 
     ev = $mode == :sync ? clk.posedge : 
          $mode == :nsync ? clk.negedge : clk2.posedge
 
-    if $mode != :proco then
+    if $mode != :proco && $mode != :double then
         # Sync/Neg sync and async tests mode
         par(ev) do
             hif(rst) do
                 counter <= 0
                 idata <= 0
-                odata <= 0
+                # odata <= 0
             end
             helse do
                 hif (counter < 4) do
@@ -225,7 +301,7 @@ system :test_queue do
                 end
                 helsif ((counter > 10) & (counter < 15)) do
                     my_ch.read(odata) do
-                        idata <= idata - odata
+                        # idata <= idata - odata
                         counter <= counter + 1
                     end
                 end
@@ -234,7 +310,7 @@ system :test_queue do
                 end
             end
         end
-    else
+    elsif $mode == :proco then
         # Producter/consumer mode
         # Producer
         par(clk2.posedge) do
@@ -258,6 +334,25 @@ system :test_queue do
                 end
             end
         end
+    else
+        # Producer and consumer are commicating through two layers of channels
+        par(ev) do
+            hif(rst) do
+                counter <= 0
+                idata <= 0
+            end
+            helse do
+                my_ch.write(idata) do
+                    idata <= idata + 1
+                end
+                my_ch.read(odata) do
+                    my_ch2.write(odata)
+                end
+                my_ch2.read(odata2) do
+                    counter <= counter + 1
+                end
+            end
+        end
     end
 
     timed do

data/lib/HDLRuby/std/memory.rb

@@ -958,7 +958,7 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
         # Declares the address counter.
         awidth = (size-1).width
         awidth = 1 if awidth == 0
-        [size.width-1].inner :abus_r
+        [awidth].inner :abus_r
         reader_inout :abus_r
 
         # Defines the read procedure at address +addr+
@@ -1002,7 +1002,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             writer_input rst_name
         end
         # Declares the address counter.
-        [size.width-1].inner :abus_w
+        awidth = (size-1).width
+        awidth = 1 if awidth == 0
+        [awidth].inner :abus_w
         writer_inout :abus_w
 
         # Defines the write procedure at address +addr+
@@ -1050,7 +1052,7 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
         # Declares the address counter.
         awidth = (size-1).width
         awidth = 1 if awidth == 0
-        [size.width-1].inner :abus_r
+        [awidth].inner :abus_r
         reader_inout :abus_r
 
         # Defines the read procedure at address +addr+
@@ -1094,7 +1096,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             reader_input rst_name
         end
         # Declares the address counter.
-        [size.width-1].inner :abus_w
+        awidth = (size-1).width
+        awidth = 1 if awidth == 0
+        [awidth].inner :abus_w
         reader_inout :abus_w
 
         # Defines the write procedure at address +addr+

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.4.11"
+  VERSION = "2.4.12"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.4.11
+  version: 2.4.12
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-10-19 00:00:00.000000000 Z
+date: 2020-10-30 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -84,6 +84,7 @@ files:
 - lib/HDLRuby/hdr_samples/include.rb
 - lib/HDLRuby/hdr_samples/instance_open.rb
 - lib/HDLRuby/hdr_samples/linear_test.rb
+- lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb
 - lib/HDLRuby/hdr_samples/mei8.rb
 - lib/HDLRuby/hdr_samples/mei8_bench.rb
 - lib/HDLRuby/hdr_samples/memory_test.rb