HDLRuby 2.4.11 → 2.4.12
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb +25 -0
- data/lib/HDLRuby/hdr_samples/mei8_bench.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +12 -0
- data/lib/HDLRuby/hdr_samples/with_multi_channels.rb +112 -17
- data/lib/HDLRuby/std/memory.rb +8 -4
- data/lib/HDLRuby/version.rb +1 -1
- metadata +3 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
|
---
|
2
2
|
SHA256:
|
3
|
-
metadata.gz:
|
4
|
-
data.tar.gz:
|
3
|
+
metadata.gz: 83c18b423b30c97938839cb341f03a35cf41a11ddedf90a2ec9609fe0da1b087
|
4
|
+
data.tar.gz: 39bd0518a77431e8b15dec7631f37bb6f0ff8e95639d107c71569cfe73c6630b
|
5
5
|
SHA512:
|
6
|
-
metadata.gz:
|
7
|
-
data.tar.gz:
|
6
|
+
metadata.gz: '0639d240f7f297771065b7781f3a78cab4628540b9616b2b3b28f64a044698f7030413cecaadeb038f816311bbb247ad7f7be715f12cc1893c0fcc3095bfe5bd'
|
7
|
+
data.tar.gz: d71455388840152cfbd8dc8a07743ed0970f8b319316e929c42576eb50757a70577fbeab737b6f8ea87d7f0bd9c6fbb1a3836dacbaa9dc869394798f2e1189d6
|
@@ -0,0 +1,25 @@
|
|
1
|
+
#!/usr/bin/ruby
|
2
|
+
# Script for generating the vcd files.
|
3
|
+
|
4
|
+
# The configuration scenarii
|
5
|
+
$scenarii = [
|
6
|
+
[:sync, :register], # 00
|
7
|
+
[:sync, :handshake], # 01
|
8
|
+
[:sync, :queue], # 02
|
9
|
+
[:nsync, :register], # 03
|
10
|
+
[:nsync, :handshake], # 04
|
11
|
+
[:nsync, :queue], # 05
|
12
|
+
[:async, :register], # 06
|
13
|
+
[:async, :handshake], # 07
|
14
|
+
[:async, :queue], # 08
|
15
|
+
[:proco, :register], # 09
|
16
|
+
[:proco, :handshake], # 10
|
17
|
+
[:proco, :queue], # 11
|
18
|
+
[:double,:register], # 12
|
19
|
+
[:double,:handshake], # 13
|
20
|
+
[:double,:queue] # 14
|
21
|
+
]
|
22
|
+
(0..11).each do |i|
|
23
|
+
`bundle exec ../hdrcc.rb -S --vcd with_multi_channels.rb WithMultiChannelPaper #{i}`
|
24
|
+
`mv WithMultiChannelPaper/hruby_simulator.vcd WithMultiChannelPaper/#{i.to_s.to_s.rjust(2,"0")}_#{$scenarii[i][0]}_#{$scenarii[i][1]}.vcd`
|
25
|
+
end
|
@@ -5,7 +5,7 @@ include HDLRuby::High::Std
|
|
5
5
|
# A simple implementation of the MEI8 processor.
|
6
6
|
#
|
7
7
|
# In this implementation, the program is hard-coded in an internal ROM
|
8
|
-
system :mei8 do |prog_file = "./
|
8
|
+
system :mei8 do |prog_file = "./prog.obj"|
|
9
9
|
# Clock and reset.
|
10
10
|
input :clk, :rst
|
11
11
|
# Bus.
|
@@ -32,6 +32,18 @@ system :fix_test do
|
|
32
32
|
!10.ns
|
33
33
|
d <= d + c
|
34
34
|
!10.ns
|
35
|
+
d <= d / c
|
36
|
+
!10.ns
|
37
|
+
d <= d / 3.to_fix(4)
|
38
|
+
!10.ns
|
39
|
+
d <= 1.to_fix(4) - d
|
40
|
+
!10.ns
|
41
|
+
d <= -d
|
42
|
+
!10.ns
|
43
|
+
d <= d * 3.to_fix(4)
|
44
|
+
!10.ns
|
45
|
+
d <= -d
|
46
|
+
!10.ns
|
35
47
|
a <= -0.375.to_fix(4)
|
36
48
|
b <= 1.625.to_fix(4)
|
37
49
|
!10.ns
|
@@ -60,12 +60,16 @@ channel(:queue) do |typ,depth,clk,rst|
|
|
60
60
|
top_block.unshift do
|
61
61
|
rcmd <= 0
|
62
62
|
hrack <= 0
|
63
|
-
end
|
64
|
-
seq do
|
65
63
|
hif(rack) do
|
66
64
|
blk.call if blk
|
67
65
|
end
|
68
|
-
|
66
|
+
end
|
67
|
+
seq do
|
68
|
+
# hif(rack) do
|
69
|
+
# blk.call if blk
|
70
|
+
# end
|
71
|
+
# helse do
|
72
|
+
hif(rack==0) do
|
69
73
|
rcmd <= 1
|
70
74
|
target <= rdata
|
71
75
|
end
|
@@ -92,12 +96,16 @@ channel(:queue) do |typ,depth,clk,rst|
|
|
92
96
|
top_block.unshift do
|
93
97
|
wcmd <= 0
|
94
98
|
hwack <= 0
|
95
|
-
end
|
96
|
-
seq do
|
97
99
|
hif(wack) do
|
98
100
|
blk.call if blk
|
99
101
|
end
|
100
|
-
|
102
|
+
end
|
103
|
+
seq do
|
104
|
+
# hif(wack) do
|
105
|
+
# blk.call if blk
|
106
|
+
# end
|
107
|
+
# helse
|
108
|
+
hif(wack==0) { wcmd <= 1 }
|
101
109
|
wdata <= target
|
102
110
|
end
|
103
111
|
end
|
@@ -173,48 +181,116 @@ channel(:handshake) do |typ|
|
|
173
181
|
end
|
174
182
|
end
|
175
183
|
|
184
|
+
# Channel describing a handshake for transmitting data of +typ+ type, reset
|
185
|
+
# by +rst+
|
186
|
+
channel(:handshake2) do |typ|
|
187
|
+
# The data signal.
|
188
|
+
typ.inner :data
|
189
|
+
# The request and acknowledge.
|
190
|
+
inner :req, :ack
|
191
|
+
# The write flag
|
192
|
+
inner :wf
|
193
|
+
|
194
|
+
reader_input :ack, :data
|
195
|
+
reader_output :req
|
196
|
+
|
197
|
+
# The read primitive.
|
198
|
+
reader do |blk,target|
|
199
|
+
top_block.unshift do
|
200
|
+
req <= 0
|
201
|
+
hif(ack & req == 1) do
|
202
|
+
target <= data
|
203
|
+
req <= 0
|
204
|
+
blk.call if blk
|
205
|
+
end
|
206
|
+
end
|
207
|
+
hif(ack == 0) do
|
208
|
+
req <= 1
|
209
|
+
end
|
210
|
+
end
|
211
|
+
|
212
|
+
writer_input :req
|
213
|
+
writer_output :ack, :data
|
214
|
+
writer_inout :wf
|
215
|
+
|
216
|
+
# The read primitive.
|
217
|
+
writer do |blk,target|
|
218
|
+
top_block.unshift do
|
219
|
+
ack <= 0
|
220
|
+
hif(wf & req & ~ack == 1) do
|
221
|
+
data <= target
|
222
|
+
ack <= 1
|
223
|
+
blk.call if blk
|
224
|
+
end
|
225
|
+
hif(~req) { wf <= 0 }
|
226
|
+
end
|
227
|
+
hif(~ack) do
|
228
|
+
wf <= 1
|
229
|
+
end
|
230
|
+
end
|
231
|
+
end
|
232
|
+
|
176
233
|
|
177
234
|
# $mode = :sync
|
178
235
|
# $mode = :nsync
|
179
236
|
# $mode = :async
|
180
|
-
# $mode = :proco #
|
237
|
+
# $mode = :proco # Producer / Consummer
|
238
|
+
# $mode = :double # Producer and Consummer with double channels.
|
181
239
|
# $channel = :register
|
182
240
|
# $channel = :handshake
|
183
241
|
# $channel = :queue
|
184
242
|
|
185
243
|
# The configuration scenarii
|
186
|
-
$scenarii = [
|
187
|
-
[:
|
188
|
-
[:
|
189
|
-
[:
|
244
|
+
$scenarii = [
|
245
|
+
[:sync, :register], # 0
|
246
|
+
[:sync, :handshake], # 1
|
247
|
+
[:sync, :queue], # 3
|
248
|
+
[:nsync, :register], # 4
|
249
|
+
[:nsync, :handshake], # 5
|
250
|
+
[:nsync, :queue], # 6
|
251
|
+
[:async, :register], # 7
|
252
|
+
[:async, :handshake], # 8
|
253
|
+
[:async, :queue], # 9
|
254
|
+
[:proco, :register], # 10
|
255
|
+
[:proco, :handshake], # 11
|
256
|
+
[:proco, :queue], # 12
|
257
|
+
[:double,:register], # 13
|
258
|
+
[:double,:handshake], # 14
|
259
|
+
[:double,:queue] # 15
|
260
|
+
]
|
190
261
|
|
191
262
|
# The configuration
|
192
|
-
$mode, $channel = $scenarii[11]
|
263
|
+
# $mode, $channel = $scenarii[11]
|
264
|
+
$mode, $channel = $scenarii[ARGV[-1].to_i]
|
265
|
+
puts "scenario: #{$scenarii[ARGV[-1].to_i]}"
|
193
266
|
|
194
267
|
# Testing the queue channel.
|
195
268
|
system :test_queue do
|
196
269
|
inner :clk, :rst, :clk2, :clk3
|
197
|
-
[8].inner :idata, :odata
|
270
|
+
[8].inner :idata, :odata, :odata2
|
198
271
|
[4].inner :counter
|
199
272
|
|
200
273
|
if $channel == :register then
|
201
274
|
register(bit[8]).(:my_ch)
|
275
|
+
register(bit[8]).(:my_ch2)
|
202
276
|
elsif $channel == :handshake then
|
203
277
|
handshake(bit[8],rst).(:my_ch)
|
278
|
+
handshake(bit[8],rst).(:my_ch2)
|
204
279
|
elsif $channel == :queue then
|
205
280
|
queue(bit[8],5,clk,rst).(:my_ch)
|
281
|
+
queue(bit[8],5,clk,rst).(:my_ch2)
|
206
282
|
end
|
207
283
|
|
208
284
|
ev = $mode == :sync ? clk.posedge :
|
209
285
|
$mode == :nsync ? clk.negedge : clk2.posedge
|
210
286
|
|
211
|
-
if $mode != :proco then
|
287
|
+
if $mode != :proco && $mode != :double then
|
212
288
|
# Sync/Neg sync and async tests mode
|
213
289
|
par(ev) do
|
214
290
|
hif(rst) do
|
215
291
|
counter <= 0
|
216
292
|
idata <= 0
|
217
|
-
odata <= 0
|
293
|
+
# odata <= 0
|
218
294
|
end
|
219
295
|
helse do
|
220
296
|
hif (counter < 4) do
|
@@ -225,7 +301,7 @@ system :test_queue do
|
|
225
301
|
end
|
226
302
|
helsif ((counter > 10) & (counter < 15)) do
|
227
303
|
my_ch.read(odata) do
|
228
|
-
idata <= idata - odata
|
304
|
+
# idata <= idata - odata
|
229
305
|
counter <= counter + 1
|
230
306
|
end
|
231
307
|
end
|
@@ -234,7 +310,7 @@ system :test_queue do
|
|
234
310
|
end
|
235
311
|
end
|
236
312
|
end
|
237
|
-
|
313
|
+
elsif $mode == :proco then
|
238
314
|
# Producter/consumer mode
|
239
315
|
# Producer
|
240
316
|
par(clk2.posedge) do
|
@@ -258,6 +334,25 @@ system :test_queue do
|
|
258
334
|
end
|
259
335
|
end
|
260
336
|
end
|
337
|
+
else
|
338
|
+
# Producer and consumer are commicating through two layers of channels
|
339
|
+
par(ev) do
|
340
|
+
hif(rst) do
|
341
|
+
counter <= 0
|
342
|
+
idata <= 0
|
343
|
+
end
|
344
|
+
helse do
|
345
|
+
my_ch.write(idata) do
|
346
|
+
idata <= idata + 1
|
347
|
+
end
|
348
|
+
my_ch.read(odata) do
|
349
|
+
my_ch2.write(odata)
|
350
|
+
end
|
351
|
+
my_ch2.read(odata2) do
|
352
|
+
counter <= counter + 1
|
353
|
+
end
|
354
|
+
end
|
355
|
+
end
|
261
356
|
end
|
262
357
|
|
263
358
|
timed do
|
data/lib/HDLRuby/std/memory.rb
CHANGED
@@ -958,7 +958,7 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
958
958
|
# Declares the address counter.
|
959
959
|
awidth = (size-1).width
|
960
960
|
awidth = 1 if awidth == 0
|
961
|
-
[
|
961
|
+
[awidth].inner :abus_r
|
962
962
|
reader_inout :abus_r
|
963
963
|
|
964
964
|
# Defines the read procedure at address +addr+
|
@@ -1002,7 +1002,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
1002
1002
|
writer_input rst_name
|
1003
1003
|
end
|
1004
1004
|
# Declares the address counter.
|
1005
|
-
|
1005
|
+
awidth = (size-1).width
|
1006
|
+
awidth = 1 if awidth == 0
|
1007
|
+
[awidth].inner :abus_w
|
1006
1008
|
writer_inout :abus_w
|
1007
1009
|
|
1008
1010
|
# Defines the write procedure at address +addr+
|
@@ -1050,7 +1052,7 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
1050
1052
|
# Declares the address counter.
|
1051
1053
|
awidth = (size-1).width
|
1052
1054
|
awidth = 1 if awidth == 0
|
1053
|
-
[
|
1055
|
+
[awidth].inner :abus_r
|
1054
1056
|
reader_inout :abus_r
|
1055
1057
|
|
1056
1058
|
# Defines the read procedure at address +addr+
|
@@ -1094,7 +1096,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
1094
1096
|
reader_input rst_name
|
1095
1097
|
end
|
1096
1098
|
# Declares the address counter.
|
1097
|
-
|
1099
|
+
awidth = (size-1).width
|
1100
|
+
awidth = 1 if awidth == 0
|
1101
|
+
[awidth].inner :abus_w
|
1098
1102
|
reader_inout :abus_w
|
1099
1103
|
|
1100
1104
|
# Defines the write procedure at address +addr+
|
data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: HDLRuby
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 2.4.
|
4
|
+
version: 2.4.12
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Lovic Gauthier
|
8
8
|
autorequire:
|
9
9
|
bindir: exe
|
10
10
|
cert_chain: []
|
11
|
-
date: 2020-10-
|
11
|
+
date: 2020-10-30 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: bundler
|
@@ -84,6 +84,7 @@ files:
|
|
84
84
|
- lib/HDLRuby/hdr_samples/include.rb
|
85
85
|
- lib/HDLRuby/hdr_samples/instance_open.rb
|
86
86
|
- lib/HDLRuby/hdr_samples/linear_test.rb
|
87
|
+
- lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb
|
87
88
|
- lib/HDLRuby/hdr_samples/mei8.rb
|
88
89
|
- lib/HDLRuby/hdr_samples/mei8_bench.rb
|
89
90
|
- lib/HDLRuby/hdr_samples/memory_test.rb
|