HDLRuby 2.4.1 → 2.4.11

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 65ef28718e6de9e9d1358073d2d7ae8bd914a3f942b48d6cd45c8f28f545a906
-  data.tar.gz: 0d469d886d79f65ebfc69a4c4f95d2d8f50c0ada6f4fdbf0349d3c9650fa4581
+  metadata.gz: cbfb36d00f3809e50b2470308d24b09b413918ee4a78ab5f6cfc85c16af8ff50
+  data.tar.gz: e2883c6628972cb353fcf7438f1af07ba2c6700c4fdbddcf26ba9b3a00a5cdec
 SHA512:
-  metadata.gz: 4d458fe640fd29e1e31470b1f395333c3fd344703903c0c7d126e780d9e6f93c419f18a4e4cbaadc91461d19ed0087388a249fe3ccd87b2ed29d731733ecbc5b
-  data.tar.gz: 1ff098b2ca9bff7758bff7a5bb5e20df7272f53f103944037f9575b55444e6179781129e5d87e301a4e29b885bee5cc82794918ad85ac8236894603759d66212
+  metadata.gz: 2fa905701cad381e3d352524b1fd85f21ee3340e0eaa2b7d5579b93c6126d302bc35e407d10561a2e81a70b94137dda0a6398a49de1790fddeba1434a99ba467
+  data.tar.gz: 5d04403133e3ed080eef1f4494bcfc7694bcdd66ccace555361383c9f15a83c71f1994826171c4eaf5c20d5f059b9148c2e5cdfce7ba3d4b08691e57abf09395

data/lib/HDLRuby/hdr_samples/bstr_bench.rb

@@ -0,0 +1,14 @@
+
+# A benchmark for the bit string generation in case of signed values.
+system :bstr_bench do
+    signed[7..0].inner :val
+
+    timed do
+        val <= 0
+        !10.ns
+        val <= 26
+        !10.ns
+        val <= -25
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/neg_arith_bench.rb

@@ -0,0 +1,49 @@
+
+# A benchmark for testing the arithmetic with signed values.
+system :neg_arith_bench do
+    signed[11..0].inner :x,:y,:z
+
+    timed do
+        x <= 10
+        y <= 10
+        z <= 0
+        !10.ns
+        z <= 10 * 10
+        !10.ns
+        z <= x * y
+        !10.ns
+        x <= 10
+        y <= -10
+        !10.ns
+        z <= 10 * (-10)
+        !10.ns
+        z <= x * y
+        !10.ns
+        x <= -10
+        y <= 10
+        !10.ns
+        z <= (-10) * 10
+        !10.ns
+        z <= x * y
+        !10.ns
+        x <= -10
+        y <= -10
+        !10.ns
+        z <= (-10) * (-10)
+        !10.ns
+        z <= x * y
+        !10.ns
+        x <= _000000011010
+        y <= _000011111010
+        z <= 0
+        !10.ns
+        z <= x * y
+        !10.ns
+        x <= _000000011010
+        y <= _111111111010
+        z <= 0
+        !10.ns
+        z <= x * y
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/with_fixpoint.rb

@@ -31,5 +31,23 @@ system :fix_test do
         d <= 0
         !10.ns
         d <= d + c 
+        !10.ns
+        a <= -0.375.to_fix(4)
+        b <= 1.625.to_fix(4)
+        !10.ns
+        c <= a * b
+        !10.ns
+        # a <= _00010000
+        # b <= _00010101
+        a <= _0000111x
+        b <= _1110011x
+        !10.ns
+        # a <= a & _11111110
+        # b <= b | _00000001
+        a <= a | _00000001
+        b <= b | _00000001
+        !10.ns
+        c <= a * b
+        !10.ns
     end
 end

data/lib/HDLRuby/hdr_samples/with_memory_rom.rb

@@ -0,0 +1,53 @@
+require 'std/memory.rb'
+
+include HDLRuby::High::Std
+
+
+
+
+
+# A system testing the rom channel.
+system :rorm_test do
+    inner :clk,:rst
+    [8].inner :value
+    inner :addr
+
+    # Declares a 8-bit-data and 1 element rom address synchronous memory
+    # on negative edge of clk.
+    # mem_rom([8],2,clk,rst,[_00000110,_00000111], rinc: :rst).(:romI)
+    mem_rom([8],1,clk,rst,[_00000110], rinc: :rst).(:romI)
+    rd = romI.branch(:rinc)
+
+    par(clk.posedge) do
+        hif(rst) { addr <= 0 }
+        helse do
+            rd.read(value)
+        end
+    end
+
+    timed do
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        !10.ns
+        10.times do
+            clk <= 1
+            !10.ns
+            clk <= 0
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_multi_channels.rb

@@ -135,7 +135,7 @@ channel(:handshake) do |typ|
     # The data signal.
     typ.inner :data
     # The request and acknowledge.
-    typ.inner :req, :ack
+    inner :req, :ack
 
     reader_input :ack, :data
     reader_output :req
@@ -174,13 +174,22 @@ channel(:handshake) do |typ|
 end
 
 
-$mode = :prodcons
 # $mode = :sync
 # $mode = :nsync
 # $mode = :async
+# $mode = :proco  # Producter / Consummer
 # $channel = :register
 # $channel = :handshake
-$channel = :queue
+# $channel = :queue
+
+# The configuration scenarii
+$scenarii = [ [:sync,  :register], [:sync,  :handshake], [:sync,  :queue],
+              [:nsync, :register], [:nsync, :handshake], [:nsync, :queue],
+              [:async, :register], [:async, :handshake], [:async, :queue],
+              [:proco, :register], [:proco, :handshake], [:proco, :queue] ]
+
+# The configuration
+$mode, $channel = $scenarii[11]
 
 # Testing the queue channel.
 system :test_queue do
@@ -199,7 +208,7 @@ system :test_queue do
     ev = $mode == :sync ? clk.posedge : 
          $mode == :nsync ? clk.negedge : clk2.posedge
 
-    if $mode != :prodcons then
+    if $mode != :proco then
         # Sync/Neg sync and async tests mode
         par(ev) do
             hif(rst) do
@@ -263,27 +272,28 @@ system :test_queue do
         rst <= 1
         !3.ns
         clk2 <= 1
-        !1.ns
-        clk3 <= 1
-        !6.ns
+        !3.ns
+        clk3 <= 0
+        !4.ns
         clk <= 1
         !10.ns
         clk <= 0
-        rst <= 0
         !3.ns
         clk2 <= 0
-        !1.ns
+        !3.ns
         clk3 <= 1
-        !6.ns
+        !2.ns
+        rst <= 0
+        !2.ns
         64.times do
             clk <= 1
             !10.ns
             clk <= 0
             !3.ns
             clk2 <= ~clk2
-            !1.ns
+            !3.ns
             hif (clk2 == 0) { clk3 <= ~ clk3 }
-            !6.ns
+            !4.ns
         end
     end
 end

data/lib/HDLRuby/hruby_bstr.rb

@@ -32,13 +32,17 @@ module HDLRuby
         #   and negative when "1".
         # * when not present it is assumed to be within str.
         def initialize(str,sign = nil)
+            # puts "str=#{str}"
             # Maybe str is an numeric.
             if str.is_a?(Numeric) then
                 # Yes, convert it to a binary string.
-                str = str.to_s(2)
+                num = str
+                str = num.to_s(2)
                 # And fix the sign.
                 if str[0] == "-" then
-                    str = str[1..-1]
+                    # str = str[1..-1]
+                    str = (2**str.size+num).to_s(2)
+                    puts "str=#{str}"
                     sign = "-"
                 else
                     sign = "+"
@@ -71,6 +75,7 @@ module HDLRuby
                 end.reverse.join
             end
             @str += str.to_s.downcase
+            # puts "@str=#{@str}"
             unless @str.match(/^[0-1zx]+$/) then
                 raise "Invalid value for creating a bit string: #{str}"
             end

data/lib/HDLRuby/hruby_low2c.rb

@@ -111,6 +111,8 @@ module HDLRuby::Low
             res << "int main(int argc, char* argv[]) {\n"
             # Build the objects.
             objs.each { |obj| res << "   #{Low2C.make_name(obj)}();\n" }
+            # Sets the top systemT.
+            res << "   top_system = #{Low2C.obj_name(top)};\n"
             # Starts the simulation.
             res<< "   hruby_sim_core(\"#{name}\",#{init_visualizer},-1);\n"
             # Close the main.
@@ -1329,6 +1331,10 @@ module HDLRuby::Low
                 res << "block->owner = NULL;\n"
             end
 
+            # The name
+            res << " " * (level+1)*3
+            res << "block->name = \"#{self.name}\";\n"
+
             # Add the inner signals declaration.
             res << " " * (level+1)*3
             res << "block->num_inners = #{self.each_inner.to_a.size};\n"
@@ -1439,8 +1445,18 @@ module HDLRuby::Low
                 str = self.content.is_a?(BitString) ?
                     self.content.to_s : self.content.to_s(2).rjust(32,"0")
             else
-                sign = self.content>=0 ? "0" : "1"
-                str = self.content.abs.to_s(2).rjust(width,sign).upcase
+                # sign = self.content>=0 ? "0" : "1"
+                # str = self.content.abs.to_s(2).rjust(width,sign).upcase
+                if self.content >= 0 then
+                    str = self.content.to_s(2).rjust(width,"0").upcase
+                else
+                    # Compute the extension to the next multiple
+                    # of int_width
+                    ext_width = (((width-1) / Low2C.int_width)+1)*Low2C.int_width
+                    # Convert the string.
+                    str = (2**ext_width+self.content).to_s(2).upcase
+                end
+                # puts "content=#{self.content} str=#{str}"
             end
             # Is it a fully defined number?
             if str =~ /^[01]+$/ then
@@ -1453,13 +1469,14 @@ module HDLRuby::Low
                 res << " };\n"
                 # Create the value.
                 res << " " * (level+1)*3
-                # puts "str=#{str} type width=#{self.type.width}"
+                # puts "str=#{str} type width=#{self.type.width} signed? #{type.signed?}"
                 res << "return make_set_value(#{self.type.to_c(level+1)},1," +
                        "data);\n" 
             else
                 # No, generate a bit string value.
                 res << " " * (level+1)*3
-                res << "static unsigned char data[] = \"#{str}\";\n"
+                # res << "static unsigned char data[] = \"#{str}\";\n"
+                res << "static unsigned char data[] = \"#{str.reverse}\";\n"
                 # Create the value.
                 res << " " * (level+1)*3
                 res << "return make_set_value(#{self.type.to_c(level+1)},0," +

data/lib/HDLRuby/sim/hruby_sim.h

@@ -50,8 +50,9 @@ typedef enum {
 
 /* The interface to the type engine. */
 typedef struct FlagsS_ {
-    unsigned int all;
-    unsigned int sign : 1; /* Tells if the type is signed or not. */
+    // unsigned int all;
+    // unsigned int sign : 1; /* Tells if the type is signed or not. */
+    unsigned int sign; /* Tells if the type is signed or not. */
 } FlagsS;
 
 /** The type structure. */
@@ -474,6 +475,7 @@ typedef struct BlockS_ {
     Kind kind;          /* The kind of object. */
     Object owner;       /* The owner if any. */
 
+    char* name;         /* The name of the block. */
     int num_inners;     /* The number of inners. */
     SignalI* inners;    /* The inners of the scope. */
     void (*function)(); /* The function to execute for the block. */
@@ -496,6 +498,9 @@ typedef struct EventS_ {
 /* The time units. */
 typedef enum { S, MS, US, NS, PS, FS } Unit;
 
+/** The top system. */
+extern SystemT top_system;
+
 /** Adds a timed behavior for processing. 
  *  @param behavior the timed behavior to register */
 extern void register_timed_behavior(Behavior behavior);
@@ -574,17 +579,17 @@ typedef struct {
     void (*print_signal)(SignalI);
 } PrinterS;
 
-PrinterS printer;
+extern PrinterS printer;
 
 /** Initializes the visualization printer engine.
  *  @param print_time the time printer
  *  @param print_name the name printer
  *  @param print_value the value printer
  *  @param print_signal the signal state printer. */
-void init_visualizer(void (*print_time)(unsigned long long), 
-                     void (*print_name)(Object),
-                     void (*print_value)(Value),
-                     void (*print_signal)(SignalI));
+extern void init_visualizer(void (*print_time)(unsigned long long), 
+                            void (*print_name)(Object),
+                            void (*print_value)(Value),
+                            void (*print_signal)(SignalI));
 
 // /** Prints the time.
 //  *  @param time the time to show. */

data/lib/HDLRuby/sim/hruby_sim_calc.c

@@ -70,7 +70,8 @@ static List hash_type[HASH_TYPE_SIZE] = {};
  *  @return the resulting type. */
 static int hash_value(unsigned long long base, unsigned long long number,
                       FlagsS flags) {
-    return ((base+flags.all)^(number)) & 1023;
+    // return ((base+flags.all)^(number)) & 1023;
+    return ((base+flags.sign)^(number)) & 1023;
 }
 
 /** Adds a type to the hash of types.
@@ -109,7 +110,8 @@ static Type get_hash_type(Type base, unsigned long long number) {
         while(elem) {
             Type type = elem->data;
             if ((type->base == bw) && (type->number == number) &&
-                (type->flags.all == flags.all)) {
+                // (type->flags.all == flags.all)) {
+                (type->flags.sign == flags.sign)) {
                 /* The type is found. */
                 return type;
             }
@@ -243,8 +245,10 @@ void resize_value(Value value, int size) {
 void set_value(Value value, int numeric, void* data) {
     value->numeric = numeric;
     if (numeric) {
+    // printf("set_value with data=%llx\n",*(unsigned long long*)data);
         value->data_int = *((unsigned long long*)data);
     } else  {
+        // printf("data=%s\n",(char*)data);
         memcpy(value->data_str,data,type_width(value->type)*sizeof(char));
     }
 }
@@ -254,6 +258,7 @@ void set_value(Value value, int numeric, void* data) {
  *  @param numeric tell if the value is in numeric form or in bitstring form
  *  @param data the source data */
 Value make_set_value(Type type, int numeric, void* data) {
+    // printf("make_set_value with type->flags.sign=%x\n",type->flags.sign);
     Value value = make_value(type,numeric);
     set_value(value,numeric,data);
     return value;
@@ -307,6 +312,7 @@ Value copy_value(Value src, Value dst) {
         /* Numeric copy. */
         dst->data_int = fix_numeric_type(dst->type,src->data_int);
     } else {
+        // printf("copy_value with bit string: %s\n",src->data_str);
         /* Resize the destination if required. */
         resize_value(dst,type_width(dst->type));
         /* Bitstring copy up to the end of dst or src. */
@@ -603,12 +609,14 @@ static Value sub_value_bitstring(Value src0, Value src1, Value dst) {
  *  @param dst the destination value
  *  @return dst */
 static Value mul_value_defined_bitstring(Value src0, Value src1, Value dst) {
+    // printf("mul_value_defined_bitstring with src0=%llx src1=%llx\n",value2integer(src0),value2integer(src1));
     /* Sets state of the destination using the first source. */
     dst->type = src0->type;
     dst->numeric = 1;
 
     /* Perform the multiplication. */
     dst->data_int = value2integer(src0) * value2integer(src1);
+    // printf("dst->data_int=%llx\n",dst->data_int);
     return dst;
 }
 
@@ -1172,7 +1180,7 @@ static Value equal_value_bitstring(Value src0, Value src1, Value dst) {
 static Value select_value_bitstring(Value cond, Value dst, unsigned int num,
         va_list args) 
 {
-    printf("select_value_bitstring with cond=%s\n",cond->data_str);
+    // printf("select_value_bitstring with cond=%s\n",cond->data_str);
     /* Get the first alternative for sizing the result. */
     Value src = va_arg(args,Value);
     /* Compute the width of the result in bits. */
@@ -1556,6 +1564,7 @@ static Value sub_value_numeric(Value src0, Value src1, Value dst) {
  *  @param dst the destination value
  *  @return dst */
 static Value mul_value_numeric(Value src0, Value src1, Value dst) {
+    // printf("mul_value_numeric with src0->data_int=%llx src1->data_int=%llx\n",src0->data_int, src1->data_int);
     /* Sets state of the destination using the first source. */
     dst->type = src0->type;
     dst->numeric = 1;
@@ -1823,7 +1832,7 @@ static Value concat_value_numeric_array(int num, int dir,
  *  @param dst the destination value
  *  @return dst */
 static Value cast_value_numeric(Value src, Type type, Value dst) {
-    // printf("cast_value_numeric with src=%llx",src->data_int);
+    // printf("cast_value_numeric with src=%llx\n",src->data_int);
     /* Copy the source to the destination. */
     dst->data_int = src->data_int;
     /* Update the destination type to the cast. */
@@ -2665,6 +2674,7 @@ unsigned long long value2integer(Value value) {
     char bit;
     /* Access the bitstring data. */
     char* data_str = value->data_str;
+    // printf("value2integer with data_str=%s\n",data_str);
     /* Copy the bits. */
     for (i=0; i<width && i<LONG_LONG_BIT; ++i) {
         /* Get the bit. */
@@ -2676,12 +2686,17 @@ unsigned long long value2integer(Value value) {
         /* Write the bit. */
         res = (res << 1) | bit;
     }
+    // printf("first res=%llx\n",res);
+    unsigned long long bit0 = (data_str[width-1]-'0') << i;
     /* Perform the sign extension if required. */
     if (i>=width && value->type->flags.sign) {
         for(; i<LONG_LONG_BIT; ++i) {
-            res = (res << 1) | bit;
+            // res = (res << 1) | bit;
+            res |= bit0;
+            bit0 <<= 1;
         }
     }
+    // printf("then res=%llx\n",res);
     return res;
 }
 

data/lib/HDLRuby/sim/hruby_sim_core.c

@@ -12,6 +12,9 @@
  *  hruby_low2c. 
  *  */
 
+/** The top system. */
+SystemT top_system;
+
 /** The number of all the signals. */
 static int num_all_signals = 0;
 /** The capacity of the set of signals. */

data/lib/HDLRuby/sim/hruby_sim_vcd.c

@@ -64,35 +64,49 @@ static void vcd_print_time(unsigned long long time) {
 }
 
 
-/** Prints the name of an object.
+/** Prints the name of an object without its hierarchy.
  *  @param object the object to print the name. */
 static void vcd_print_name(Object object) {
-    /* Recurse on the owner if any. */
-    // printf("owner=%p\n",object->owner);
-    if (object->owner != NULL) {
-        vcd_print_name(object->owner);
-        vcd_print("$");
-    }
     /* Depending on the kind of object. */
     switch(object->kind) {
         case SYSTEMT:
         case SIGNALI:
         case SCOPE:
         case SYSTEMI:
+        case BLOCK:
             /* Print the name if name. */
             /* Trick: SystemT, SignalI, Scope and SystemI have the
              * field name at the same place. */
-            if (((SystemI)object)->name != NULL) {
+            if ((((Block)object)->name != NULL) &&
+                    strlen(((Block)object)->name)>0) {
                 char name[256];
-                strncpy(name,((SystemI)object)->name,256);
+                strncpy(name,((Block)object)->name,256);
                 replace_char(name,':','$');
                 vcd_print("%s",name);
+            } else {
+                /* No name, use the address of the object as name generator.*/
+                vcd_print("$%p",(void*)object);
             }
+            break;
         default: /* Nothing to do */
             break;
     }
 }
 
+
+/** Prints the name of an object incluing its heirarchy.
+ *  @param object the object to print the name. */
+static void vcd_print_full_name(Object object) {
+    /* Recurse on the owner if any. */
+    // printf("owner=%p\n",object->owner);
+    if (object->owner != NULL) {
+        vcd_print_full_name(object->owner);
+        vcd_print("$");
+    }
+    /* Print the name of the object. */
+    vcd_print_name(object);
+}
+
 /** Prints a value.
  *  @param value the value to print */
 static void vcd_print_value(Value value) {
@@ -127,23 +141,169 @@ static void vcd_print_value(Value value) {
  *  @param signal the signal to declare */
 static void vcd_print_var(SignalI signal) {
     vcd_print("$var wire %d ",type_width(signal->type));
-    vcd_print_name((Object)signal);
+    vcd_print_full_name((Object)signal);
     vcd_print(" ");
     vcd_print_name((Object)signal);
     vcd_print(" $end\n");
 }
 
 
-/** Prints a signal.
+/** Prints a signal with its future value if any.
  *  @param signal the signal to show */
-static void vcd_print_signal(SignalI signal) {
-    vcd_print_value(signal->f_value);
-    vcd_print(" ");
-    vcd_print_name((Object)signal);
-    vcd_print("\n");
+static void vcd_print_signal_fvalue(SignalI signal) {
+    if (signal->f_value) {
+        vcd_print_value(signal->f_value);
+        vcd_print(" ");
+        vcd_print_full_name((Object)signal);
+        vcd_print("\n");
+    }
+}
+
+
+/** Prints a signal with its current value if any
+ *  @param signal the signal to show */
+static void vcd_print_signal_cvalue(SignalI signal) {
+    if (signal->c_value) {
+        vcd_print_value(signal->c_value);
+        vcd_print(" ");
+        vcd_print_full_name((Object)signal);
+        vcd_print("\n");
+    }
+}
+
+
+/** Prints the hierarchy content of a system type.
+ *  @param system the system to print. */
+static void vcd_print_systemT_content(SystemT system);
+
+/** Prints the hierarchy of a scope.
+ *  @param scope the scope to print. */
+static void vcd_print_scope(Scope scope);
+
+
+/** Prints the hierarchy of a block.
+ *  @param block the block to print. */
+static void vcd_print_block(Block block) {
+    int i;
+    /* Do not print block with no declaration. */
+    if (block->num_inners == 0) return;
+
+    /* Declares the block if named. */
+    vcd_print("$scope module ");
+    vcd_print_name((Object)block);
+    vcd_print(" $end\n");
+
+    /* Declare the inners of the systems. */
+    for(i=0; i<block->num_inners; ++i) {
+        vcd_print_var(block->inners[i]);
+    }
+
+    /* Close the hierarchy. */
+    vcd_print("$upscope $end\n");
 }
 
 
+/** Prints the hierarchy of a system instances.
+ *  @param scope the scope to print. */
+static void vcd_print_systemI(SystemI systemI) {
+    /* Declares the systemI. */
+    vcd_print("$scope module ");
+    vcd_print_name((Object)systemI);
+    vcd_print(" $end\n");
+
+    /* Declares its content. */
+    vcd_print_systemT_content(systemI->system);
+
+    /* Close the hierarchy. */
+    vcd_print("$upscope $end\n");
+}
+
+
+/** Prints the hierarchy inside a scope.
+ *  @param scope the scope to print the inside. */
+static void vcd_print_scope_content(Scope scope) {
+    int i;
+
+    /* Declare the inners of the systems. */
+    for(i=0; i<scope->num_inners; ++i) {
+        vcd_print_var(scope->inners[i]);
+    }
+
+    /* Recurse on the system instances. */
+    for(i=0; i<scope->num_systemIs; ++i) {
+        vcd_print_systemI(scope->systemIs[i]);
+    }
+
+    /* Recurse on the sub scopes. */
+    for(i=0; i<scope->num_scopes; ++i) {
+        vcd_print_scope(scope->scopes[i]);
+    }
+
+    /* Recurse on the behaviors. */
+    for(i=0; i<scope->num_behaviors; ++i) {
+        vcd_print_block(scope->behaviors[i]->block);
+    }
+}
+
+
+/** Prints the hierarchy of a scope.
+ *  @param scope the scope to print. */
+static void vcd_print_scope(Scope scope) {
+    /* Do not print block with no declaration. */
+    if (scope->num_inners == 0 && scope->num_scopes == 0 && scope->num_behaviors == 0) return;
+    /* Declares the scope. */
+    vcd_print("$scope module ");
+    vcd_print_name((Object)scope);
+    vcd_print(" $end\n");
+
+    /* Declares its content. */
+    vcd_print_scope_content(scope);
+
+    /* Close the hierarchy. */
+    vcd_print("$upscope $end\n");
+}
+
+
+/** Prints the hierarchy content of a system type.
+ *  @param system the system to print. */
+static void vcd_print_systemT_content(SystemT system) {
+    int i;
+
+    /* Declare the inputs of the systems. */
+    for(i = 0; i<system->num_inputs; ++i) {
+        vcd_print_var(system->inputs[i]);
+    }
+    /* Declare the outputs of the systems. */
+    for(i = 0; i<system->num_outputs; ++i) {
+        vcd_print_var(system->outputs[i]);
+    }
+    /* Declare the inouts of the systems. */
+    for(i = 0; i<system->num_inouts; ++i) {
+        vcd_print_var(system->inouts[i]);
+    }
+    /* Recurse on the content of the scope (the scope header is the system).*/
+    vcd_print_scope_content(system->scope);
+}
+
+
+/** Prints the hierarchy of a system type.
+ *  @param system the system to print. */
+static void vcd_print_systemT(SystemT system) {
+    int i;
+    /* Declares the module. */
+    vcd_print("$scope module ");
+    vcd_print_name((Object)system);
+    vcd_print(" $end\n");
+
+    /* Declares the content. */
+    vcd_print_systemT_content(system);
+
+    /* Close the hierarchy. */
+    vcd_print("$upscope $end\n");
+}
+
+
+
 
 
 /* high-end print functions. */
@@ -164,7 +324,7 @@ static void vcd_print_header() {
     /* The version section. */
     vcd_print("$version\n");
     vcd_print("   Generated from HDLRuby simulator\n");
-    vcd_print("$end");
+    vcd_print("$end\n");
     
     /* The comment section. */
     vcd_print("$comment\n");
@@ -174,20 +334,25 @@ static void vcd_print_header() {
     /* The time scale section: for now 1ps only. */
     vcd_print("$timescale 1ps $end\n");
 
-    /* The scope section: nothing specific. */
-    vcd_print("$scope module logic $end\n");
+    // /* The scope section: nothing specific. */
+    // vcd_print("$scope module logic $end\n");
 
-    /* The variables declaration. */
-    each_all_signal(&vcd_print_var);
+    // /* The variables declaration. */
+    // each_all_signal(&vcd_print_var);
 
+    // /* Ends the declarations. */
+    // vcd_print("$upscope $end\n");
+    // vcd_print("$enddefinitions $end\n");
+
+    /* The declaration of the hierarchy and the variables
+     * from the top system. */
+    vcd_print_systemT(top_system);
     /* Ends the declarations. */
-    vcd_print("$upscope $end\n");
     vcd_print("$enddefinitions $end\n");
 
     /* Display the initializations. */
     vcd_print("$dumpvars\n");
-    // Maybe nothing to do.
-    // each_all_init_signal(&vcd_print_signal);
+    each_all_signal(&vcd_print_signal_cvalue);
     vcd_print("$end\n");
 }
 
@@ -206,9 +371,9 @@ extern void init_vcd_visualizer(char* name) {
 
     /* Initialize the vizualizer printer engine. */
     init_visualizer(&vcd_print_time,
-                    &vcd_print_name,
+                    &vcd_print_full_name,
                     &vcd_print_value,
-                    &vcd_print_signal);
+                    &vcd_print_signal_fvalue);
 
     /* Prints the header of the vcd file. */
     vcd_print_header();

data/lib/HDLRuby/std/fixpoint.rb

@@ -52,10 +52,18 @@ module HDLRuby::High::Std
                         end
                         # Redefine the multiplication and division for fixed point.
                         typ.define_operator(:*) do |left,right|
-                            (left.as([isize+fsize*2])*right) >> fsize
+                            if (typ.signed?) then
+                                (left.as(signed[isize+fsize*2])*right) >> fsize
+                            else
+                                (left.as([isize+fsize*2])*right) >> fsize
+                            end
                         end
                         typ.define_operator(:/) do |left,right|
-                            (left.as([isize+fsize*2]) << fsize) / right
+                            if (typ.signed?) then
+                                (left.as(signed[isize+fsize*2]) << fsize) / right
+                            else
+                                (left.as([isize+fsize*2]) << fsize) / right
+                            end
                         end
                         typ
                     end

data/lib/HDLRuby/std/linear.rb

@@ -209,6 +209,7 @@ module HDLRuby::High::Std
         # lv and rv are valid.
         lvoks = lefts.each_with_index.map { |left,i| inner :"lvok#{i}" }
         inner :rvok
+        woks = lefts.each_with_index.map { |left,i| inner :"wok#{i}" }
         # Run flag
         inner :run
         par(ev) do
@@ -218,28 +219,39 @@ module HDLRuby::High::Std
                 rvok <= 0
                 lefts.each_with_index do |left,i|
                     lvoks[i] <= 0
-                    # accs[i].write(0)
-                    avs[i] <= 0
+                    # avs[i] <= 0
+                    woks[i] <= 0
                 end
             end
             hif(req | run) do
                 run <= 1
                 # Computation request.
-                right.read(rv) { rvok <= 1 }
+                hif(~rvok) { right.read(rv) { rvok <= 1 } }
                 lefts.each_with_index do |left,i|
-                    left.read(lvs[i])  { lvoks[i] <= 1 }
+                    hif(~lvoks[i]) { left.read(lvs[i])  { lvoks[i] <= 1 } }
                     # accs[i].read(avs[i])
-                    hif(lvoks[i] & rvok) do
+                    hif(lvoks[i] & rvok & ~woks[i]) do
                         ack <= 1
                         run <= 0
-                        # accs[i].write(add.(avs[i],mul.(lvs[i],rv)))
                         seq do
                             avs[i] <= add.(avs[i],mul.(lvs[i],rv))
-                            accs[i].write(avs[i])
+                            accs[i].write(avs[i]) do
+                                woks[i] <= 1
+                                # seq do
+                                #     lvoks[i] <= 0
+                                #     rvok <= lvoks.reduce(:|)
+                                # end
+                            end
                         end
                     end
+                    hif (woks.reduce(:&)) do
+                        woks.each { |wok| wok <= 0 }
+                        lvoks.each { | lvok| lvok <=0 }
+                        rvok <= 0
+                    end
                 end
             end
+            helse { avs.each {|av| av <= 0 } }
             # helse do
             #     rvok <= 0
             #     lefts.each_with_index do |left,i|

data/lib/HDLRuby/std/memory.rb

@@ -34,6 +34,7 @@ HDLRuby::High::Std.channel(:mem_sync) do |n,typ,size,clk_e,rst,br_rsts = []|
     size = size.to_i
     # Compute the address bus width from the size.
     awidth = (size-1).width
+    awidth = 1 if awidth == 0
     # Ensure clk_e is an event, if not set it to a positive edge.
     clk_e = clk_e.posedge unless clk_e.is_a?(Event)
 
@@ -209,6 +210,7 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
     size = size.to_i
     # Compute the address bus width from the size.
     awidth = (size-1).width
+    awidth = 1 if awidth == 0
     # Process the table of reset mapping for the branches.
     # Ensures br_srts is a hash.
     br_rsts = br_rsts.to_hash
@@ -292,17 +294,43 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
                 trig_r <= 0
             end
             # The read procedure.
+        #     par do
+        #         hif(rst == 0) do
+        #             # No reset, so can perform the read.
+        #             hif(trig_r == 1) do
+        #                 # The trigger was previously set, read ok.
+        #                 target <= dbus_r
+        #                 blk.call if blk
+        #             end
+        #             # Prepare the read.
+        #             abus_r <= abus_r + 1
+        #             trig_r <= 1
+        #         end
+        #     end
+            # The read procedure.
             par do
                 hif(rst == 0) do
                     # No reset, so can perform the read.
                     hif(trig_r == 1) do
                         # The trigger was previously set, read ok.
-                        target <= dbus_r
-                        blk.call if blk
+                        # target <= dbus_r
+                        # blk.call if blk
+                        seq do
+                            # abus_r <= abus_r + 1
+                            target <= dbus_r
+                            blk.call if blk
+                        end
+                    end
+                    helse do
+                        # Prepare the read.
+                        # abus_r <= abus_r + 1
+                        if 2**size.width != size then
+                            abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
+                        else
+                            abus_r <= abus_r + 1
+                        end
+                        trig_r <= 1
                     end
-                    # Prepare the read.
-                    abus_r <= abus_r + 1
-                    trig_r <= 1
                 end
             end
         end
@@ -331,18 +359,44 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
                 # Reset so switch of the access trigger.
                 trig_r <= 0
             end
+            # # The read procedure.
+            # par do
+            #     hif(rst == 0) do
+            #         # No reset, so can perform the read.
+            #         hif(trig_r == 1) do
+            #             # The trigger was previously set, read ok.
+            #             target <= dbus_r
+            #             blk.call if blk
+            #         end
+            #         # Prepare the read.
+            #         abus_r <= abus_r - 1
+            #         trig_r <= 1
+            #     end
+            # end
             # The read procedure.
             par do
                 hif(rst == 0) do
                     # No reset, so can perform the read.
                     hif(trig_r == 1) do
                         # The trigger was previously set, read ok.
-                        target <= dbus_r
-                        blk.call if blk
+                        # target <= dbus_r
+                        # blk.call if blk
+                        seq do
+                            # abus_r <= abus_r - 1
+                            target <= dbus_r
+                            blk.call if blk
+                        end
+                    end
+                    helse do
+                        # Prepare the read.
+                        # abus_r <= abus_r - 1
+                        if 2**size.width != size then
+                            abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
+                        else
+                            abus_r <= abus_r - 1
+                        end
+                        trig_r <= 1
                     end
-                    # Prepare the read.
-                    abus_r <= abus_r - 1
-                    trig_r <= 1
                 end
             end
         end
@@ -392,6 +446,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
     size = size.to_i
     # Compute the address bus width from the size.
     awidth = (size-1).width
+    awidth = 1 if awidth == 0
     # Process the table of reset mapping for the branches.
     # puts "first br_rsts=#{br_rsts}"
     # if br_rsts.is_a?(Array) then
@@ -541,12 +596,24 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     # No reset, so can perform the read.
                     hif(trig_r == 1) do
                         # The trigger was previously set, read ok.
-                        target <= dbus_r
-                        blk.call if blk
+                        # target <= dbus_r
+                        # blk.call if blk
+                        seq do
+                            # abus_r <= abus_r + 1
+                            target <= dbus_r
+                            blk.call if blk
+                        end
+                    end
+                    helse do
+                        # Prepare the read.
+                        # abus_r <= abus_r + 1
+                        if 2**size.width != size then
+                            abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
+                        else
+                            abus_r <= abus_r + 1
+                        end
+                        trig_r <= 1
                     end
-                    # Prepare the read.
-                    abus_r <= abus_r + 1
-                    trig_r <= 1
                 end
             end
         end
@@ -581,7 +648,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     # No reset, so can perform the write.
                     blk.call if blk
                     # Prepare the write.
-                    abus_w <= abus_w + 1
+                    # abus_w <= abus_w + 1
+                    if 2**size.width != size then
+                        abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
+                    else
+                        abus_w <= abus_w + 1
+                    end
                     trig_w <= 1
                     dbus_w <= target
                 end
@@ -613,18 +685,44 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                 # Reset so switch of the access trigger.
                 trig_r <= 0
             end
+            # # The read procedure.
+            # par do
+            #     hif(rst == 0) do
+            #         # No reset, so can perform the read.
+            #         hif(trig_r == 1) do
+            #             # The trigger was previously set, read ok.
+            #             target <= dbus_r
+            #             blk.call if blk
+            #         end
+            #         # Prepare the read.
+            #         abus_r <= abus_r - 1
+            #         trig_r <= 1
+            #     end
+            # end
             # The read procedure.
             par do
                 hif(rst == 0) do
                     # No reset, so can perform the read.
                     hif(trig_r == 1) do
                         # The trigger was previously set, read ok.
-                        target <= dbus_r
-                        blk.call if blk
+                        # target <= dbus_r
+                        # blk.call if blk
+                        seq do
+                            # abus_r <= abus_r - 1
+                            target <= dbus_r
+                            blk.call if blk
+                        end
+                    end
+                    helse do
+                        # Prepare the read.
+                        # abus_r <= abus_r - 1
+                        if 2**size.width != size then
+                            abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
+                        else
+                            abus_r <= abus_r - 1
+                        end
+                        trig_r <= 1
                     end
-                    # Prepare the read.
-                    abus_r <= abus_r - 1
-                    trig_r <= 1
                 end
             end
         end
@@ -659,7 +757,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
                     # No reset, so can perform the write.
                     blk.call if blk
                     # Prepare the write.
-                    abus_w <= abus_w - 1
+                    # abus_w <= abus_w - 1
+                    if 2**size.width != size then
+                        abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
+                    else
+                        abus_w <= abus_w - 1
+                    end
                     trig_w <= 1
                     dbus_w <= target
                 end
@@ -853,6 +956,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             reader_input rst_name
         end
         # Declares the address counter.
+        awidth = (size-1).width
+        awidth = 1 if awidth == 0
         [size.width-1].inner :abus_r
         reader_inout :abus_r
 
@@ -876,7 +981,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     blk.call if blk
                     # Prepare the next read.
-                    abus_r <= abus_r + 1
+                    # abus_r <= abus_r + 1
+                    if 2**size.width != size then
+                        abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
+                    else
+                        abus_r <= abus_r + 1
+                    end
                 end
             end
         end
@@ -915,7 +1025,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     blk.call if blk
                     # Prepare the next write.
-                    abus_w <= abus_w + 1
+                    # abus_w <= abus_w + 1
+                    if 2**size.width != size then
+                        abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
+                    else
+                        abus_w <= abus_w + 1
+                    end
                 end
             end
         end
@@ -933,6 +1048,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             reader_input rst_name
         end
         # Declares the address counter.
+        awidth = (size-1).width
+        awidth = 1 if awidth == 0
         [size.width-1].inner :abus_r
         reader_inout :abus_r
 
@@ -956,7 +1073,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     blk.call if blk
                     # Prepare the next read.
-                    abus_r <= abus_r - 1
+                    # abus_r <= abus_r - 1
+                    if 2**size.width != size then
+                        abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
+                    else
+                        abus_r <= abus_r - 1
+                    end
                 end
             end
         end
@@ -995,7 +1117,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
                     end
                     blk.call if blk
                     # Prepare the next write.
-                    abus_w <= abus_w - 1
+                    # abus_w <= abus_w - 1
+                    if 2**size.width != size then
+                        abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
+                    else
+                        abus_w <= abus_w - 1
+                    end
                 end
             end
         end
@@ -1043,7 +1170,9 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
     size = size.to_i
     # Compute the address bus width from the size.
     awidth = (size*nbanks-1).width
+    awidth = 1 if awidth == 0
     awidth_b = (size-1).width # Bank width
+    awidth_b = 1 if awidth_b == 0
     # Ensures br_srts is a hash.
     br_rsts = br_rsts.to_hash
 
@@ -1204,7 +1333,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                         blk.call if blk
                     end
                     # Prepare the read.
-                    abus_r <= abus_r + 1
+                    # abus_r <= abus_r + 1
+                    if 2**size.width != size then
+                        abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
+                    else
+                        abus_r <= abus_r + 1
+                    end
                     trig_r <= 1
                 end
             end
@@ -1240,7 +1374,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                     # No reset, so can perform the write.
                     blk.call if blk
                     # Prepare the write.
-                    abus_w <= abus_w + 1
+                    # abus_w <= abus_w + 1
+                    if 2**size.width != size then
+                        abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
+                    else
+                        abus_w <= abus_w + 1
+                    end
                     trig_w <= 1
                     dbus_w <= target
                 end
@@ -1281,7 +1420,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                         blk.call if blk
                     end
                     # Prepare the read.
-                    abus_r <= abus_r - 1
+                    # abus_r <= abus_r - 1
+                    if 2**size.width != size then
+                        abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
+                    else
+                        abus_r <= abus_r - 1
+                    end
                     trig_r <= 1
                 end
             end
@@ -1318,6 +1462,11 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
                     blk.call if blk
                     # Prepare the write.
                     abus_w <= abus_w - 1
+                    if 2**size.width != size then
+                        abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
+                    else
+                        abus_w <= abus_w - 1
+                    end
                     trig_w <= 1
                     dbus_w <= target
                 end

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.4.1"
+  VERSION = "2.4.11"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.4.1
+  version: 2.4.11
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-09-24 00:00:00.000000000 Z
+date: 2020-10-19 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -75,6 +75,7 @@ files:
 - lib/HDLRuby/hdr_samples/addsub.rb
 - lib/HDLRuby/hdr_samples/addsubz.rb
 - lib/HDLRuby/hdr_samples/alu.rb
+- lib/HDLRuby/hdr_samples/bstr_bench.rb
 - lib/HDLRuby/hdr_samples/calculator.rb
 - lib/HDLRuby/hdr_samples/counter_bench.rb
 - lib/HDLRuby/hdr_samples/dff.rb
@@ -88,6 +89,7 @@ files:
 - lib/HDLRuby/hdr_samples/memory_test.rb
 - lib/HDLRuby/hdr_samples/multer_gen.rb
 - lib/HDLRuby/hdr_samples/multer_seq.rb
+- lib/HDLRuby/hdr_samples/neg_arith_bench.rb
 - lib/HDLRuby/hdr_samples/neural/a.rb
 - lib/HDLRuby/hdr_samples/neural/a_sub.rb
 - lib/HDLRuby/hdr_samples/neural/bw.rb
@@ -123,6 +125,7 @@ files:
 - lib/HDLRuby/hdr_samples/with_linear.rb
 - lib/HDLRuby/hdr_samples/with_loop.rb
 - lib/HDLRuby/hdr_samples/with_memory.rb
+- lib/HDLRuby/hdr_samples/with_memory_rom.rb
 - lib/HDLRuby/hdr_samples/with_multi_channels.rb
 - lib/HDLRuby/hdr_samples/with_reconf.rb
 - lib/HDLRuby/hdrcc.rb