HDLRuby 2.4.1 → 2.4.11
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- checksums.yaml +4 -4
- data/lib/HDLRuby/hdr_samples/bstr_bench.rb +14 -0
- data/lib/HDLRuby/hdr_samples/neg_arith_bench.rb +49 -0
- data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +18 -0
- data/lib/HDLRuby/hdr_samples/with_memory_rom.rb +53 -0
- data/lib/HDLRuby/hdr_samples/with_multi_channels.rb +22 -12
- data/lib/HDLRuby/hruby_bstr.rb +7 -2
- data/lib/HDLRuby/hruby_low2c.rb +21 -4
- data/lib/HDLRuby/sim/hruby_sim.h +12 -7
- data/lib/HDLRuby/sim/hruby_sim_calc.c +20 -5
- data/lib/HDLRuby/sim/hruby_sim_core.c +3 -0
- data/lib/HDLRuby/sim/hruby_sim_vcd.c +191 -26
- data/lib/HDLRuby/std/fixpoint.rb +10 -2
- data/lib/HDLRuby/std/linear.rb +19 -7
- data/lib/HDLRuby/std/memory.rb +178 -29
- data/lib/HDLRuby/version.rb +1 -1
- metadata +5 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: cbfb36d00f3809e50b2470308d24b09b413918ee4a78ab5f6cfc85c16af8ff50
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data.tar.gz: e2883c6628972cb353fcf7438f1af07ba2c6700c4fdbddcf26ba9b3a00a5cdec
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SHA512:
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-
metadata.gz:
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-
data.tar.gz:
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metadata.gz: 2fa905701cad381e3d352524b1fd85f21ee3340e0eaa2b7d5579b93c6126d302bc35e407d10561a2e81a70b94137dda0a6398a49de1790fddeba1434a99ba467
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7
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+
data.tar.gz: 5d04403133e3ed080eef1f4494bcfc7694bcdd66ccace555361383c9f15a83c71f1994826171c4eaf5c20d5f059b9148c2e5cdfce7ba3d4b08691e57abf09395
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@@ -0,0 +1,49 @@
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2
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# A benchmark for testing the arithmetic with signed values.
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3
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system :neg_arith_bench do
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4
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signed[11..0].inner :x,:y,:z
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5
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6
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timed do
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7
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x <= 10
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8
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y <= 10
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9
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z <= 0
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10
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+
!10.ns
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11
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z <= 10 * 10
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12
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!10.ns
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13
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z <= x * y
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14
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!10.ns
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15
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x <= 10
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16
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y <= -10
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17
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+
!10.ns
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18
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z <= 10 * (-10)
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19
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+
!10.ns
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20
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+
z <= x * y
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21
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+
!10.ns
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22
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x <= -10
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23
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y <= 10
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24
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!10.ns
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25
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z <= (-10) * 10
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26
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+
!10.ns
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27
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z <= x * y
|
28
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+
!10.ns
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29
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x <= -10
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30
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y <= -10
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31
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!10.ns
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32
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z <= (-10) * (-10)
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33
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+
!10.ns
|
34
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z <= x * y
|
35
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+
!10.ns
|
36
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+
x <= _000000011010
|
37
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y <= _000011111010
|
38
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z <= 0
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39
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+
!10.ns
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40
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z <= x * y
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41
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!10.ns
|
42
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x <= _000000011010
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43
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y <= _111111111010
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44
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z <= 0
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45
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!10.ns
|
46
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z <= x * y
|
47
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+
!10.ns
|
48
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+
end
|
49
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+
end
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@@ -31,5 +31,23 @@ system :fix_test do
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31
31
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d <= 0
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32
32
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!10.ns
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33
33
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d <= d + c
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34
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!10.ns
|
35
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a <= -0.375.to_fix(4)
|
36
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b <= 1.625.to_fix(4)
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!10.ns
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c <= a * b
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!10.ns
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# a <= _00010000
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# b <= _00010101
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a <= _0000111x
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b <= _1110011x
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!10.ns
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# a <= a & _11111110
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# b <= b | _00000001
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a <= a | _00000001
|
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b <= b | _00000001
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49
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!10.ns
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c <= a * b
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!10.ns
|
34
52
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end
|
35
53
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end
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@@ -0,0 +1,53 @@
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1
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+
require 'std/memory.rb'
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2
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|
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include HDLRuby::High::Std
|
4
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6
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|
7
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|
8
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|
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# A system testing the rom channel.
|
10
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system :rorm_test do
|
11
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inner :clk,:rst
|
12
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[8].inner :value
|
13
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inner :addr
|
14
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+
|
15
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# Declares a 8-bit-data and 1 element rom address synchronous memory
|
16
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+
# on negative edge of clk.
|
17
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+
# mem_rom([8],2,clk,rst,[_00000110,_00000111], rinc: :rst).(:romI)
|
18
|
+
mem_rom([8],1,clk,rst,[_00000110], rinc: :rst).(:romI)
|
19
|
+
rd = romI.branch(:rinc)
|
20
|
+
|
21
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+
par(clk.posedge) do
|
22
|
+
hif(rst) { addr <= 0 }
|
23
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+
helse do
|
24
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+
rd.read(value)
|
25
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+
end
|
26
|
+
end
|
27
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+
|
28
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timed do
|
29
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clk <= 0
|
30
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rst <= 0
|
31
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+
!10.ns
|
32
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clk <= 1
|
33
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+
!10.ns
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34
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+
clk <= 0
|
35
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rst <= 1
|
36
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+
!10.ns
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37
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+
clk <= 1
|
38
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+
!10.ns
|
39
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clk <= 0
|
40
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+
!10.ns
|
41
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+
clk <= 1
|
42
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+
!10.ns
|
43
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+
clk <= 0
|
44
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+
rst <= 0
|
45
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+
!10.ns
|
46
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+
10.times do
|
47
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+
clk <= 1
|
48
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+
!10.ns
|
49
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+
clk <= 0
|
50
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+
!10.ns
|
51
|
+
end
|
52
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+
end
|
53
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+
end
|
@@ -135,7 +135,7 @@ channel(:handshake) do |typ|
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|
135
135
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# The data signal.
|
136
136
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typ.inner :data
|
137
137
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# The request and acknowledge.
|
138
|
-
|
138
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+
inner :req, :ack
|
139
139
|
|
140
140
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reader_input :ack, :data
|
141
141
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reader_output :req
|
@@ -174,13 +174,22 @@ channel(:handshake) do |typ|
|
|
174
174
|
end
|
175
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|
176
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|
177
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-
$mode = :prodcons
|
178
177
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# $mode = :sync
|
179
178
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# $mode = :nsync
|
180
179
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# $mode = :async
|
180
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+
# $mode = :proco # Producter / Consummer
|
181
181
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# $channel = :register
|
182
182
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# $channel = :handshake
|
183
|
-
$channel = :queue
|
183
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+
# $channel = :queue
|
184
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+
|
185
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+
# The configuration scenarii
|
186
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+
$scenarii = [ [:sync, :register], [:sync, :handshake], [:sync, :queue],
|
187
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+
[:nsync, :register], [:nsync, :handshake], [:nsync, :queue],
|
188
|
+
[:async, :register], [:async, :handshake], [:async, :queue],
|
189
|
+
[:proco, :register], [:proco, :handshake], [:proco, :queue] ]
|
190
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+
|
191
|
+
# The configuration
|
192
|
+
$mode, $channel = $scenarii[11]
|
184
193
|
|
185
194
|
# Testing the queue channel.
|
186
195
|
system :test_queue do
|
@@ -199,7 +208,7 @@ system :test_queue do
|
|
199
208
|
ev = $mode == :sync ? clk.posedge :
|
200
209
|
$mode == :nsync ? clk.negedge : clk2.posedge
|
201
210
|
|
202
|
-
if $mode != :
|
211
|
+
if $mode != :proco then
|
203
212
|
# Sync/Neg sync and async tests mode
|
204
213
|
par(ev) do
|
205
214
|
hif(rst) do
|
@@ -263,27 +272,28 @@ system :test_queue do
|
|
263
272
|
rst <= 1
|
264
273
|
!3.ns
|
265
274
|
clk2 <= 1
|
266
|
-
!
|
267
|
-
clk3 <=
|
268
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-
!
|
275
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+
!3.ns
|
276
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+
clk3 <= 0
|
277
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+
!4.ns
|
269
278
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clk <= 1
|
270
279
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!10.ns
|
271
280
|
clk <= 0
|
272
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-
rst <= 0
|
273
281
|
!3.ns
|
274
282
|
clk2 <= 0
|
275
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-
!
|
283
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+
!3.ns
|
276
284
|
clk3 <= 1
|
277
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-
!
|
285
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+
!2.ns
|
286
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+
rst <= 0
|
287
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+
!2.ns
|
278
288
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64.times do
|
279
289
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clk <= 1
|
280
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!10.ns
|
281
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clk <= 0
|
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!3.ns
|
283
293
|
clk2 <= ~clk2
|
284
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-
!
|
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+
!3.ns
|
285
295
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hif (clk2 == 0) { clk3 <= ~ clk3 }
|
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-
!
|
296
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+
!4.ns
|
287
297
|
end
|
288
298
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end
|
289
299
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end
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data/lib/HDLRuby/hruby_bstr.rb
CHANGED
@@ -32,13 +32,17 @@ module HDLRuby
|
|
32
32
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# and negative when "1".
|
33
33
|
# * when not present it is assumed to be within str.
|
34
34
|
def initialize(str,sign = nil)
|
35
|
+
# puts "str=#{str}"
|
35
36
|
# Maybe str is an numeric.
|
36
37
|
if str.is_a?(Numeric) then
|
37
38
|
# Yes, convert it to a binary string.
|
38
|
-
|
39
|
+
num = str
|
40
|
+
str = num.to_s(2)
|
39
41
|
# And fix the sign.
|
40
42
|
if str[0] == "-" then
|
41
|
-
str = str[1..-1]
|
43
|
+
# str = str[1..-1]
|
44
|
+
str = (2**str.size+num).to_s(2)
|
45
|
+
puts "str=#{str}"
|
42
46
|
sign = "-"
|
43
47
|
else
|
44
48
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sign = "+"
|
@@ -71,6 +75,7 @@ module HDLRuby
|
|
71
75
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end.reverse.join
|
72
76
|
end
|
73
77
|
@str += str.to_s.downcase
|
78
|
+
# puts "@str=#{@str}"
|
74
79
|
unless @str.match(/^[0-1zx]+$/) then
|
75
80
|
raise "Invalid value for creating a bit string: #{str}"
|
76
81
|
end
|
data/lib/HDLRuby/hruby_low2c.rb
CHANGED
@@ -111,6 +111,8 @@ module HDLRuby::Low
|
|
111
111
|
res << "int main(int argc, char* argv[]) {\n"
|
112
112
|
# Build the objects.
|
113
113
|
objs.each { |obj| res << " #{Low2C.make_name(obj)}();\n" }
|
114
|
+
# Sets the top systemT.
|
115
|
+
res << " top_system = #{Low2C.obj_name(top)};\n"
|
114
116
|
# Starts the simulation.
|
115
117
|
res<< " hruby_sim_core(\"#{name}\",#{init_visualizer},-1);\n"
|
116
118
|
# Close the main.
|
@@ -1329,6 +1331,10 @@ module HDLRuby::Low
|
|
1329
1331
|
res << "block->owner = NULL;\n"
|
1330
1332
|
end
|
1331
1333
|
|
1334
|
+
# The name
|
1335
|
+
res << " " * (level+1)*3
|
1336
|
+
res << "block->name = \"#{self.name}\";\n"
|
1337
|
+
|
1332
1338
|
# Add the inner signals declaration.
|
1333
1339
|
res << " " * (level+1)*3
|
1334
1340
|
res << "block->num_inners = #{self.each_inner.to_a.size};\n"
|
@@ -1439,8 +1445,18 @@ module HDLRuby::Low
|
|
1439
1445
|
str = self.content.is_a?(BitString) ?
|
1440
1446
|
self.content.to_s : self.content.to_s(2).rjust(32,"0")
|
1441
1447
|
else
|
1442
|
-
sign = self.content>=0 ? "0" : "1"
|
1443
|
-
str = self.content.abs.to_s(2).rjust(width,sign).upcase
|
1448
|
+
# sign = self.content>=0 ? "0" : "1"
|
1449
|
+
# str = self.content.abs.to_s(2).rjust(width,sign).upcase
|
1450
|
+
if self.content >= 0 then
|
1451
|
+
str = self.content.to_s(2).rjust(width,"0").upcase
|
1452
|
+
else
|
1453
|
+
# Compute the extension to the next multiple
|
1454
|
+
# of int_width
|
1455
|
+
ext_width = (((width-1) / Low2C.int_width)+1)*Low2C.int_width
|
1456
|
+
# Convert the string.
|
1457
|
+
str = (2**ext_width+self.content).to_s(2).upcase
|
1458
|
+
end
|
1459
|
+
# puts "content=#{self.content} str=#{str}"
|
1444
1460
|
end
|
1445
1461
|
# Is it a fully defined number?
|
1446
1462
|
if str =~ /^[01]+$/ then
|
@@ -1453,13 +1469,14 @@ module HDLRuby::Low
|
|
1453
1469
|
res << " };\n"
|
1454
1470
|
# Create the value.
|
1455
1471
|
res << " " * (level+1)*3
|
1456
|
-
# puts "str=#{str} type width=#{self.type.width}"
|
1472
|
+
# puts "str=#{str} type width=#{self.type.width} signed? #{type.signed?}"
|
1457
1473
|
res << "return make_set_value(#{self.type.to_c(level+1)},1," +
|
1458
1474
|
"data);\n"
|
1459
1475
|
else
|
1460
1476
|
# No, generate a bit string value.
|
1461
1477
|
res << " " * (level+1)*3
|
1462
|
-
res << "static unsigned char data[] = \"#{str}\";\n"
|
1478
|
+
# res << "static unsigned char data[] = \"#{str}\";\n"
|
1479
|
+
res << "static unsigned char data[] = \"#{str.reverse}\";\n"
|
1463
1480
|
# Create the value.
|
1464
1481
|
res << " " * (level+1)*3
|
1465
1482
|
res << "return make_set_value(#{self.type.to_c(level+1)},0," +
|
data/lib/HDLRuby/sim/hruby_sim.h
CHANGED
@@ -50,8 +50,9 @@ typedef enum {
|
|
50
50
|
|
51
51
|
/* The interface to the type engine. */
|
52
52
|
typedef struct FlagsS_ {
|
53
|
-
unsigned int all;
|
54
|
-
unsigned int sign : 1; /* Tells if the type is signed or not. */
|
53
|
+
// unsigned int all;
|
54
|
+
// unsigned int sign : 1; /* Tells if the type is signed or not. */
|
55
|
+
unsigned int sign; /* Tells if the type is signed or not. */
|
55
56
|
} FlagsS;
|
56
57
|
|
57
58
|
/** The type structure. */
|
@@ -474,6 +475,7 @@ typedef struct BlockS_ {
|
|
474
475
|
Kind kind; /* The kind of object. */
|
475
476
|
Object owner; /* The owner if any. */
|
476
477
|
|
478
|
+
char* name; /* The name of the block. */
|
477
479
|
int num_inners; /* The number of inners. */
|
478
480
|
SignalI* inners; /* The inners of the scope. */
|
479
481
|
void (*function)(); /* The function to execute for the block. */
|
@@ -496,6 +498,9 @@ typedef struct EventS_ {
|
|
496
498
|
/* The time units. */
|
497
499
|
typedef enum { S, MS, US, NS, PS, FS } Unit;
|
498
500
|
|
501
|
+
/** The top system. */
|
502
|
+
extern SystemT top_system;
|
503
|
+
|
499
504
|
/** Adds a timed behavior for processing.
|
500
505
|
* @param behavior the timed behavior to register */
|
501
506
|
extern void register_timed_behavior(Behavior behavior);
|
@@ -574,17 +579,17 @@ typedef struct {
|
|
574
579
|
void (*print_signal)(SignalI);
|
575
580
|
} PrinterS;
|
576
581
|
|
577
|
-
PrinterS printer;
|
582
|
+
extern PrinterS printer;
|
578
583
|
|
579
584
|
/** Initializes the visualization printer engine.
|
580
585
|
* @param print_time the time printer
|
581
586
|
* @param print_name the name printer
|
582
587
|
* @param print_value the value printer
|
583
588
|
* @param print_signal the signal state printer. */
|
584
|
-
void init_visualizer(void (*print_time)(unsigned long long),
|
585
|
-
|
586
|
-
|
587
|
-
|
589
|
+
extern void init_visualizer(void (*print_time)(unsigned long long),
|
590
|
+
void (*print_name)(Object),
|
591
|
+
void (*print_value)(Value),
|
592
|
+
void (*print_signal)(SignalI));
|
588
593
|
|
589
594
|
// /** Prints the time.
|
590
595
|
// * @param time the time to show. */
|
@@ -70,7 +70,8 @@ static List hash_type[HASH_TYPE_SIZE] = {};
|
|
70
70
|
* @return the resulting type. */
|
71
71
|
static int hash_value(unsigned long long base, unsigned long long number,
|
72
72
|
FlagsS flags) {
|
73
|
-
return ((base+flags.all)^(number)) & 1023;
|
73
|
+
// return ((base+flags.all)^(number)) & 1023;
|
74
|
+
return ((base+flags.sign)^(number)) & 1023;
|
74
75
|
}
|
75
76
|
|
76
77
|
/** Adds a type to the hash of types.
|
@@ -109,7 +110,8 @@ static Type get_hash_type(Type base, unsigned long long number) {
|
|
109
110
|
while(elem) {
|
110
111
|
Type type = elem->data;
|
111
112
|
if ((type->base == bw) && (type->number == number) &&
|
112
|
-
(type->flags.all == flags.all)) {
|
113
|
+
// (type->flags.all == flags.all)) {
|
114
|
+
(type->flags.sign == flags.sign)) {
|
113
115
|
/* The type is found. */
|
114
116
|
return type;
|
115
117
|
}
|
@@ -243,8 +245,10 @@ void resize_value(Value value, int size) {
|
|
243
245
|
void set_value(Value value, int numeric, void* data) {
|
244
246
|
value->numeric = numeric;
|
245
247
|
if (numeric) {
|
248
|
+
// printf("set_value with data=%llx\n",*(unsigned long long*)data);
|
246
249
|
value->data_int = *((unsigned long long*)data);
|
247
250
|
} else {
|
251
|
+
// printf("data=%s\n",(char*)data);
|
248
252
|
memcpy(value->data_str,data,type_width(value->type)*sizeof(char));
|
249
253
|
}
|
250
254
|
}
|
@@ -254,6 +258,7 @@ void set_value(Value value, int numeric, void* data) {
|
|
254
258
|
* @param numeric tell if the value is in numeric form or in bitstring form
|
255
259
|
* @param data the source data */
|
256
260
|
Value make_set_value(Type type, int numeric, void* data) {
|
261
|
+
// printf("make_set_value with type->flags.sign=%x\n",type->flags.sign);
|
257
262
|
Value value = make_value(type,numeric);
|
258
263
|
set_value(value,numeric,data);
|
259
264
|
return value;
|
@@ -307,6 +312,7 @@ Value copy_value(Value src, Value dst) {
|
|
307
312
|
/* Numeric copy. */
|
308
313
|
dst->data_int = fix_numeric_type(dst->type,src->data_int);
|
309
314
|
} else {
|
315
|
+
// printf("copy_value with bit string: %s\n",src->data_str);
|
310
316
|
/* Resize the destination if required. */
|
311
317
|
resize_value(dst,type_width(dst->type));
|
312
318
|
/* Bitstring copy up to the end of dst or src. */
|
@@ -603,12 +609,14 @@ static Value sub_value_bitstring(Value src0, Value src1, Value dst) {
|
|
603
609
|
* @param dst the destination value
|
604
610
|
* @return dst */
|
605
611
|
static Value mul_value_defined_bitstring(Value src0, Value src1, Value dst) {
|
612
|
+
// printf("mul_value_defined_bitstring with src0=%llx src1=%llx\n",value2integer(src0),value2integer(src1));
|
606
613
|
/* Sets state of the destination using the first source. */
|
607
614
|
dst->type = src0->type;
|
608
615
|
dst->numeric = 1;
|
609
616
|
|
610
617
|
/* Perform the multiplication. */
|
611
618
|
dst->data_int = value2integer(src0) * value2integer(src1);
|
619
|
+
// printf("dst->data_int=%llx\n",dst->data_int);
|
612
620
|
return dst;
|
613
621
|
}
|
614
622
|
|
@@ -1172,7 +1180,7 @@ static Value equal_value_bitstring(Value src0, Value src1, Value dst) {
|
|
1172
1180
|
static Value select_value_bitstring(Value cond, Value dst, unsigned int num,
|
1173
1181
|
va_list args)
|
1174
1182
|
{
|
1175
|
-
printf("select_value_bitstring with cond=%s\n",cond->data_str);
|
1183
|
+
// printf("select_value_bitstring with cond=%s\n",cond->data_str);
|
1176
1184
|
/* Get the first alternative for sizing the result. */
|
1177
1185
|
Value src = va_arg(args,Value);
|
1178
1186
|
/* Compute the width of the result in bits. */
|
@@ -1556,6 +1564,7 @@ static Value sub_value_numeric(Value src0, Value src1, Value dst) {
|
|
1556
1564
|
* @param dst the destination value
|
1557
1565
|
* @return dst */
|
1558
1566
|
static Value mul_value_numeric(Value src0, Value src1, Value dst) {
|
1567
|
+
// printf("mul_value_numeric with src0->data_int=%llx src1->data_int=%llx\n",src0->data_int, src1->data_int);
|
1559
1568
|
/* Sets state of the destination using the first source. */
|
1560
1569
|
dst->type = src0->type;
|
1561
1570
|
dst->numeric = 1;
|
@@ -1823,7 +1832,7 @@ static Value concat_value_numeric_array(int num, int dir,
|
|
1823
1832
|
* @param dst the destination value
|
1824
1833
|
* @return dst */
|
1825
1834
|
static Value cast_value_numeric(Value src, Type type, Value dst) {
|
1826
|
-
// printf("cast_value_numeric with src=%llx",src->data_int);
|
1835
|
+
// printf("cast_value_numeric with src=%llx\n",src->data_int);
|
1827
1836
|
/* Copy the source to the destination. */
|
1828
1837
|
dst->data_int = src->data_int;
|
1829
1838
|
/* Update the destination type to the cast. */
|
@@ -2665,6 +2674,7 @@ unsigned long long value2integer(Value value) {
|
|
2665
2674
|
char bit;
|
2666
2675
|
/* Access the bitstring data. */
|
2667
2676
|
char* data_str = value->data_str;
|
2677
|
+
// printf("value2integer with data_str=%s\n",data_str);
|
2668
2678
|
/* Copy the bits. */
|
2669
2679
|
for (i=0; i<width && i<LONG_LONG_BIT; ++i) {
|
2670
2680
|
/* Get the bit. */
|
@@ -2676,12 +2686,17 @@ unsigned long long value2integer(Value value) {
|
|
2676
2686
|
/* Write the bit. */
|
2677
2687
|
res = (res << 1) | bit;
|
2678
2688
|
}
|
2689
|
+
// printf("first res=%llx\n",res);
|
2690
|
+
unsigned long long bit0 = (data_str[width-1]-'0') << i;
|
2679
2691
|
/* Perform the sign extension if required. */
|
2680
2692
|
if (i>=width && value->type->flags.sign) {
|
2681
2693
|
for(; i<LONG_LONG_BIT; ++i) {
|
2682
|
-
res = (res << 1) | bit;
|
2694
|
+
// res = (res << 1) | bit;
|
2695
|
+
res |= bit0;
|
2696
|
+
bit0 <<= 1;
|
2683
2697
|
}
|
2684
2698
|
}
|
2699
|
+
// printf("then res=%llx\n",res);
|
2685
2700
|
return res;
|
2686
2701
|
}
|
2687
2702
|
|
@@ -64,35 +64,49 @@ static void vcd_print_time(unsigned long long time) {
|
|
64
64
|
}
|
65
65
|
|
66
66
|
|
67
|
-
/** Prints the name of an object.
|
67
|
+
/** Prints the name of an object without its hierarchy.
|
68
68
|
* @param object the object to print the name. */
|
69
69
|
static void vcd_print_name(Object object) {
|
70
|
-
/* Recurse on the owner if any. */
|
71
|
-
// printf("owner=%p\n",object->owner);
|
72
|
-
if (object->owner != NULL) {
|
73
|
-
vcd_print_name(object->owner);
|
74
|
-
vcd_print("$");
|
75
|
-
}
|
76
70
|
/* Depending on the kind of object. */
|
77
71
|
switch(object->kind) {
|
78
72
|
case SYSTEMT:
|
79
73
|
case SIGNALI:
|
80
74
|
case SCOPE:
|
81
75
|
case SYSTEMI:
|
76
|
+
case BLOCK:
|
82
77
|
/* Print the name if name. */
|
83
78
|
/* Trick: SystemT, SignalI, Scope and SystemI have the
|
84
79
|
* field name at the same place. */
|
85
|
-
if (((
|
80
|
+
if ((((Block)object)->name != NULL) &&
|
81
|
+
strlen(((Block)object)->name)>0) {
|
86
82
|
char name[256];
|
87
|
-
strncpy(name,((
|
83
|
+
strncpy(name,((Block)object)->name,256);
|
88
84
|
replace_char(name,':','$');
|
89
85
|
vcd_print("%s",name);
|
86
|
+
} else {
|
87
|
+
/* No name, use the address of the object as name generator.*/
|
88
|
+
vcd_print("$%p",(void*)object);
|
90
89
|
}
|
90
|
+
break;
|
91
91
|
default: /* Nothing to do */
|
92
92
|
break;
|
93
93
|
}
|
94
94
|
}
|
95
95
|
|
96
|
+
|
97
|
+
/** Prints the name of an object incluing its heirarchy.
|
98
|
+
* @param object the object to print the name. */
|
99
|
+
static void vcd_print_full_name(Object object) {
|
100
|
+
/* Recurse on the owner if any. */
|
101
|
+
// printf("owner=%p\n",object->owner);
|
102
|
+
if (object->owner != NULL) {
|
103
|
+
vcd_print_full_name(object->owner);
|
104
|
+
vcd_print("$");
|
105
|
+
}
|
106
|
+
/* Print the name of the object. */
|
107
|
+
vcd_print_name(object);
|
108
|
+
}
|
109
|
+
|
96
110
|
/** Prints a value.
|
97
111
|
* @param value the value to print */
|
98
112
|
static void vcd_print_value(Value value) {
|
@@ -127,23 +141,169 @@ static void vcd_print_value(Value value) {
|
|
127
141
|
* @param signal the signal to declare */
|
128
142
|
static void vcd_print_var(SignalI signal) {
|
129
143
|
vcd_print("$var wire %d ",type_width(signal->type));
|
130
|
-
|
144
|
+
vcd_print_full_name((Object)signal);
|
131
145
|
vcd_print(" ");
|
132
146
|
vcd_print_name((Object)signal);
|
133
147
|
vcd_print(" $end\n");
|
134
148
|
}
|
135
149
|
|
136
150
|
|
137
|
-
/** Prints a signal.
|
151
|
+
/** Prints a signal with its future value if any.
|
138
152
|
* @param signal the signal to show */
|
139
|
-
static void
|
140
|
-
|
141
|
-
|
142
|
-
|
143
|
-
|
153
|
+
static void vcd_print_signal_fvalue(SignalI signal) {
|
154
|
+
if (signal->f_value) {
|
155
|
+
vcd_print_value(signal->f_value);
|
156
|
+
vcd_print(" ");
|
157
|
+
vcd_print_full_name((Object)signal);
|
158
|
+
vcd_print("\n");
|
159
|
+
}
|
160
|
+
}
|
161
|
+
|
162
|
+
|
163
|
+
/** Prints a signal with its current value if any
|
164
|
+
* @param signal the signal to show */
|
165
|
+
static void vcd_print_signal_cvalue(SignalI signal) {
|
166
|
+
if (signal->c_value) {
|
167
|
+
vcd_print_value(signal->c_value);
|
168
|
+
vcd_print(" ");
|
169
|
+
vcd_print_full_name((Object)signal);
|
170
|
+
vcd_print("\n");
|
171
|
+
}
|
172
|
+
}
|
173
|
+
|
174
|
+
|
175
|
+
/** Prints the hierarchy content of a system type.
|
176
|
+
* @param system the system to print. */
|
177
|
+
static void vcd_print_systemT_content(SystemT system);
|
178
|
+
|
179
|
+
/** Prints the hierarchy of a scope.
|
180
|
+
* @param scope the scope to print. */
|
181
|
+
static void vcd_print_scope(Scope scope);
|
182
|
+
|
183
|
+
|
184
|
+
/** Prints the hierarchy of a block.
|
185
|
+
* @param block the block to print. */
|
186
|
+
static void vcd_print_block(Block block) {
|
187
|
+
int i;
|
188
|
+
/* Do not print block with no declaration. */
|
189
|
+
if (block->num_inners == 0) return;
|
190
|
+
|
191
|
+
/* Declares the block if named. */
|
192
|
+
vcd_print("$scope module ");
|
193
|
+
vcd_print_name((Object)block);
|
194
|
+
vcd_print(" $end\n");
|
195
|
+
|
196
|
+
/* Declare the inners of the systems. */
|
197
|
+
for(i=0; i<block->num_inners; ++i) {
|
198
|
+
vcd_print_var(block->inners[i]);
|
199
|
+
}
|
200
|
+
|
201
|
+
/* Close the hierarchy. */
|
202
|
+
vcd_print("$upscope $end\n");
|
144
203
|
}
|
145
204
|
|
146
205
|
|
206
|
+
/** Prints the hierarchy of a system instances.
|
207
|
+
* @param scope the scope to print. */
|
208
|
+
static void vcd_print_systemI(SystemI systemI) {
|
209
|
+
/* Declares the systemI. */
|
210
|
+
vcd_print("$scope module ");
|
211
|
+
vcd_print_name((Object)systemI);
|
212
|
+
vcd_print(" $end\n");
|
213
|
+
|
214
|
+
/* Declares its content. */
|
215
|
+
vcd_print_systemT_content(systemI->system);
|
216
|
+
|
217
|
+
/* Close the hierarchy. */
|
218
|
+
vcd_print("$upscope $end\n");
|
219
|
+
}
|
220
|
+
|
221
|
+
|
222
|
+
/** Prints the hierarchy inside a scope.
|
223
|
+
* @param scope the scope to print the inside. */
|
224
|
+
static void vcd_print_scope_content(Scope scope) {
|
225
|
+
int i;
|
226
|
+
|
227
|
+
/* Declare the inners of the systems. */
|
228
|
+
for(i=0; i<scope->num_inners; ++i) {
|
229
|
+
vcd_print_var(scope->inners[i]);
|
230
|
+
}
|
231
|
+
|
232
|
+
/* Recurse on the system instances. */
|
233
|
+
for(i=0; i<scope->num_systemIs; ++i) {
|
234
|
+
vcd_print_systemI(scope->systemIs[i]);
|
235
|
+
}
|
236
|
+
|
237
|
+
/* Recurse on the sub scopes. */
|
238
|
+
for(i=0; i<scope->num_scopes; ++i) {
|
239
|
+
vcd_print_scope(scope->scopes[i]);
|
240
|
+
}
|
241
|
+
|
242
|
+
/* Recurse on the behaviors. */
|
243
|
+
for(i=0; i<scope->num_behaviors; ++i) {
|
244
|
+
vcd_print_block(scope->behaviors[i]->block);
|
245
|
+
}
|
246
|
+
}
|
247
|
+
|
248
|
+
|
249
|
+
/** Prints the hierarchy of a scope.
|
250
|
+
* @param scope the scope to print. */
|
251
|
+
static void vcd_print_scope(Scope scope) {
|
252
|
+
/* Do not print block with no declaration. */
|
253
|
+
if (scope->num_inners == 0 && scope->num_scopes == 0 && scope->num_behaviors == 0) return;
|
254
|
+
/* Declares the scope. */
|
255
|
+
vcd_print("$scope module ");
|
256
|
+
vcd_print_name((Object)scope);
|
257
|
+
vcd_print(" $end\n");
|
258
|
+
|
259
|
+
/* Declares its content. */
|
260
|
+
vcd_print_scope_content(scope);
|
261
|
+
|
262
|
+
/* Close the hierarchy. */
|
263
|
+
vcd_print("$upscope $end\n");
|
264
|
+
}
|
265
|
+
|
266
|
+
|
267
|
+
/** Prints the hierarchy content of a system type.
|
268
|
+
* @param system the system to print. */
|
269
|
+
static void vcd_print_systemT_content(SystemT system) {
|
270
|
+
int i;
|
271
|
+
|
272
|
+
/* Declare the inputs of the systems. */
|
273
|
+
for(i = 0; i<system->num_inputs; ++i) {
|
274
|
+
vcd_print_var(system->inputs[i]);
|
275
|
+
}
|
276
|
+
/* Declare the outputs of the systems. */
|
277
|
+
for(i = 0; i<system->num_outputs; ++i) {
|
278
|
+
vcd_print_var(system->outputs[i]);
|
279
|
+
}
|
280
|
+
/* Declare the inouts of the systems. */
|
281
|
+
for(i = 0; i<system->num_inouts; ++i) {
|
282
|
+
vcd_print_var(system->inouts[i]);
|
283
|
+
}
|
284
|
+
/* Recurse on the content of the scope (the scope header is the system).*/
|
285
|
+
vcd_print_scope_content(system->scope);
|
286
|
+
}
|
287
|
+
|
288
|
+
|
289
|
+
/** Prints the hierarchy of a system type.
|
290
|
+
* @param system the system to print. */
|
291
|
+
static void vcd_print_systemT(SystemT system) {
|
292
|
+
int i;
|
293
|
+
/* Declares the module. */
|
294
|
+
vcd_print("$scope module ");
|
295
|
+
vcd_print_name((Object)system);
|
296
|
+
vcd_print(" $end\n");
|
297
|
+
|
298
|
+
/* Declares the content. */
|
299
|
+
vcd_print_systemT_content(system);
|
300
|
+
|
301
|
+
/* Close the hierarchy. */
|
302
|
+
vcd_print("$upscope $end\n");
|
303
|
+
}
|
304
|
+
|
305
|
+
|
306
|
+
|
147
307
|
|
148
308
|
|
149
309
|
/* high-end print functions. */
|
@@ -164,7 +324,7 @@ static void vcd_print_header() {
|
|
164
324
|
/* The version section. */
|
165
325
|
vcd_print("$version\n");
|
166
326
|
vcd_print(" Generated from HDLRuby simulator\n");
|
167
|
-
vcd_print("$end");
|
327
|
+
vcd_print("$end\n");
|
168
328
|
|
169
329
|
/* The comment section. */
|
170
330
|
vcd_print("$comment\n");
|
@@ -174,20 +334,25 @@ static void vcd_print_header() {
|
|
174
334
|
/* The time scale section: for now 1ps only. */
|
175
335
|
vcd_print("$timescale 1ps $end\n");
|
176
336
|
|
177
|
-
/* The scope section: nothing specific. */
|
178
|
-
vcd_print("$scope module logic $end\n");
|
337
|
+
// /* The scope section: nothing specific. */
|
338
|
+
// vcd_print("$scope module logic $end\n");
|
179
339
|
|
180
|
-
/* The variables declaration. */
|
181
|
-
each_all_signal(&vcd_print_var);
|
340
|
+
// /* The variables declaration. */
|
341
|
+
// each_all_signal(&vcd_print_var);
|
182
342
|
|
343
|
+
// /* Ends the declarations. */
|
344
|
+
// vcd_print("$upscope $end\n");
|
345
|
+
// vcd_print("$enddefinitions $end\n");
|
346
|
+
|
347
|
+
/* The declaration of the hierarchy and the variables
|
348
|
+
* from the top system. */
|
349
|
+
vcd_print_systemT(top_system);
|
183
350
|
/* Ends the declarations. */
|
184
|
-
vcd_print("$upscope $end\n");
|
185
351
|
vcd_print("$enddefinitions $end\n");
|
186
352
|
|
187
353
|
/* Display the initializations. */
|
188
354
|
vcd_print("$dumpvars\n");
|
189
|
-
|
190
|
-
// each_all_init_signal(&vcd_print_signal);
|
355
|
+
each_all_signal(&vcd_print_signal_cvalue);
|
191
356
|
vcd_print("$end\n");
|
192
357
|
}
|
193
358
|
|
@@ -206,9 +371,9 @@ extern void init_vcd_visualizer(char* name) {
|
|
206
371
|
|
207
372
|
/* Initialize the vizualizer printer engine. */
|
208
373
|
init_visualizer(&vcd_print_time,
|
209
|
-
&
|
374
|
+
&vcd_print_full_name,
|
210
375
|
&vcd_print_value,
|
211
|
-
&
|
376
|
+
&vcd_print_signal_fvalue);
|
212
377
|
|
213
378
|
/* Prints the header of the vcd file. */
|
214
379
|
vcd_print_header();
|
data/lib/HDLRuby/std/fixpoint.rb
CHANGED
@@ -52,10 +52,18 @@ module HDLRuby::High::Std
|
|
52
52
|
end
|
53
53
|
# Redefine the multiplication and division for fixed point.
|
54
54
|
typ.define_operator(:*) do |left,right|
|
55
|
-
(
|
55
|
+
if (typ.signed?) then
|
56
|
+
(left.as(signed[isize+fsize*2])*right) >> fsize
|
57
|
+
else
|
58
|
+
(left.as([isize+fsize*2])*right) >> fsize
|
59
|
+
end
|
56
60
|
end
|
57
61
|
typ.define_operator(:/) do |left,right|
|
58
|
-
(
|
62
|
+
if (typ.signed?) then
|
63
|
+
(left.as(signed[isize+fsize*2]) << fsize) / right
|
64
|
+
else
|
65
|
+
(left.as([isize+fsize*2]) << fsize) / right
|
66
|
+
end
|
59
67
|
end
|
60
68
|
typ
|
61
69
|
end
|
data/lib/HDLRuby/std/linear.rb
CHANGED
@@ -209,6 +209,7 @@ module HDLRuby::High::Std
|
|
209
209
|
# lv and rv are valid.
|
210
210
|
lvoks = lefts.each_with_index.map { |left,i| inner :"lvok#{i}" }
|
211
211
|
inner :rvok
|
212
|
+
woks = lefts.each_with_index.map { |left,i| inner :"wok#{i}" }
|
212
213
|
# Run flag
|
213
214
|
inner :run
|
214
215
|
par(ev) do
|
@@ -218,28 +219,39 @@ module HDLRuby::High::Std
|
|
218
219
|
rvok <= 0
|
219
220
|
lefts.each_with_index do |left,i|
|
220
221
|
lvoks[i] <= 0
|
221
|
-
#
|
222
|
-
|
222
|
+
# avs[i] <= 0
|
223
|
+
woks[i] <= 0
|
223
224
|
end
|
224
225
|
end
|
225
226
|
hif(req | run) do
|
226
227
|
run <= 1
|
227
228
|
# Computation request.
|
228
|
-
right.read(rv) { rvok <= 1 }
|
229
|
+
hif(~rvok) { right.read(rv) { rvok <= 1 } }
|
229
230
|
lefts.each_with_index do |left,i|
|
230
|
-
left.read(lvs[i]) { lvoks[i] <= 1 }
|
231
|
+
hif(~lvoks[i]) { left.read(lvs[i]) { lvoks[i] <= 1 } }
|
231
232
|
# accs[i].read(avs[i])
|
232
|
-
hif(lvoks[i] & rvok) do
|
233
|
+
hif(lvoks[i] & rvok & ~woks[i]) do
|
233
234
|
ack <= 1
|
234
235
|
run <= 0
|
235
|
-
# accs[i].write(add.(avs[i],mul.(lvs[i],rv)))
|
236
236
|
seq do
|
237
237
|
avs[i] <= add.(avs[i],mul.(lvs[i],rv))
|
238
|
-
accs[i].write(avs[i])
|
238
|
+
accs[i].write(avs[i]) do
|
239
|
+
woks[i] <= 1
|
240
|
+
# seq do
|
241
|
+
# lvoks[i] <= 0
|
242
|
+
# rvok <= lvoks.reduce(:|)
|
243
|
+
# end
|
244
|
+
end
|
239
245
|
end
|
240
246
|
end
|
247
|
+
hif (woks.reduce(:&)) do
|
248
|
+
woks.each { |wok| wok <= 0 }
|
249
|
+
lvoks.each { | lvok| lvok <=0 }
|
250
|
+
rvok <= 0
|
251
|
+
end
|
241
252
|
end
|
242
253
|
end
|
254
|
+
helse { avs.each {|av| av <= 0 } }
|
243
255
|
# helse do
|
244
256
|
# rvok <= 0
|
245
257
|
# lefts.each_with_index do |left,i|
|
data/lib/HDLRuby/std/memory.rb
CHANGED
@@ -34,6 +34,7 @@ HDLRuby::High::Std.channel(:mem_sync) do |n,typ,size,clk_e,rst,br_rsts = []|
|
|
34
34
|
size = size.to_i
|
35
35
|
# Compute the address bus width from the size.
|
36
36
|
awidth = (size-1).width
|
37
|
+
awidth = 1 if awidth == 0
|
37
38
|
# Ensure clk_e is an event, if not set it to a positive edge.
|
38
39
|
clk_e = clk_e.posedge unless clk_e.is_a?(Event)
|
39
40
|
|
@@ -209,6 +210,7 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
|
|
209
210
|
size = size.to_i
|
210
211
|
# Compute the address bus width from the size.
|
211
212
|
awidth = (size-1).width
|
213
|
+
awidth = 1 if awidth == 0
|
212
214
|
# Process the table of reset mapping for the branches.
|
213
215
|
# Ensures br_srts is a hash.
|
214
216
|
br_rsts = br_rsts.to_hash
|
@@ -292,17 +294,43 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
|
|
292
294
|
trig_r <= 0
|
293
295
|
end
|
294
296
|
# The read procedure.
|
297
|
+
# par do
|
298
|
+
# hif(rst == 0) do
|
299
|
+
# # No reset, so can perform the read.
|
300
|
+
# hif(trig_r == 1) do
|
301
|
+
# # The trigger was previously set, read ok.
|
302
|
+
# target <= dbus_r
|
303
|
+
# blk.call if blk
|
304
|
+
# end
|
305
|
+
# # Prepare the read.
|
306
|
+
# abus_r <= abus_r + 1
|
307
|
+
# trig_r <= 1
|
308
|
+
# end
|
309
|
+
# end
|
310
|
+
# The read procedure.
|
295
311
|
par do
|
296
312
|
hif(rst == 0) do
|
297
313
|
# No reset, so can perform the read.
|
298
314
|
hif(trig_r == 1) do
|
299
315
|
# The trigger was previously set, read ok.
|
300
|
-
target <= dbus_r
|
301
|
-
blk.call if blk
|
316
|
+
# target <= dbus_r
|
317
|
+
# blk.call if blk
|
318
|
+
seq do
|
319
|
+
# abus_r <= abus_r + 1
|
320
|
+
target <= dbus_r
|
321
|
+
blk.call if blk
|
322
|
+
end
|
323
|
+
end
|
324
|
+
helse do
|
325
|
+
# Prepare the read.
|
326
|
+
# abus_r <= abus_r + 1
|
327
|
+
if 2**size.width != size then
|
328
|
+
abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
|
329
|
+
else
|
330
|
+
abus_r <= abus_r + 1
|
331
|
+
end
|
332
|
+
trig_r <= 1
|
302
333
|
end
|
303
|
-
# Prepare the read.
|
304
|
-
abus_r <= abus_r + 1
|
305
|
-
trig_r <= 1
|
306
334
|
end
|
307
335
|
end
|
308
336
|
end
|
@@ -331,18 +359,44 @@ HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
|
|
331
359
|
# Reset so switch of the access trigger.
|
332
360
|
trig_r <= 0
|
333
361
|
end
|
362
|
+
# # The read procedure.
|
363
|
+
# par do
|
364
|
+
# hif(rst == 0) do
|
365
|
+
# # No reset, so can perform the read.
|
366
|
+
# hif(trig_r == 1) do
|
367
|
+
# # The trigger was previously set, read ok.
|
368
|
+
# target <= dbus_r
|
369
|
+
# blk.call if blk
|
370
|
+
# end
|
371
|
+
# # Prepare the read.
|
372
|
+
# abus_r <= abus_r - 1
|
373
|
+
# trig_r <= 1
|
374
|
+
# end
|
375
|
+
# end
|
334
376
|
# The read procedure.
|
335
377
|
par do
|
336
378
|
hif(rst == 0) do
|
337
379
|
# No reset, so can perform the read.
|
338
380
|
hif(trig_r == 1) do
|
339
381
|
# The trigger was previously set, read ok.
|
340
|
-
target <= dbus_r
|
341
|
-
blk.call if blk
|
382
|
+
# target <= dbus_r
|
383
|
+
# blk.call if blk
|
384
|
+
seq do
|
385
|
+
# abus_r <= abus_r - 1
|
386
|
+
target <= dbus_r
|
387
|
+
blk.call if blk
|
388
|
+
end
|
389
|
+
end
|
390
|
+
helse do
|
391
|
+
# Prepare the read.
|
392
|
+
# abus_r <= abus_r - 1
|
393
|
+
if 2**size.width != size then
|
394
|
+
abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
|
395
|
+
else
|
396
|
+
abus_r <= abus_r - 1
|
397
|
+
end
|
398
|
+
trig_r <= 1
|
342
399
|
end
|
343
|
-
# Prepare the read.
|
344
|
-
abus_r <= abus_r - 1
|
345
|
-
trig_r <= 1
|
346
400
|
end
|
347
401
|
end
|
348
402
|
end
|
@@ -392,6 +446,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
|
|
392
446
|
size = size.to_i
|
393
447
|
# Compute the address bus width from the size.
|
394
448
|
awidth = (size-1).width
|
449
|
+
awidth = 1 if awidth == 0
|
395
450
|
# Process the table of reset mapping for the branches.
|
396
451
|
# puts "first br_rsts=#{br_rsts}"
|
397
452
|
# if br_rsts.is_a?(Array) then
|
@@ -541,12 +596,24 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
|
|
541
596
|
# No reset, so can perform the read.
|
542
597
|
hif(trig_r == 1) do
|
543
598
|
# The trigger was previously set, read ok.
|
544
|
-
target <= dbus_r
|
545
|
-
blk.call if blk
|
599
|
+
# target <= dbus_r
|
600
|
+
# blk.call if blk
|
601
|
+
seq do
|
602
|
+
# abus_r <= abus_r + 1
|
603
|
+
target <= dbus_r
|
604
|
+
blk.call if blk
|
605
|
+
end
|
606
|
+
end
|
607
|
+
helse do
|
608
|
+
# Prepare the read.
|
609
|
+
# abus_r <= abus_r + 1
|
610
|
+
if 2**size.width != size then
|
611
|
+
abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
|
612
|
+
else
|
613
|
+
abus_r <= abus_r + 1
|
614
|
+
end
|
615
|
+
trig_r <= 1
|
546
616
|
end
|
547
|
-
# Prepare the read.
|
548
|
-
abus_r <= abus_r + 1
|
549
|
-
trig_r <= 1
|
550
617
|
end
|
551
618
|
end
|
552
619
|
end
|
@@ -581,7 +648,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
|
|
581
648
|
# No reset, so can perform the write.
|
582
649
|
blk.call if blk
|
583
650
|
# Prepare the write.
|
584
|
-
abus_w <= abus_w + 1
|
651
|
+
# abus_w <= abus_w + 1
|
652
|
+
if 2**size.width != size then
|
653
|
+
abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
|
654
|
+
else
|
655
|
+
abus_w <= abus_w + 1
|
656
|
+
end
|
585
657
|
trig_w <= 1
|
586
658
|
dbus_w <= target
|
587
659
|
end
|
@@ -613,18 +685,44 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
|
|
613
685
|
# Reset so switch of the access trigger.
|
614
686
|
trig_r <= 0
|
615
687
|
end
|
688
|
+
# # The read procedure.
|
689
|
+
# par do
|
690
|
+
# hif(rst == 0) do
|
691
|
+
# # No reset, so can perform the read.
|
692
|
+
# hif(trig_r == 1) do
|
693
|
+
# # The trigger was previously set, read ok.
|
694
|
+
# target <= dbus_r
|
695
|
+
# blk.call if blk
|
696
|
+
# end
|
697
|
+
# # Prepare the read.
|
698
|
+
# abus_r <= abus_r - 1
|
699
|
+
# trig_r <= 1
|
700
|
+
# end
|
701
|
+
# end
|
616
702
|
# The read procedure.
|
617
703
|
par do
|
618
704
|
hif(rst == 0) do
|
619
705
|
# No reset, so can perform the read.
|
620
706
|
hif(trig_r == 1) do
|
621
707
|
# The trigger was previously set, read ok.
|
622
|
-
target <= dbus_r
|
623
|
-
blk.call if blk
|
708
|
+
# target <= dbus_r
|
709
|
+
# blk.call if blk
|
710
|
+
seq do
|
711
|
+
# abus_r <= abus_r - 1
|
712
|
+
target <= dbus_r
|
713
|
+
blk.call if blk
|
714
|
+
end
|
715
|
+
end
|
716
|
+
helse do
|
717
|
+
# Prepare the read.
|
718
|
+
# abus_r <= abus_r - 1
|
719
|
+
if 2**size.width != size then
|
720
|
+
abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
|
721
|
+
else
|
722
|
+
abus_r <= abus_r - 1
|
723
|
+
end
|
724
|
+
trig_r <= 1
|
624
725
|
end
|
625
|
-
# Prepare the read.
|
626
|
-
abus_r <= abus_r - 1
|
627
|
-
trig_r <= 1
|
628
726
|
end
|
629
727
|
end
|
630
728
|
end
|
@@ -659,7 +757,12 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
|
|
659
757
|
# No reset, so can perform the write.
|
660
758
|
blk.call if blk
|
661
759
|
# Prepare the write.
|
662
|
-
abus_w <= abus_w - 1
|
760
|
+
# abus_w <= abus_w - 1
|
761
|
+
if 2**size.width != size then
|
762
|
+
abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
|
763
|
+
else
|
764
|
+
abus_w <= abus_w - 1
|
765
|
+
end
|
663
766
|
trig_w <= 1
|
664
767
|
dbus_w <= target
|
665
768
|
end
|
@@ -853,6 +956,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
853
956
|
reader_input rst_name
|
854
957
|
end
|
855
958
|
# Declares the address counter.
|
959
|
+
awidth = (size-1).width
|
960
|
+
awidth = 1 if awidth == 0
|
856
961
|
[size.width-1].inner :abus_r
|
857
962
|
reader_inout :abus_r
|
858
963
|
|
@@ -876,7 +981,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
876
981
|
end
|
877
982
|
blk.call if blk
|
878
983
|
# Prepare the next read.
|
879
|
-
abus_r <= abus_r + 1
|
984
|
+
# abus_r <= abus_r + 1
|
985
|
+
if 2**size.width != size then
|
986
|
+
abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
|
987
|
+
else
|
988
|
+
abus_r <= abus_r + 1
|
989
|
+
end
|
880
990
|
end
|
881
991
|
end
|
882
992
|
end
|
@@ -915,7 +1025,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
915
1025
|
end
|
916
1026
|
blk.call if blk
|
917
1027
|
# Prepare the next write.
|
918
|
-
abus_w <= abus_w + 1
|
1028
|
+
# abus_w <= abus_w + 1
|
1029
|
+
if 2**size.width != size then
|
1030
|
+
abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
|
1031
|
+
else
|
1032
|
+
abus_w <= abus_w + 1
|
1033
|
+
end
|
919
1034
|
end
|
920
1035
|
end
|
921
1036
|
end
|
@@ -933,6 +1048,8 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
933
1048
|
reader_input rst_name
|
934
1049
|
end
|
935
1050
|
# Declares the address counter.
|
1051
|
+
awidth = (size-1).width
|
1052
|
+
awidth = 1 if awidth == 0
|
936
1053
|
[size.width-1].inner :abus_r
|
937
1054
|
reader_inout :abus_r
|
938
1055
|
|
@@ -956,7 +1073,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
956
1073
|
end
|
957
1074
|
blk.call if blk
|
958
1075
|
# Prepare the next read.
|
959
|
-
abus_r <= abus_r - 1
|
1076
|
+
# abus_r <= abus_r - 1
|
1077
|
+
if 2**size.width != size then
|
1078
|
+
abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
|
1079
|
+
else
|
1080
|
+
abus_r <= abus_r - 1
|
1081
|
+
end
|
960
1082
|
end
|
961
1083
|
end
|
962
1084
|
end
|
@@ -995,7 +1117,12 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
|
|
995
1117
|
end
|
996
1118
|
blk.call if blk
|
997
1119
|
# Prepare the next write.
|
998
|
-
abus_w <= abus_w - 1
|
1120
|
+
# abus_w <= abus_w - 1
|
1121
|
+
if 2**size.width != size then
|
1122
|
+
abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
|
1123
|
+
else
|
1124
|
+
abus_w <= abus_w - 1
|
1125
|
+
end
|
999
1126
|
end
|
1000
1127
|
end
|
1001
1128
|
end
|
@@ -1043,7 +1170,9 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
|
|
1043
1170
|
size = size.to_i
|
1044
1171
|
# Compute the address bus width from the size.
|
1045
1172
|
awidth = (size*nbanks-1).width
|
1173
|
+
awidth = 1 if awidth == 0
|
1046
1174
|
awidth_b = (size-1).width # Bank width
|
1175
|
+
awidth_b = 1 if awidth_b == 0
|
1047
1176
|
# Ensures br_srts is a hash.
|
1048
1177
|
br_rsts = br_rsts.to_hash
|
1049
1178
|
|
@@ -1204,7 +1333,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
|
|
1204
1333
|
blk.call if blk
|
1205
1334
|
end
|
1206
1335
|
# Prepare the read.
|
1207
|
-
abus_r <= abus_r + 1
|
1336
|
+
# abus_r <= abus_r + 1
|
1337
|
+
if 2**size.width != size then
|
1338
|
+
abus_r <= mux((abus_r + 1) == size, abus_r + 1, 0)
|
1339
|
+
else
|
1340
|
+
abus_r <= abus_r + 1
|
1341
|
+
end
|
1208
1342
|
trig_r <= 1
|
1209
1343
|
end
|
1210
1344
|
end
|
@@ -1240,7 +1374,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
|
|
1240
1374
|
# No reset, so can perform the write.
|
1241
1375
|
blk.call if blk
|
1242
1376
|
# Prepare the write.
|
1243
|
-
abus_w <= abus_w + 1
|
1377
|
+
# abus_w <= abus_w + 1
|
1378
|
+
if 2**size.width != size then
|
1379
|
+
abus_w <= mux((abus_w + 1) == size, abus_w + 1, 0)
|
1380
|
+
else
|
1381
|
+
abus_w <= abus_w + 1
|
1382
|
+
end
|
1244
1383
|
trig_w <= 1
|
1245
1384
|
dbus_w <= target
|
1246
1385
|
end
|
@@ -1281,7 +1420,12 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
|
|
1281
1420
|
blk.call if blk
|
1282
1421
|
end
|
1283
1422
|
# Prepare the read.
|
1284
|
-
abus_r <= abus_r - 1
|
1423
|
+
# abus_r <= abus_r - 1
|
1424
|
+
if 2**size.width != size then
|
1425
|
+
abus_r <= mux(abus_r == 0, abus_r - 1, size - 1)
|
1426
|
+
else
|
1427
|
+
abus_r <= abus_r - 1
|
1428
|
+
end
|
1285
1429
|
trig_r <= 1
|
1286
1430
|
end
|
1287
1431
|
end
|
@@ -1318,6 +1462,11 @@ HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
|
|
1318
1462
|
blk.call if blk
|
1319
1463
|
# Prepare the write.
|
1320
1464
|
abus_w <= abus_w - 1
|
1465
|
+
if 2**size.width != size then
|
1466
|
+
abus_w <= mux(abus_w == 0, abus_w - 1, size - 1)
|
1467
|
+
else
|
1468
|
+
abus_w <= abus_w - 1
|
1469
|
+
end
|
1321
1470
|
trig_w <= 1
|
1322
1471
|
dbus_w <= target
|
1323
1472
|
end
|
data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: HDLRuby
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 2.4.
|
4
|
+
version: 2.4.11
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Lovic Gauthier
|
8
8
|
autorequire:
|
9
9
|
bindir: exe
|
10
10
|
cert_chain: []
|
11
|
-
date: 2020-
|
11
|
+
date: 2020-10-19 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: bundler
|
@@ -75,6 +75,7 @@ files:
|
|
75
75
|
- lib/HDLRuby/hdr_samples/addsub.rb
|
76
76
|
- lib/HDLRuby/hdr_samples/addsubz.rb
|
77
77
|
- lib/HDLRuby/hdr_samples/alu.rb
|
78
|
+
- lib/HDLRuby/hdr_samples/bstr_bench.rb
|
78
79
|
- lib/HDLRuby/hdr_samples/calculator.rb
|
79
80
|
- lib/HDLRuby/hdr_samples/counter_bench.rb
|
80
81
|
- lib/HDLRuby/hdr_samples/dff.rb
|
@@ -88,6 +89,7 @@ files:
|
|
88
89
|
- lib/HDLRuby/hdr_samples/memory_test.rb
|
89
90
|
- lib/HDLRuby/hdr_samples/multer_gen.rb
|
90
91
|
- lib/HDLRuby/hdr_samples/multer_seq.rb
|
92
|
+
- lib/HDLRuby/hdr_samples/neg_arith_bench.rb
|
91
93
|
- lib/HDLRuby/hdr_samples/neural/a.rb
|
92
94
|
- lib/HDLRuby/hdr_samples/neural/a_sub.rb
|
93
95
|
- lib/HDLRuby/hdr_samples/neural/bw.rb
|
@@ -123,6 +125,7 @@ files:
|
|
123
125
|
- lib/HDLRuby/hdr_samples/with_linear.rb
|
124
126
|
- lib/HDLRuby/hdr_samples/with_loop.rb
|
125
127
|
- lib/HDLRuby/hdr_samples/with_memory.rb
|
128
|
+
- lib/HDLRuby/hdr_samples/with_memory_rom.rb
|
126
129
|
- lib/HDLRuby/hdr_samples/with_multi_channels.rb
|
127
130
|
- lib/HDLRuby/hdr_samples/with_reconf.rb
|
128
131
|
- lib/HDLRuby/hdrcc.rb
|