HDLRuby 2.3.5 → 2.4.6

data/lib/HDLRuby/hruby_low_resolve.rb

@@ -145,6 +145,7 @@ module HDLRuby::Low
             # puts "Resolve with #{self} and name=#{self.name}"
             # First resolve the sub reference if possible.
             if self.ref.is_a?(RefName) then
+                # puts "ref name=#{self.ref.name}"
                 obj = self.ref.resolve
                 # Look into the object for the name.
                 return obj.get_by_name(self.name)

data/lib/HDLRuby/hruby_low_without_connection.rb

@@ -29,7 +29,9 @@ module HDLRuby::Low
                 if scope.each_connection.to_a.any? then
                     inputs_blk = Block.new(:par)
                     outputs_blk = Block.new(:par)
+                    timed_blk = TimeBlock.new(:seq)
                     scope.each_connection do |connection|
+                        # puts "For connection: #{connection}"
                         # Check the left and right of the connection
                         # for input or output port.
                         left = connection.left
@@ -40,6 +42,15 @@ module HDLRuby::Low
                         right_r = right.resolve if right.respond_to?(:resolve)
                         # puts "right_r=#{right_r.name}" if right_r
                         # puts "right_r.parent=#{right_r.parent.name}" if right_r && right_r.parent
+                        if right.is_a?(Value) then
+                            # Right is value, the new transmit is to add
+                            # to the timed block.
+                            timed_blk.add_statement(
+                                Transmit.new(left.clone,right.clone))
+                            # No more process for this connection.
+                            next
+                        end
+
                         # Check if left is an input or an output.
                         left_is_i = left_is_o = false
                         if left_r && left_r.parent.is_a?(SystemT) then
@@ -118,6 +129,9 @@ module HDLRuby::Low
                     if outputs_blk.each_statement.any? then
                         scope.add_behavior(Behavior.new(outputs_blk))
                     end
+                    if timed_blk.each_statement.any? then
+                        scope.add_behavior(TimeBehavior.new(timed_blk))
+                    end
                 end
             end
         end

data/lib/HDLRuby/sim/hruby_sim.h

@@ -170,6 +170,12 @@ extern Value mod_value(Value src0, Value src1, Value dst);
  *  @return dst */
 extern Value not_value(Value src, Value dst);
 
+/** Compute the or of the bits a a value.
+ *  @param src the source value
+ *  @param dst the destination value
+ *  @return dst */
+extern Value reduce_or_value(Value src, Value dst);
+
 /** Computes the AND of two values.
  *  @param src0 the first source value of the and
  *  @param src1 the second source value of the and
@@ -185,43 +191,43 @@ extern Value and_value(Value src0, Value src1, Value dst);
 extern Value or_value(Value src0, Value src1, Value dst);
 
 /** Computes the XOR of two values.
- *  @param src0 the first source value of the or
- *  @param src1 the second source value of the or
+ *  @param src0 the first source value of the xor
+ *  @param src1 the second source value of the xor
  *  @param dst the destination value
  *  @return dst */
 extern Value xor_value(Value src0, Value src1, Value dst);
 
 /** Computes the left shift of two general values.
- *  @param src0 the first source value of the addition
- *  @param src1 the second source value of the addition
+ *  @param src0 the first source value of the shift
+ *  @param src1 the second source value of the shift
  *  @param dst the destination
  *  @return dst */
 Value shift_left_value(Value src0, Value src1, Value dst);
 
 /** Computes the right shift of two general values.
- *  @param src0 the first source value of the addition
- *  @param src1 the second source value of the addition
+ *  @param src0 the first source value of the shift
+ *  @param src1 the second source value of the shift
  *  @param dst the destination
  *  @return dst */
 Value shift_right_value(Value src0, Value src1, Value dst);
 
 /** Computes the equal (NXOR) of two values.
- *  @param src0 the first source value of the addition
- *  @param src1 the second source value of the addition
+ *  @param src0 the first source value of the comparison
+ *  @param src1 the second source value of the comparison
  *  @param dst the destination value
  *  @return dst */
 extern Value equal_value(Value src0, Value src1, Value dst);
 
 /** Computes the lesser comparision of two values.
- *  @param src0 the first source value of the addition
- *  @param src1 the second source value of the addition
+ *  @param src0 the first source value of the comparison
+ *  @param src1 the second source value of the comparison
  *  @param dst the destination value
  *  @return dst */
 extern Value lesser_value(Value src0, Value src1, Value dst);
 
 /** Computes the greater comparision of two values.
- *  @param src0 the first source value of the addition
- *  @param src1 the second source value of the addition
+ *  @param src0 the first source value of the comparison
+ *  @param src1 the second source value of the comparison
  *  @param dst the destination value
  *  @return dst */
 extern Value greater_value(Value src0, Value src1, Value dst);
@@ -468,6 +474,7 @@ typedef struct BlockS_ {
     Kind kind;          /* The kind of object. */
     Object owner;       /* The owner if any. */
 
+    char* name;         /* The name of the block. */
     int num_inners;     /* The number of inners. */
     SignalI* inners;    /* The inners of the scope. */
     void (*function)(); /* The function to execute for the block. */
@@ -490,6 +497,9 @@ typedef struct EventS_ {
 /* The time units. */
 typedef enum { S, MS, US, NS, PS, FS } Unit;
 
+/** The top system. */
+extern SystemT top_system;
+
 /** Adds a timed behavior for processing. 
  *  @param behavior the timed behavior to register */
 extern void register_timed_behavior(Behavior behavior);
@@ -555,39 +565,71 @@ extern unsigned long long make_delay(int value, Unit unit);
 
 
 
+/* Iterate over all the signals.
+ * @param func function to applie on each signal. */
+extern void each_all_signal(void (*func)(SignalI));
 
 /* Interface to the visualization engine. */
 
-/** Prints the time.
- *  @param time the time to show. */
-extern void print_time(unsigned long long time);
-
-/** Prints the time and goes to the next line.
- *  @param time the time to show. */
-extern void println_time(unsigned long long time);
-
-/** Prints the name of an object.
- *  @param object the object to print the name. */
-extern void print_name(Object object);
-
-/** Prints a value.
- *  @param value the value to print */
-extern void print_value(Value value);
-
-/** Prints a signal.
- *  @param signal the signal to show */
-extern void print_signal(SignalI signal);
-
-/** Prints a signal and goes to the next line.
- *  @param signal the signal to show */
-extern void println_signal(SignalI signal);
-
+typedef struct {
+    void (*print_time)(unsigned long long);
+    void (*print_name)(Object);
+    void (*print_value)(Value);
+    void (*print_signal)(SignalI);
+} PrinterS;
+
+extern PrinterS printer;
+
+/** Initializes the visualization printer engine.
+ *  @param print_time the time printer
+ *  @param print_name the name printer
+ *  @param print_value the value printer
+ *  @param print_signal the signal state printer. */
+extern void init_visualizer(void (*print_time)(unsigned long long), 
+                            void (*print_name)(Object),
+                            void (*print_value)(Value),
+                            void (*print_signal)(SignalI));
+
+// /** Prints the time.
+//  *  @param time the time to show. */
+// extern void print_time(unsigned long long time);
+// 
+// // /** Prints the time and goes to the next line.
+// //  *  @param time the time to show. */
+// // extern void println_time(unsigned long long time);
+// 
+// /** Prints the name of an object.
+//  *  @param object the object to print the name. */
+// extern void print_name(Object object);
+// 
+// /** Prints a value.
+//  *  @param value the value to print */
+// extern void print_value(Value value);
+// 
+// /** Prints a signal.
+//  *  @param signal the signal to show */
+// extern void print_signal(SignalI signal);
+// 
+// // /** Prints a signal and goes to the next line.
+// //  *  @param signal the signal to show */
+// // extern void println_signal(SignalI signal);
+
+/** Sets up the default vizualization engine.
+ *  @param name the name of the vizualization. */
+extern void init_default_visualizer(char* name);
+
+/** Sets up the vcd vizualization engine.
+ *  @param name the name of the vizualization. */
+extern void init_vcd_visualizer(char* name);
 
 /* The interface to the simulator core. */
 
 /** The simulation core function.
+ *  @param name the name of the simulation.
+ *  @param init_vizualizer the vizualizer engine initializer.
  *  @param limit the time limit in fs. */
-extern void hruby_sim_core(unsigned long long limit);
+extern void hruby_sim_core(char* name, void (*init_vizualizer)(char*),
+                           unsigned long long limit);
 
 
 

data/lib/HDLRuby/sim/hruby_sim_calc.c

@@ -714,6 +714,45 @@ static Value not_value_bitstring(Value src, Value dst) {
     return dst;
 }
 
+/** Compute the or of the bits a bitstring value.
+ *  @param src the source value
+ *  @param dst the destination value
+ *  @return dst */
+Value reduce_or_value_bitstring(Value src, Value dst) {
+    /* Compute the width of the result in bits. */
+    unsigned long long width = type_width(src->type);
+
+    /* Update the destination capacity if required. */
+    resize_value(dst,width);
+    /* Set the type and size of the destination from the type of the source.*/
+    dst->type = src->type;
+    dst->numeric = 0;
+
+    /* Get access to the source and destination data. */
+    char* src_data = src->data_str;
+    char* dst_data = dst->data_str;
+
+    /* Performs the reduce or. */
+    unsigned long long count;
+    char res;
+    for(count = 0; count < width; ++count) {
+        /* Performs the reduce or. */
+        char d = src_data[count] - '0'; /* Get and convert to bit. */
+        if ((d == (d&1)) && (res != 'x'-'0')) { /* d is defined. */
+            res |= d;
+        } else {
+            /* res is undefined. */
+            res = 'x' - '0';
+        }
+        /* Apart for the first bit, there are only 0, still we are in
+         * the loop, set it. */
+        dst_data[count] = '0';
+    }
+    dst_data[0] = res + '0';
+    /* Return the destination. */
+    return dst;
+}
+
 
 /** Computes the and of two bitstring values.
  *  @param src0 the first source value of the and
@@ -1575,6 +1614,21 @@ static Value not_value_numeric(Value src, Value dst) {
 }
 
 
+/** Compute the or of the bits a numeric value.
+ *  @param src the source value
+ *  @param dst the destination value
+ *  @return dst */
+Value reduce_or_value_numeric(Value src, Value dst) {
+    /* Sets state of the destination using the first source. */
+    dst->type = src->type;
+    dst->numeric = 1;
+
+    /* Perform the reduce or. */
+    dst->data_int = fix_numeric_type(dst->type, src->data_int != 0);
+    return dst;
+}
+
+
 /** Computes the AND of two numeric values.
  *  @param src0 the first source value of the addition
  *  @param src1 the second source value of the addition
@@ -2093,6 +2147,21 @@ Value not_value(Value src, Value dst) {
 }
 
 
+/** Compute the or of the bits a value.
+ *  @param src the source value
+ *  @param dst the destination value
+ *  @return dst */
+Value reduce_or_value(Value src, Value dst) {
+    if (src->numeric) {
+        /* The source is numeric. */
+        return reduce_or_value_numeric(src,dst);
+    } else {
+        /* The source cannot be numeric, compute bitsitrings. */
+        return reduce_or_value_bitstring(src,dst);
+    }
+}
+
+
 /** Computes the AND of two general values. 
  *  @param src0 the first source value of the addition
  *  @param src1 the second source value of the addition

data/lib/HDLRuby/sim/hruby_sim_core.c

@@ -12,6 +12,9 @@
  *  hruby_low2c. 
  *  */
 
+/** The top system. */
+SystemT top_system;
+
 /** The number of all the signals. */
 static int num_all_signals = 0;
 /** The capacity of the set of signals. */
@@ -118,9 +121,10 @@ void hruby_sim_update_signals() {
             /* Is there a change? */
             if (same_content_value(sig->c_value,sig->f_value)) continue;
             /* Yes, process the signal. */
-            println_signal(sig);
-            // printf("c_value="); print_value(sig->c_value);
-            // printf("\nf_value="); print_value(sig->f_value); printf("\n");
+            // println_signal(sig);
+            printer.print_signal(sig);
+            // printf("c_value="); printer.print_value(sig->c_value);
+            // printf("\nf_value="); printer.print_value(sig->f_value); printf("\n");
             // printf("Touched signal: %p (%s)\n",sig,sig->name);
             /* Update the current value of the signal. */
             copy_value(sig->f_value,sig->c_value);
@@ -185,7 +189,8 @@ void hruby_sim_update_signals() {
             SignalI sig = e->data;
             delete_element(e);
             /* Yes, process the signal. */
-            println_signal(sig);
+            // println_signal(sig);
+            printer.print_signal(sig);
             /* Update the current value of the signal. */
             /* Mark the corresponding code as activated. */
             /* Any edge activation. */
@@ -284,7 +289,8 @@ void hruby_sim_advance_time() {
     }
     /* Sets the new activation time. */
     hruby_sim_time = next_time;
-    println_time(hruby_sim_time);
+    // println_time(hruby_sim_time);
+    printer.print_time(hruby_sim_time);
 }
 
 
@@ -393,9 +399,18 @@ void hruby_sim_end_timed_behaviors() {
 
 
 
+// /** The simulation core function.
+//  *  @param limit the time limit in fs. */
+// void hruby_sim_core(unsigned long long limit) {
 /** The simulation core function.
+ *  @param name the name of the simulation.
+ *  @param vizualizer the vizualizer engine initializer.
  *  @param limit the time limit in fs. */
-void hruby_sim_core(unsigned long long limit) {
+void hruby_sim_core(char* name, void (*init_vizualizer)(char*),
+                           unsigned long long limit) {
+    /* Initilize the vizualizer. */
+    init_vizualizer(name);
+
     /* Initialize the time to 0. */
     hruby_sim_time = 0;
 
@@ -597,3 +612,14 @@ unsigned long long make_delay(int value, Unit unit) {
     return -1;
 }
 
+
+
+
+/* Iterate over all the signals.
+ * @param func function to applie on each signal. */
+void each_all_signal(void (*func)(SignalI)) {
+    int i;
+    for(i = 0; i<num_all_signals; ++i) {
+        func(all_signals[i]);
+    }
+}

data/lib/HDLRuby/sim/hruby_sim_vcd.c

@@ -0,0 +1,380 @@
+#include <stdio.h>
+#include <string.h>
+#include <time.h>
+#include <stdarg.h>
+#include "hruby_sim.h"
+
+
+/**
+ *  The HDLRuby simulation vcd format genertion engine, to be used with C code
+ *  generated by hruby_low2c. 
+ **/
+
+/* Global variables storing the configuration of the vcd generation. */
+
+/* The target file. */
+static FILE* vcd_file;
+
+/* The time scale unit in the ps. */
+static unsigned long long vcd_timeunit = 1;
+
+/* Accessing target file. */
+
+/** Prints to the vcd file.
+ *  @param fmt the format for handling the variadic arguments. */
+static int vcd_print(char* fmt, ...) {
+    int ret;
+
+    /* Declare a va_list type variable */
+    va_list myargs;
+
+    /* Initialise the va_list variable with the ... after fmt */
+    va_start(myargs, fmt);
+
+    /* Forward the '...' to vprintf */
+    ret = vfprintf(vcd_file, fmt, myargs);
+
+    /* Clean up the va_list */
+    va_end(myargs);
+
+    return ret;
+}
+
+
+/* Utility functions for printing in vcd format. */
+
+/* Replace all the occurences of a character with another. 
+ * CREDIT: Superlokkus */
+static char* replace_char(char* str, char find, char replace){
+    char *current_pos = strchr(str,find);
+    while (current_pos){
+        *current_pos = replace;
+        current_pos = strchr(current_pos+1,find);
+    }
+    return str;
+}
+
+
+/* Low-end print functions. */
+
+/** Prints the time.
+ *  @param time the time to show (given in ps). */
+static void vcd_print_time(unsigned long long time) {
+    vcd_print("#%llu\n",time/vcd_timeunit);
+}
+
+
+/** Prints the name of an object without its hierarchy.
+ *  @param object the object to print the name. */
+static void vcd_print_name(Object object) {
+    /* Depending on the kind of object. */
+    switch(object->kind) {
+        case SYSTEMT:
+        case SIGNALI:
+        case SCOPE:
+        case SYSTEMI:
+        case BLOCK:
+            /* Print the name if name. */
+            /* Trick: SystemT, SignalI, Scope and SystemI have the
+             * field name at the same place. */
+            if ((((Block)object)->name != NULL) &&
+                    strlen(((Block)object)->name)>0) {
+                char name[256];
+                strncpy(name,((Block)object)->name,256);
+                replace_char(name,':','$');
+                vcd_print("%s",name);
+            } else {
+                /* No name, use the address of the object as name generator.*/
+                vcd_print("$%p",(void*)object);
+            }
+            break;
+        default: /* Nothing to do */
+            break;
+    }
+}
+
+
+/** Prints the name of an object incluing its heirarchy.
+ *  @param object the object to print the name. */
+static void vcd_print_full_name(Object object) {
+    /* Recurse on the owner if any. */
+    // printf("owner=%p\n",object->owner);
+    if (object->owner != NULL) {
+        vcd_print_full_name(object->owner);
+        vcd_print("$");
+    }
+    /* Print the name of the object. */
+    vcd_print_name(object);
+}
+
+/** Prints a value.
+ *  @param value the value to print */
+static void vcd_print_value(Value value) {
+    vcd_print("b");
+    if (value->numeric) {
+        unsigned long long width = type_width(value->type);
+        unsigned long long mask = 1ULL << (width-1);
+        for(; mask > 0; mask >>= 1) {
+            vcd_print("%d",(value->data_int & mask) != 0);
+        }
+    } else {
+        /* Display a bitstring value. */
+        int i;
+        int width = type_width(value->type);
+        char* data = value->data_str;
+        if (value->capacity == 0) {
+            /* The value is empty, therefore undefined. */
+            for(i=width; i>0; --i) {
+                vcd_print("u");
+            }
+        }
+        else {
+            /* The value is not empty. */
+            for(i=width; i>0; --i) {
+                vcd_print("%c",data[i-1]);
+            } 
+        }
+    }
+}
+
+/** Prints a signal declaration.
+ *  @param signal the signal to declare */
+static void vcd_print_var(SignalI signal) {
+    vcd_print("$var wire %d ",type_width(signal->type));
+    vcd_print_full_name((Object)signal);
+    vcd_print(" ");
+    vcd_print_name((Object)signal);
+    vcd_print(" $end\n");
+}
+
+
+/** Prints a signal with its future value if any.
+ *  @param signal the signal to show */
+static void vcd_print_signal_fvalue(SignalI signal) {
+    if (signal->f_value) {
+        vcd_print_value(signal->f_value);
+        vcd_print(" ");
+        vcd_print_full_name((Object)signal);
+        vcd_print("\n");
+    }
+}
+
+
+/** Prints a signal with its current value if any
+ *  @param signal the signal to show */
+static void vcd_print_signal_cvalue(SignalI signal) {
+    if (signal->c_value) {
+        vcd_print_value(signal->c_value);
+        vcd_print(" ");
+        vcd_print_full_name((Object)signal);
+        vcd_print("\n");
+    }
+}
+
+
+/** Prints the hierarchy content of a system type.
+ *  @param system the system to print. */
+static void vcd_print_systemT_content(SystemT system);
+
+/** Prints the hierarchy of a scope.
+ *  @param scope the scope to print. */
+static void vcd_print_scope(Scope scope);
+
+
+/** Prints the hierarchy of a block.
+ *  @param block the block to print. */
+static void vcd_print_block(Block block) {
+    int i;
+    /* Do not print block with no declaration. */
+    if (block->num_inners == 0) return;
+
+    /* Declares the block if named. */
+    vcd_print("$scope module ");
+    vcd_print_name((Object)block);
+    vcd_print(" $end\n");
+
+    /* Declare the inners of the systems. */
+    for(i=0; i<block->num_inners; ++i) {
+        vcd_print_var(block->inners[i]);
+    }
+
+    /* Close the hierarchy. */
+    vcd_print("$upscope $end\n");
+}
+
+
+/** Prints the hierarchy of a system instances.
+ *  @param scope the scope to print. */
+static void vcd_print_systemI(SystemI systemI) {
+    /* Declares the systemI. */
+    vcd_print("$scope module ");
+    vcd_print_name((Object)systemI);
+    vcd_print(" $end\n");
+
+    /* Declares its content. */
+    vcd_print_systemT_content(systemI->system);
+
+    /* Close the hierarchy. */
+    vcd_print("$upscope $end\n");
+}
+
+
+/** Prints the hierarchy inside a scope.
+ *  @param scope the scope to print the inside. */
+static void vcd_print_scope_content(Scope scope) {
+    int i;
+
+    /* Declare the inners of the systems. */
+    for(i=0; i<scope->num_inners; ++i) {
+        vcd_print_var(scope->inners[i]);
+    }
+
+    /* Recurse on the system instances. */
+    for(i=0; i<scope->num_systemIs; ++i) {
+        vcd_print_systemI(scope->systemIs[i]);
+    }
+
+    /* Recurse on the sub scopes. */
+    for(i=0; i<scope->num_scopes; ++i) {
+        vcd_print_scope(scope->scopes[i]);
+    }
+
+    /* Recurse on the behaviors. */
+    for(i=0; i<scope->num_behaviors; ++i) {
+        vcd_print_block(scope->behaviors[i]->block);
+    }
+}
+
+
+/** Prints the hierarchy of a scope.
+ *  @param scope the scope to print. */
+static void vcd_print_scope(Scope scope) {
+    /* Do not print block with no declaration. */
+    if (scope->num_inners == 0 && scope->num_scopes == 0 && scope->num_behaviors == 0) return;
+    /* Declares the scope. */
+    vcd_print("$scope module ");
+    vcd_print_name((Object)scope);
+    vcd_print(" $end\n");
+
+    /* Declares its content. */
+    vcd_print_scope_content(scope);
+
+    /* Close the hierarchy. */
+    vcd_print("$upscope $end\n");
+}
+
+
+/** Prints the hierarchy content of a system type.
+ *  @param system the system to print. */
+static void vcd_print_systemT_content(SystemT system) {
+    int i;
+
+    /* Declare the inputs of the systems. */
+    for(i = 0; i<system->num_inputs; ++i) {
+        vcd_print_var(system->inputs[i]);
+    }
+    /* Declare the outputs of the systems. */
+    for(i = 0; i<system->num_outputs; ++i) {
+        vcd_print_var(system->outputs[i]);
+    }
+    /* Declare the inouts of the systems. */
+    for(i = 0; i<system->num_inouts; ++i) {
+        vcd_print_var(system->inouts[i]);
+    }
+    /* Recurse on the content of the scope (the scope header is the system).*/
+    vcd_print_scope_content(system->scope);
+}
+
+
+/** Prints the hierarchy of a system type.
+ *  @param system the system to print. */
+static void vcd_print_systemT(SystemT system) {
+    int i;
+    /* Declares the module. */
+    vcd_print("$scope module ");
+    vcd_print_name((Object)system);
+    vcd_print(" $end\n");
+
+    /* Declares the content. */
+    vcd_print_systemT_content(system);
+
+    /* Close the hierarchy. */
+    vcd_print("$upscope $end\n");
+}
+
+
+
+
+
+/* high-end print functions. */
+
+/** Prints the header of the vcd file. */
+static void vcd_print_header() {
+    /* The date section. */
+    vcd_print("$date\n");
+    {
+        char text[100];
+        time_t now = time(NULL);
+        struct tm *t = localtime(&now);
+        strftime(text, sizeof(text), "%d %m %Y %H:%M", t);
+        vcd_print("   %s\n", text);
+    }
+    vcd_print("$end\n");
+
+    /* The version section. */
+    vcd_print("$version\n");
+    vcd_print("   Generated from HDLRuby simulator\n");
+    vcd_print("$end\n");
+    
+    /* The comment section. */
+    vcd_print("$comment\n");
+    vcd_print("   Is it an easter egg?\n");
+    vcd_print("$end\n");
+
+    /* The time scale section: for now 1ps only. */
+    vcd_print("$timescale 1ps $end\n");
+
+    // /* The scope section: nothing specific. */
+    // vcd_print("$scope module logic $end\n");
+
+    // /* The variables declaration. */
+    // each_all_signal(&vcd_print_var);
+
+    // /* Ends the declarations. */
+    // vcd_print("$upscope $end\n");
+    // vcd_print("$enddefinitions $end\n");
+
+    /* The declaration of the hierarchy and the variables
+     * from the top system. */
+    vcd_print_systemT(top_system);
+    /* Ends the declarations. */
+    vcd_print("$enddefinitions $end\n");
+
+    /* Display the initializations. */
+    vcd_print("$dumpvars\n");
+    each_all_signal(&vcd_print_signal_cvalue);
+    vcd_print("$end\n");
+}
+
+
+/* The configuration and initialization of the vcd vizualizer. */
+
+
+/** Sets up the vcd vizualization engine.
+ *  @param name the name of the vizualization. */
+extern void init_vcd_visualizer(char* name) {
+    /* Open the resulting file with name: <name>.vcd */
+    char filename[256];
+    strncpy(filename,name,256);
+    strncat(filename,".vcd",256);
+    vcd_file = fopen(filename,"w");
+
+    /* Initialize the vizualizer printer engine. */
+    init_visualizer(&vcd_print_time,
+                    &vcd_print_full_name,
+                    &vcd_print_value,
+                    &vcd_print_signal_fvalue);
+
+    /* Prints the header of the vcd file. */
+    vcd_print_header();
+}