HDLRuby 2.3.5 → 2.4.6
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- checksums.yaml +4 -4
- data/README.md +1 -0
- data/lib/HDLRuby/hdr_samples/bstr_bench.rb +14 -0
- data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +9 -0
- data/lib/HDLRuby/hdr_samples/with_linear.rb +3 -15
- data/lib/HDLRuby/hdr_samples/with_multi_channels.rb +300 -0
- data/lib/HDLRuby/hdrcc.rb +10 -1
- data/lib/HDLRuby/hruby_bstr.rb +5 -2
- data/lib/HDLRuby/hruby_high.rb +8 -0
- data/lib/HDLRuby/hruby_low.rb +107 -8
- data/lib/HDLRuby/hruby_low2c.rb +24 -7
- data/lib/HDLRuby/hruby_low_mutable.rb +90 -2
- data/lib/HDLRuby/hruby_low_resolve.rb +1 -0
- data/lib/HDLRuby/hruby_low_without_connection.rb +14 -0
- data/lib/HDLRuby/sim/hruby_sim.h +79 -37
- data/lib/HDLRuby/sim/hruby_sim_calc.c +69 -0
- data/lib/HDLRuby/sim/hruby_sim_core.c +32 -6
- data/lib/HDLRuby/sim/hruby_sim_vcd.c +380 -0
- data/lib/HDLRuby/sim/hruby_sim_vizualize.c +51 -12
- data/lib/HDLRuby/std/channel.rb +302 -60
- data/lib/HDLRuby/std/linear.rb +16 -8
- data/lib/HDLRuby/version.rb +1 -1
- metadata +5 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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-
metadata.gz:
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data.tar.gz:
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metadata.gz: 9c3f6418748c0552d8c5d8544ae64ebdc287646b95ffec70d50c66d131529a6a
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4
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data.tar.gz: c2c55a5b9defc62bbb387072dd318918f9dc802065eb764303cacac3cfbf5f91
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 619d787d2f4f621591f37b06d4cf048c39a1a652a810835b18aa12610c69a17d2587a06fee10a3f2ff4406b744b567d2aed5d2dc21b2a5201676057c58a24b26
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7
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+
data.tar.gz: a5d2677dd07c54224dfb189d28c5c82015c4b099b7b204049402d1df940ac19e9051f9e199e56e6f2d043134697b307873b53e80dc86728bca2ebdc1087ce39f
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data/README.md
CHANGED
@@ -50,6 +50,7 @@ Where:
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50
50
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| `-s, --syntax` | Output the Ruby syntax tree |
|
51
51
|
| `-C, --clang` | Output the C code of the simulator |
|
52
52
|
| `-S, --sim` | Output the executable simulator and execute it |
|
53
|
+
| `--vcd` | Make the simulator generate a vcd file |
|
53
54
|
| `-d, --directory` | Specify the base directory for loading the HDLRuby files |
|
54
55
|
| `-D, --debug` | Set the HDLRuby debug mode |
|
55
56
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| `-t, --top system`| Specify the top system describing the circuit to compile |
|
@@ -9,6 +9,8 @@ system :fix_test do
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|
9
9
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|
10
10
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# Declare three 4-bit integer part 4-bit fractional part
|
11
11
|
bit[3..0,3..0].inner :x,:y,:z
|
12
|
+
# Declare three 8-bit integer part 8-bit fractional part
|
13
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+
signed[3..0,3..0].inner :a,:b,:c,:d
|
12
14
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|
13
15
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# Performs calculation between then
|
14
16
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timed do
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@@ -22,5 +24,12 @@ system :fix_test do
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22
24
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!10.ns
|
23
25
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z <= z / x
|
24
26
|
!10.ns
|
27
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+
a <= _00010000
|
28
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+
b <= _00001111
|
29
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+
!10.ns
|
30
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+
c <= a * b
|
31
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+
d <= 0
|
32
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+
!10.ns
|
33
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+
d <= d + c
|
25
34
|
end
|
26
35
|
end
|
@@ -22,9 +22,6 @@ system :testmat do
|
|
22
22
|
mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memL1)
|
23
23
|
mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memR)
|
24
24
|
# Access ports.
|
25
|
-
# # memL0.branch(:rinc).inner :readL0
|
26
|
-
# # memL1.branch(:rinc).inner :readL1
|
27
|
-
# # memR.branch(:rinc).inner :readR
|
28
25
|
# memL0.branch(:rinc).input :readL0
|
29
26
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# memL1.branch(:rinc).input :readL1
|
30
27
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# memR.branch(:rinc).input :readR
|
@@ -35,9 +32,9 @@ system :testmat do
|
|
35
32
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|
36
33
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# Accumulators memory.
|
37
34
|
mem_file([8],2,clk,rst,rinc: :rst).(:memAcc)
|
38
|
-
#
|
39
|
-
|
40
|
-
accs_out = [
|
35
|
+
# memAcc.branch(:anum).inout :accs
|
36
|
+
# accs_out = [accs.wrap(0), accs.wrap(1)]
|
37
|
+
accs_out = [memAcc.branch(:anum).wrap(0), memAcc.branch(:anum).wrap(1)]
|
41
38
|
|
42
39
|
# Layer 0 ack.
|
43
40
|
inner :ack0
|
@@ -52,8 +49,6 @@ system :testmat do
|
|
52
49
|
# Tarnslation result
|
53
50
|
mem_file([8],2,clk,rst,rinc: :rst).(:memF)
|
54
51
|
# Access ports.
|
55
|
-
# # memT.branch(:anum).inner :readT
|
56
|
-
# # memF.branch(:anum).inner :writeF
|
57
52
|
memT.branch(:anum).input :readT
|
58
53
|
memF.branch(:anum).output :writeF
|
59
54
|
regRs = [ readT.wrap(0), readT.wrap(1) ]
|
@@ -72,8 +67,6 @@ system :testmat do
|
|
72
67
|
# Input memories.
|
73
68
|
mem_dual([8],2,clk,rst, rinc: :rst,winc: :rst).(:mem2L0)
|
74
69
|
# Access ports.
|
75
|
-
# # mem2L0.branch(:rinc).inner :read2L0
|
76
|
-
# # memF.branch(:rinc).inner :readF
|
77
70
|
# mem2L0.branch(:rinc).input :read2L0
|
78
71
|
# memF.branch(:rinc).input :readF
|
79
72
|
|
@@ -93,11 +86,6 @@ system :testmat do
|
|
93
86
|
|
94
87
|
|
95
88
|
# The memory initializer.
|
96
|
-
# # memL0.branch(:winc).inner :writeL0
|
97
|
-
# # memL1.branch(:winc).inner :writeL1
|
98
|
-
# # memR.branch(:winc).inner :writeR
|
99
|
-
# # memT.branch(:winc).inner :writeT
|
100
|
-
# # mem2L0.branch(:winc).inner :write2L0
|
101
89
|
# memL0.branch(:winc).output :writeL0
|
102
90
|
# memL1.branch(:winc).output :writeL1
|
103
91
|
# memR.branch(:winc).output :writeR
|
@@ -0,0 +1,300 @@
|
|
1
|
+
require "std/channel.rb"
|
2
|
+
|
3
|
+
include HDLRuby::High::Std
|
4
|
+
|
5
|
+
# Channel describing a buffered queue storing data of +typ+ type of +depth+,
|
6
|
+
# synchronized through clk and reset on +rst+.
|
7
|
+
channel(:queue) do |typ,depth,clk,rst|
|
8
|
+
# The inner buffer of the queue.
|
9
|
+
typ[-depth].inner :buffer
|
10
|
+
# The read and write pointers.
|
11
|
+
[depth.width].inner :rptr, :wptr
|
12
|
+
# The read and write command signals.
|
13
|
+
inner :rcmd, :wcmd
|
14
|
+
# The read and write ack signals.
|
15
|
+
inner :rack, :wack
|
16
|
+
# The ack check deactivator (for synchron accesses).
|
17
|
+
inner :hrack, :hwack
|
18
|
+
# The read/write data registers.
|
19
|
+
typ.inner :rdata, :wdata
|
20
|
+
|
21
|
+
# The process handling the decoupled access to the buffer.
|
22
|
+
par(clk.posedge) do
|
23
|
+
# rack <= 0
|
24
|
+
# wack <= 0
|
25
|
+
hif (~rcmd) { rack <= 0 }
|
26
|
+
hif (~wcmd) { wack <= 0 }
|
27
|
+
hif(rst) { rptr <= 0; wptr <= 0 }
|
28
|
+
hif(rcmd & (hrack|~rack) & (rptr != wptr)) do
|
29
|
+
rptr <= (rptr + 1) % depth
|
30
|
+
rack <= 1
|
31
|
+
end
|
32
|
+
hif(wcmd & (hwack|~wack) & (((wptr+1) % depth) != rptr)) do
|
33
|
+
buffer[wptr] <= wdata
|
34
|
+
# buffer[1] <= wdata
|
35
|
+
wptr <= (wptr + 1) % depth
|
36
|
+
wack <= 1
|
37
|
+
end
|
38
|
+
end
|
39
|
+
par { rdata <= buffer[rptr] }
|
40
|
+
|
41
|
+
reader_output :rcmd, :rptr, :hrack
|
42
|
+
reader_input :rdata, :rack
|
43
|
+
|
44
|
+
# The read primitive.
|
45
|
+
reader do |blk,target|
|
46
|
+
if (cur_behavior.on_event?(clk.posedge,clk.negedge)) then
|
47
|
+
# Same clk event, synchrone case: perform a direct access.
|
48
|
+
# Now perform the access.
|
49
|
+
top_block.unshift do
|
50
|
+
rcmd <= 0
|
51
|
+
hrack <= 1
|
52
|
+
end
|
53
|
+
seq do
|
54
|
+
rptr <= (rptr + 1) % depth
|
55
|
+
target <= rdata
|
56
|
+
blk.call if blk
|
57
|
+
end
|
58
|
+
else
|
59
|
+
# Different clk event, perform a decoupled access.
|
60
|
+
top_block.unshift do
|
61
|
+
rcmd <= 0
|
62
|
+
hrack <= 0
|
63
|
+
end
|
64
|
+
seq do
|
65
|
+
hif(rack) do
|
66
|
+
blk.call if blk
|
67
|
+
end
|
68
|
+
helse do
|
69
|
+
rcmd <= 1
|
70
|
+
target <= rdata
|
71
|
+
end
|
72
|
+
end
|
73
|
+
end
|
74
|
+
end
|
75
|
+
|
76
|
+
writer_output :wcmd, :wdata, :hwack
|
77
|
+
writer_input :wack
|
78
|
+
|
79
|
+
# The write primitive.
|
80
|
+
writer do |blk,target|
|
81
|
+
if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
|
82
|
+
# Same clk event, synchrone case: perform a direct access.
|
83
|
+
top_block.unshift do
|
84
|
+
wcmd <= 0
|
85
|
+
hwack <= 1
|
86
|
+
end
|
87
|
+
wcmd <= 1
|
88
|
+
wdata <= target
|
89
|
+
blk.call if blk
|
90
|
+
else
|
91
|
+
# Different clk event, asynchrone case: perform a decoupled access.
|
92
|
+
top_block.unshift do
|
93
|
+
wcmd <= 0
|
94
|
+
hwack <= 0
|
95
|
+
end
|
96
|
+
seq do
|
97
|
+
hif(wack) do
|
98
|
+
blk.call if blk
|
99
|
+
end
|
100
|
+
helse { wcmd <= 1 }
|
101
|
+
wdata <= target
|
102
|
+
end
|
103
|
+
end
|
104
|
+
end
|
105
|
+
end
|
106
|
+
|
107
|
+
|
108
|
+
# Channel describing a register of +typ+ type.
|
109
|
+
channel(:register) do |typ|
|
110
|
+
# The register.
|
111
|
+
typ.inner :buffer
|
112
|
+
|
113
|
+
reader_input :buffer
|
114
|
+
|
115
|
+
# The read primitive.
|
116
|
+
reader do |blk,target|
|
117
|
+
target <= buffer
|
118
|
+
blk.call if blk
|
119
|
+
end
|
120
|
+
|
121
|
+
writer_output :buffer
|
122
|
+
|
123
|
+
# The read primitive.
|
124
|
+
writer do |blk,target|
|
125
|
+
buffer <= target
|
126
|
+
blk.call if blk
|
127
|
+
end
|
128
|
+
end
|
129
|
+
|
130
|
+
|
131
|
+
|
132
|
+
# Channel describing a handshake for transmitting data of +typ+ type, reset
|
133
|
+
# by +rst+
|
134
|
+
channel(:handshake) do |typ|
|
135
|
+
# The data signal.
|
136
|
+
typ.inner :data
|
137
|
+
# The request and acknowledge.
|
138
|
+
typ.inner :req, :ack
|
139
|
+
|
140
|
+
reader_input :ack, :data
|
141
|
+
reader_output :req
|
142
|
+
|
143
|
+
# The read primitive.
|
144
|
+
reader do |blk,target|
|
145
|
+
top_block.unshift do
|
146
|
+
req <= 0
|
147
|
+
end
|
148
|
+
hif(ack == 0) do
|
149
|
+
req <= 1
|
150
|
+
end
|
151
|
+
helsif(req) do
|
152
|
+
target <= data
|
153
|
+
req <= 0
|
154
|
+
blk.call if blk
|
155
|
+
end
|
156
|
+
end
|
157
|
+
|
158
|
+
writer_input :req
|
159
|
+
writer_output :ack, :data
|
160
|
+
|
161
|
+
# The read primitive.
|
162
|
+
writer do |blk,target|
|
163
|
+
top_block.unshift do
|
164
|
+
ack <= 0
|
165
|
+
end
|
166
|
+
hif(req) do
|
167
|
+
hif(~ack) do
|
168
|
+
data <= target
|
169
|
+
blk.call if blk
|
170
|
+
end
|
171
|
+
ack <= 1
|
172
|
+
end
|
173
|
+
end
|
174
|
+
end
|
175
|
+
|
176
|
+
|
177
|
+
# $mode = :sync
|
178
|
+
# $mode = :nsync
|
179
|
+
# $mode = :async
|
180
|
+
# $mode = :proco # Producter / Consummer
|
181
|
+
# $channel = :register
|
182
|
+
# $channel = :handshake
|
183
|
+
# $channel = :queue
|
184
|
+
|
185
|
+
# The configuration scenarii
|
186
|
+
$scenarii = [ [:sync, :register], [:sync, :handshake], [:sync, :queue],
|
187
|
+
[:nsync, :register], [:nsync, :handshake], [:nsync, :queue],
|
188
|
+
[:async, :register], [:async, :handshake], [:async, :queue],
|
189
|
+
[:proco, :register], [:proco, :handshake], [:proco, :queue] ]
|
190
|
+
|
191
|
+
# The configuration
|
192
|
+
$mode, $channel = $scenarii[11]
|
193
|
+
|
194
|
+
# Testing the queue channel.
|
195
|
+
system :test_queue do
|
196
|
+
inner :clk, :rst, :clk2, :clk3
|
197
|
+
[8].inner :idata, :odata
|
198
|
+
[4].inner :counter
|
199
|
+
|
200
|
+
if $channel == :register then
|
201
|
+
register(bit[8]).(:my_ch)
|
202
|
+
elsif $channel == :handshake then
|
203
|
+
handshake(bit[8],rst).(:my_ch)
|
204
|
+
elsif $channel == :queue then
|
205
|
+
queue(bit[8],5,clk,rst).(:my_ch)
|
206
|
+
end
|
207
|
+
|
208
|
+
ev = $mode == :sync ? clk.posedge :
|
209
|
+
$mode == :nsync ? clk.negedge : clk2.posedge
|
210
|
+
|
211
|
+
if $mode != :proco then
|
212
|
+
# Sync/Neg sync and async tests mode
|
213
|
+
par(ev) do
|
214
|
+
hif(rst) do
|
215
|
+
counter <= 0
|
216
|
+
idata <= 0
|
217
|
+
odata <= 0
|
218
|
+
end
|
219
|
+
helse do
|
220
|
+
hif (counter < 4) do
|
221
|
+
my_ch.write(idata) do
|
222
|
+
idata <= idata + 1
|
223
|
+
counter <= counter + 1
|
224
|
+
end
|
225
|
+
end
|
226
|
+
helsif ((counter > 10) & (counter < 15)) do
|
227
|
+
my_ch.read(odata) do
|
228
|
+
idata <= idata - odata
|
229
|
+
counter <= counter + 1
|
230
|
+
end
|
231
|
+
end
|
232
|
+
helse do
|
233
|
+
counter <= counter + 1
|
234
|
+
end
|
235
|
+
end
|
236
|
+
end
|
237
|
+
else
|
238
|
+
# Producter/consumer mode
|
239
|
+
# Producer
|
240
|
+
par(clk2.posedge) do
|
241
|
+
hif(rst) do
|
242
|
+
idata <= 0
|
243
|
+
end
|
244
|
+
helse do
|
245
|
+
my_ch.write(idata) do
|
246
|
+
idata <= idata + 1
|
247
|
+
end
|
248
|
+
end
|
249
|
+
end
|
250
|
+
# Consumer
|
251
|
+
par(clk3.posedge) do
|
252
|
+
hif(rst) do
|
253
|
+
counter <= 0
|
254
|
+
end
|
255
|
+
helse do
|
256
|
+
my_ch.read(odata) do
|
257
|
+
counter <= counter + 1
|
258
|
+
end
|
259
|
+
end
|
260
|
+
end
|
261
|
+
end
|
262
|
+
|
263
|
+
timed do
|
264
|
+
clk <= 0
|
265
|
+
clk2 <= 0
|
266
|
+
clk3 <= 0
|
267
|
+
rst <= 0
|
268
|
+
!10.ns
|
269
|
+
clk <= 1
|
270
|
+
!10.ns
|
271
|
+
clk <= 0
|
272
|
+
rst <= 1
|
273
|
+
!3.ns
|
274
|
+
clk2 <= 1
|
275
|
+
!3.ns
|
276
|
+
clk3 <= 0
|
277
|
+
!4.ns
|
278
|
+
clk <= 1
|
279
|
+
!10.ns
|
280
|
+
clk <= 0
|
281
|
+
!3.ns
|
282
|
+
clk2 <= 0
|
283
|
+
!3.ns
|
284
|
+
clk3 <= 1
|
285
|
+
!2.ns
|
286
|
+
rst <= 0
|
287
|
+
!2.ns
|
288
|
+
64.times do
|
289
|
+
clk <= 1
|
290
|
+
!10.ns
|
291
|
+
clk <= 0
|
292
|
+
!3.ns
|
293
|
+
clk2 <= ~clk2
|
294
|
+
!3.ns
|
295
|
+
hif (clk2 == 0) { clk3 <= ~ clk3 }
|
296
|
+
!4.ns
|
297
|
+
end
|
298
|
+
end
|
299
|
+
end
|
300
|
+
|
data/lib/HDLRuby/hdrcc.rb
CHANGED
@@ -269,6 +269,9 @@ $optparse = OptionParser.new do |opts|
|
|
269
269
|
$options[:multiple] = v
|
270
270
|
$options[:sim] = v
|
271
271
|
end
|
272
|
+
opts.on("--vcd", "The simulator will generate a vcd file") do |v|
|
273
|
+
$options[:vcd] = v
|
274
|
+
end
|
272
275
|
opts.on("-v", "--verilog","Output in Verlog HDL format") do |v|
|
273
276
|
$options[:verilog] = v
|
274
277
|
$options[:multiple] = v
|
@@ -515,9 +518,15 @@ elsif $options[:clang] then
|
|
515
518
|
# Generate the code for it.
|
516
519
|
$main = File.open($name,"w")
|
517
520
|
|
521
|
+
# Select the vizualizer depending on the options.
|
522
|
+
init_visualizer = $options[:vcd] ? "init_vcd_visualizer" :
|
523
|
+
"init_default_visualizer"
|
524
|
+
|
518
525
|
# Generate the code of the main function.
|
519
526
|
# HDLRuby start code
|
520
|
-
$main << HDLRuby::Low::Low2C.main(
|
527
|
+
$main << HDLRuby::Low::Low2C.main("hruby_simulator",
|
528
|
+
init_visualizer,
|
529
|
+
$top_system,
|
521
530
|
$top_system.each_systemT_deep.to_a.reverse,$hnames)
|
522
531
|
$main.close
|
523
532
|
|
data/lib/HDLRuby/hruby_bstr.rb
CHANGED
@@ -35,10 +35,13 @@ module HDLRuby
|
|
35
35
|
# Maybe str is an numeric.
|
36
36
|
if str.is_a?(Numeric) then
|
37
37
|
# Yes, convert it to a binary string.
|
38
|
-
|
38
|
+
num = str
|
39
|
+
str = num.to_s(2)
|
39
40
|
# And fix the sign.
|
40
41
|
if str[0] == "-" then
|
41
|
-
str = str[1..-1]
|
42
|
+
# str = str[1..-1]
|
43
|
+
str = (2**str.size+num).to_s(2)
|
44
|
+
puts "str=#{str}"
|
42
45
|
sign = "-"
|
43
46
|
else
|
44
47
|
sign = "+"
|