HDLRuby 2.3.2 → 2.3.7
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- checksums.yaml +4 -4
- data/README.md +19 -13
- data/lib/HDLRuby/hdr_samples/with_channel.rb +49 -8
- data/lib/HDLRuby/hdr_samples/with_linear.rb +33 -25
- data/lib/HDLRuby/hdrcc.rb +5 -6
- data/lib/HDLRuby/hruby_high.rb +6 -3
- data/lib/HDLRuby/hruby_low.rb +19 -0
- data/lib/HDLRuby/hruby_low2c.rb +3 -1
- data/lib/HDLRuby/hruby_low_without_connection.rb +13 -0
- data/lib/HDLRuby/hruby_tools.rb +2 -2
- data/lib/HDLRuby/sim/hruby_sim.h +6 -2
- data/lib/HDLRuby/sim/hruby_sim_calc.c +25 -12
- data/lib/HDLRuby/sim/hruby_sim_core.c +12 -4
- data/lib/HDLRuby/std/channel.rb +567 -164
- data/lib/HDLRuby/std/memory.rb +3 -3
- data/lib/HDLRuby/version.rb +1 -1
- metadata +2 -2
data/lib/HDLRuby/std/memory.rb
CHANGED
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@@ -568,7 +568,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
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568
568
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# using +target+ as target of access result.
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569
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writer do |blk,target|
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570
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# On reset the read trigger is 0.
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571
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-
rst
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571
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+
rst = send(rst_name)
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572
572
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top_block.unshift do
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573
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# Initialize the address so that the next access is at address 0.
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hif(rst == 1) { abus_w <= -1 }
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@@ -889,11 +889,11 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
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889
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rst_name = br_rsts[:winc].to_sym
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else
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rst_name = rst.name
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892
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-
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892
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+
writer_input rst_name
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893
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end
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# Declares the address counter.
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[size.width-1].inner :abus_w
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896
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-
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896
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+
writer_inout :abus_w
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897
897
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# Defines the write procedure at address +addr+
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# using +target+ as target of access result.
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data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
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@@ -1,14 +1,14 @@
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1
1
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--- !ruby/object:Gem::Specification
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2
2
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name: HDLRuby
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3
3
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version: !ruby/object:Gem::Version
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4
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-
version: 2.3.
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4
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+
version: 2.3.7
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5
5
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platform: ruby
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6
6
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authors:
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7
7
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- Lovic Gauthier
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8
8
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autorequire:
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bindir: exe
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10
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cert_chain: []
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11
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-
date: 2020-
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11
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+
date: 2020-09-06 00:00:00.000000000 Z
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12
12
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dependencies:
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- !ruby/object:Gem::Dependency
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name: bundler
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