HDLRuby 2.3.2 → 2.3.7

checksums.yaml

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data/README.md

@@ -2815,27 +2815,17 @@ This library provides a unified interface to complex communication protocols thr
 ### Using a channel
 
 A channel is used similarly to a pipe: it has an input where data can be written and an output where data can be read. The ordering of the data and the synchronization depend on the internals of the channel, e.g., a channel can be FIFO or LIFO. The interaction with the channel is done using the following methods:
- 
- * `input <name>`: generate ports in the system for reading from the channel amd associate them to `name`
- * `output <name>`: generate ports in the system for writing to the channel and associate them to `name`
- * `inout <name>`: generate ports in the system for reading and writing to the channel and associate them to `name`
- * `inner <name>`: generates inner signals for accessing directly the channel
-
-__Note__: `input`, `output`, `inout` and `inner` for channels work similarly to the ones of data types for declaring signals. In particular, `input`, `output` and `inout` are to be used in systems that do not include the channel and `inner` is to be used in the system that include the channel.
-
-When the channel ports are declared, they can be accessed using the following methods depending on whether they are writing or reading ports:
 
  * `write(<args>) <block>`: write to the channel and execute `block` when `write` completes. `args` is a list of arguments required for performing the write that depend on the channel.
  * `read(<args>) <block>`: read the channel and execute `block` when the read completes. `args` is a list of arguments required for performing the write that depend on the channel.
 
+
 For example, a system sending successive 8-bit values through a channel can be described as follows:
 
 ```ruby
 system :producer8 do |channel|
     # Inputs of the producer: clock and reset.
     input :clk, :rst
-    # Instantiate the channel ports
-    channel.output :chi
     # Inner 8-bit counter for generating values.
     [8].inner :counter
 
@@ -2843,7 +2833,7 @@ system :producer8 do |channel|
     par(clk.posedge) do
         hif(rst) { counter <= 0 }
         helse do
-            chi.write(counter) { counter <= counter + 1 }
+            channel.write(counter) { counter <= counter + 1 }
         end
     end
 end
@@ -2851,6 +2841,22 @@ end
 
 __Note__: In the code above, the channel is passed as generic argument of the system.
 
+The access points to a channel can also be handled individually by declaring ports using the following methods:
+ 
+ * `input <name>`: declares a port for reading from the channel and associate them to `name` if any
+ * `output <name>`: declares a port for writing to the channel and associate them to `name` if any
+ * `inout <name>`: declares a port for reading and writing to the channel and associate them to `name` if any
+
+Such port can then be accessed using the same `read` and `write` method of a channel, the difference being that they can also be configured for new access procedure using the `wrap` method:
+
+ * `wrap(<args>) <code>`: creates a new port whose read or write procedure has the elements of `<args>` and the ones produced by `<code>` assign to the arguments of the read or write procedure.
+
+For example, assuming `mem` is a channel whose read and write access have as argument the target address and data signals, the following code creates a port for always accessing at address 0:
+
+```ruby
+  addr0 = channel.input.wrap(0) 
+```
+
 ### Channel branches
 
 Some channel may include several branches, they are accessed by name using the following method:
@@ -2894,7 +2900,7 @@ Where `name` is the name of the channel and `block` is a procedure block describ
  The first argument of the block must be the following:
    - `blk`: the block to execute when the write completes.
  Other arguments can be freely defined, and will be required by the `write` command.
- * `brancher(name) <block>`: defines branch named +name+ described in `block`. The content of block can be any content valid for a channel, with the additional possiblity to access the internals of the upper channel.
+ * `brancher(name) <block>`: defines branch named +name+ described in `block`. The content of block can be any content valid for a channel, with the additional possibility to access the internals of the upper channel.
 
 For example, a channel implemented by a simple register of generic type `typ`, that can be set to 0 using the `reset` command can be described as follows:
 

data/lib/HDLRuby/hdr_samples/with_channel.rb

@@ -63,12 +63,13 @@ end
 
 
 # A system writing indefinitely to a channel.
+# Checking usage of channel without declaring a port.
 system :producer8 do |channel|
-    # puts "channel=#{channel}"
+    # puts "channel=#{channel}, channel methods=#{channel.methods}"
     # Inputs of the producer: clock and reset.
     input :clk, :rst
-    # Instantiate the channel ports
-    channel.output :ch
+    # # Instantiate the channel ports
+    # channel.output :ch
     # Inner 8-bit counter for generating values.
     [8].inner :counter
 
@@ -76,7 +77,8 @@ system :producer8 do |channel|
     par(clk.posedge) do
         hif(rst) { counter <= 0 }
         helse do
-            ch.write(counter) { counter <= counter + 1 }
+            # ch.write(counter) { counter <= counter + 1 }
+            channel.write(counter) { counter <= counter + 1 }
         end
     end
 end
@@ -96,20 +98,59 @@ system :consummer8 do |channel|
     end
 end
 
+# A system reading indefinitely from a channel.
+# Version without port declaration.
+system :consummer16 do |channel|
+    # Input of the consummer: a clock is enough.
+    input :clk
+    # # Instantiate the channel ports
+    # channel.input :ch
+    # Inner buffer for storing the cunsummed value.
+    [16].inner :buf
+
+    # The value consumption process
+    par(clk.posedge) do
+        # ch.read(buf)
+        channel.read(buf)
+    end
+end
+
 
 # A system testing the handshaker.
 system :hs_test do
     input :clk,:rst
 
-    # Declares the handshaker
-    handshaker([8]).(:hs)
+    # Declares two handshakers
+    handshaker([8]).(:hs0)
+    handshaker([16]).(:hs1)
 
     # # Sets the reset.
     # par(rst.posedge) { hs.reset }
+    
+    # For the first handshake
 
     # Instantiate the producer.
-    producer8(hs).(:producerI).(clk,rst)
+    producer8(hs0).(:producerI).(clk,rst)
 
     # Instantiate the consummer.
-    consummer8(hs).(:consummerI).(clk)
+    consummer8(hs0).(:consummerI).(clk)
+
+    # For the second handshaker
+    
+    # Instantiatethe consummer.
+    consummer16(hs1).(:consummer2I).(clk)
+
+    # Produce from within.
+    [16].inner :counter
+
+    # hs1.output :port
+
+    par(clk.posedge) do
+       hif(rst) { counter <= 0 }
+        helse do
+            # port.write(counter) { counter <= counter + 1 }
+            hs1.write(counter) { counter <= counter + 1 }
+        end
+    end
+
 end

data/lib/HDLRuby/hdr_samples/with_linear.rb

@@ -22,23 +22,26 @@ system :testmat do
     mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memL1)
     mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memR)
     # Access ports.
-    memL0.branch(:rinc).inner :readL0
-    memL1.branch(:rinc).inner :readL1
-    memR.branch(:rinc).inner :readR
+    # memL0.branch(:rinc).input :readL0
+    # memL1.branch(:rinc).input :readL1
+    # memR.branch(:rinc).input :readR
 
     # Prepares the left and acc arrays.
-    lefts = [readL0, readL1]
+    # lefts = [readL0, readL1]
+    lefts = [memL0.branch(:rinc), memL1.branch(:rinc)]
 
     # Accumulators memory.
     mem_file([8],2,clk,rst,rinc: :rst).(:memAcc)
-    memAcc.branch(:anum).inner :accs
-    accs_out = [accs.wrap(0), accs.wrap(1)]
+    # memAcc.branch(:anum).inout :accs
+    # accs_out = [accs.wrap(0), accs.wrap(1)]
+    accs_out = [memAcc.branch(:anum).wrap(0), memAcc.branch(:anum).wrap(1)]
 
     # Layer 0 ack.
     inner :ack0
     
     # Instantiate the matrix product.
-    mac_n1([8],clk,req,ack0,lefts,readR,accs_out)
+    # mac_n1([8],clk,req,ack0,lefts,readR,accs_out)
+    mac_n1([8],clk,req,ack0,lefts,memR.branch(:rinc),accs_out)
 
     # Translation.
     # Translation memory.
@@ -46,10 +49,10 @@ system :testmat do
     # Tarnslation result
     mem_file([8],2,clk,rst,rinc: :rst).(:memF)
     # Access ports.
-    memT.branch(:anum).inner :readT
-    memF.branch(:anum).inner :writeF
+    memT.branch(:anum).input :readT
+    memF.branch(:anum).output :writeF
     regRs = [ readT.wrap(0), readT.wrap(1) ]
-    regLs = [ accs.wrap(0), accs.wrap(1) ]
+    regLs = accs_out
     regs =  [ writeF.wrap(0), writeF.wrap(1) ]
 
     # Translater ack.
@@ -64,9 +67,8 @@ system :testmat do
     # Input memories.
     mem_dual([8],2,clk,rst, rinc: :rst,winc: :rst).(:mem2L0)
     # Access ports.
-    mem2L0.branch(:rinc).inner :read2L0
-    # memAcc.branch(:rinc).inner :accsR
-    memF.branch(:rinc).inner :readF
+    # mem2L0.branch(:rinc).input :read2L0
+    # memF.branch(:rinc).input :readF
 
     # Second layer ack.
     inner :ack1
@@ -76,29 +78,35 @@ system :testmat do
 
     sub do
         # Instantiate the second matrix product.
-        # mac([8],clk,req,read2L0,accsR,res)
-        mac([8],clk,ackT,ack1,read2L0,readF,channel_port(res))
+        # mac([8],clk,ackT,ack1,read2L0,readF,channel_port(res))
+        mac([8],clk,ackT,ack1,mem2L0.branch(:rinc),memF.branch(:rinc),
+            channel_port(res))
     end
 
 
 
     # The memory initializer.
-    memL0.branch(:winc).inner :writeL0
-    memL1.branch(:winc).inner :writeL1
-    memR.branch(:winc).inner :writeR
-    memT.branch(:winc).inner :writeT
-    mem2L0.branch(:winc).inner :write2L0
+    # memL0.branch(:winc).output :writeL0
+    # memL1.branch(:winc).output :writeL1
+    # memR.branch(:winc).output :writeR
+    # mem2L0.branch(:winc).output :write2L0
+    # memT.branch(:winc).output :writeT
     inner :fill, :fill2
     [8].inner :val
     par(clk.posedge) do
         hif(fill) do
-            writeL0.write(val)
-            writeL1.write(val+1)
-            writeR.write(val+1)
+            # writeL0.write(val)
+            # writeL1.write(val+1)
+            # writeR.write(val+1)
+            memL0.branch(:winc).write(val)
+            memL1.branch(:winc).write(val+1)
+            memR.branch(:winc).write(val+1)
         end
         hif(fill2) do
-            write2L0.write(val+2)
-            writeT.write(val+2)
+            # write2L0.write(val+2)
+            # writeT.write(val+2)
+            mem2L0.branch(:winc).write(val+2)
+            memT.branch(:winc).write(val+2)
         end
     end
 

data/lib/HDLRuby/hdrcc.rb

@@ -241,7 +241,7 @@ include HDLRuby
 # Process the command line options
 $options = {}
 $optparse = OptionParser.new do |opts|
-    opts.banner = "Usage: hdrcc.rb [options] <input file> [<output file>]"
+    opts.banner = "Usage: hdrcc.rb [options] <input file> [<output directory or file>]"
 
     opts.separator ""
     opts.separator "Where:"
@@ -323,18 +323,17 @@ $optparse = OptionParser.new do |opts|
     opts.separator ""
     opts.separator "Notice:"
     opts.separator "* If no output option is given, simply checks the input file"
-    opts.separator "* If no output file is given, the result is given through the standard output."
     opts.separator "* If no top system is given, it will be automatically searched in the input file."
     opts.separator ""
     opts.separator "Examples:"
     opts.separator "* Compile system named `adder` from `adder.rb` input file and generate `adder.yaml` low-level YAML description:"
     opts.separator "   hdrcc.rb --yaml --top adder adder.rb adder.yaml"
-    opts.separator "* Compile `adder.rb` input file and generate `adder.vhd` low-level VHDL description:"
-    opts.separator "   hdrcc.rb --vhdl adder.rb adder.vhd"
+    opts.separator "* Compile `adder.rb` input file and generate low-level VHDL description files in `adder_vhd` directory:"
+    opts.separator "   hdrcc.rb --vhdl adder.rb adder_vhd"
     opts.separator "* Check the validity of `adder.rb` input file:"
     opts.separator "   hdrcc.rb adder.rb"
-    opts.separator "* Compile system `adder` whose bit width is generic from `adder_gen.rb` input file to a 16-bit circuit whose low-level Verilog HDL description is dumped to the standard output:"
-    opts.separator "   hdrcc -v -t adder --param 16 adder_gen.rb"
+    opts.separator "* Compile system `adder` whose bit width is generic from `adder_gen.rb` input file to a 16-bit circuit whose low-level Verilog HDL description files are put in `adder_gen_v` directory:"
+    opts.separator "   hdrcc -v -t adder --param 16 adder_gen.rb adder_gen_v"
     opts.separator "* Compile system `multer` with inputs and output bit width is generic from `multer_gen.rb` input file to a 16x16->32 bit cicruit whose low-level YAML description is saved to output file `multer_gen.yaml`"
     opts.separator "hdrcc -y -t multer -p 16,16,32 multer_gen.rb multer_gen.yaml"
 

data/lib/HDLRuby/hruby_high.rb

@@ -1263,7 +1263,8 @@ module HDLRuby::High
         # Converts the scope to HDLRuby::Low.
         def to_low()
             # Create the resulting low scope.
-            scopeLow = HDLRuby::Low::Scope.new()
+            # scopeLow = HDLRuby::Low::Scope.new()
+            scopeLow = HDLRuby::Low::Scope.new(self.name)
             # Push the private namespace for the low generation.
             High.space_push(@namespace)
             # Pushes on the name stack for converting the internals of
@@ -1858,7 +1859,8 @@ module HDLRuby::High
     def function(name, &ruby_block)
         if HDLRuby::High.in_system? then
             define_singleton_method(name.to_sym) do |*args,&other_block|
-                sub do
+                # sub do
+                sub(HDLRuby.uniq_name(name)) do
                     HDLRuby::High.top_user.instance_exec(*args,*other_block,
                                                          &ruby_block)
                     # ruby_block.call(*args)
@@ -1866,7 +1868,8 @@ module HDLRuby::High
             end
         else
             define_method(name.to_sym) do |*args,&other_block|
-                sub do
+                # sub do
+                sub(HDLRuby.uniq_name(name)) do
                     HDLRuby::High.top_user.instance_exec(*args,*other_block,
                                                          &ruby_block)
                 end

data/lib/HDLRuby/hruby_low.rb

@@ -1123,6 +1123,10 @@ module HDLRuby::Low
             return self.parent.is_a?(SystemT) ? self : self.parent.top_scope
         end
 
+        # Gets the parent system, i.e., the parent of the top scope.
+        def parent_system
+            return self.top_scope.parent
+        end
 
     end
 
@@ -2132,6 +2136,11 @@ module HDLRuby::Low
         def top_scope
             return parent.top_scope
         end
+
+        # Gets the parent system, i.e., the parent of the top scope.
+        def parent_system
+            return self.top_scope.parent
+        end
     end
 
 
@@ -2619,6 +2628,11 @@ module HDLRuby::Low
         def top_scope
             return self.scope.top_scope
         end
+
+        # Gets the parent system, i.e., the parent of the top scope.
+        def parent_system
+            return self.top_scope.parent
+        end
     end
 
 
@@ -3717,6 +3731,11 @@ module HDLRuby::Low
         def top_scope
             return self.parent.is_a?(Scope) ? self.parent : self.parent.top_scope
         end
+
+        # Gets the parent system, i.e., the parent of the top scope.
+        def parent_system
+            return self.top_scope.parent
+        end
     end
 
 

data/lib/HDLRuby/hruby_low2c.rb

@@ -1946,7 +1946,9 @@ module HDLRuby::Low
         # Generates the C text for reference as left value to a signal.
         # +level+ is the hierarchical level of the object.
         def to_c_signal(level = 0)
-            return to_c(level,true)
+            # return to_c(level,true)
+            return "make_ref_rangeS(#{self.ref.to_c_signal(level)}," +
+                "value2integer(#{self.range.first.to_c(level)}),value2integer(#{self.range.last.to_c(level)}))"
         end
     end
 

data/lib/HDLRuby/hruby_low_without_connection.rb

@@ -29,6 +29,7 @@ module HDLRuby::Low
                 if scope.each_connection.to_a.any? then
                     inputs_blk = Block.new(:par)
                     outputs_blk = Block.new(:par)
+                    timed_blk = TimeBlock.new(:seq)
                     scope.each_connection do |connection|
                         # Check the left and right of the connection
                         # for input or output port.
@@ -40,6 +41,15 @@ module HDLRuby::Low
                         right_r = right.resolve if right.respond_to?(:resolve)
                         # puts "right_r=#{right_r.name}" if right_r
                         # puts "right_r.parent=#{right_r.parent.name}" if right_r && right_r.parent
+                        if right.is_a?(Value) then
+                            # Right is value, the new transmit is to add
+                            # to the timed block.
+                            timed_blk.add_statement(
+                                Transmit.new(left.clone,right.clone))
+                            # No more process for this connection.
+                            next
+                        end
+
                         # Check if left is an input or an output.
                         left_is_i = left_is_o = false
                         if left_r && left_r.parent.is_a?(SystemT) then
@@ -118,6 +128,9 @@ module HDLRuby::Low
                     if outputs_blk.each_statement.any? then
                         scope.add_behavior(Behavior.new(outputs_blk))
                     end
+                    if timed_blk.each_statement.any? then
+                        scope.add_behavior(TimeBehavior.new(timed_blk))
+                    end
                 end
             end
         end

data/lib/HDLRuby/hruby_tools.rb

@@ -13,9 +13,9 @@ module HDLRuby
     @@absoluteCounter = -1 # The absolute name counter.
 
     # Generates an absolute uniq name.
-    def self.uniq_name
+    def self.uniq_name(base = "")
         @@absoluteCounter += 1
-        name = ":#{@@absoluteCounter}"
+        name = base.to_s + ":#{@@absoluteCounter}"
         if Symbol.all_symbols.find {|symbol| symbol.to_s == name } then
             # The symbol exists, try again.
             return self.uniq_name

data/lib/HDLRuby/sim/hruby_sim.h

@@ -612,14 +612,18 @@ extern Value read_range(Value value, long long first, long long last,
  *  @param src the source value
  *  @param first the first index of the range
  *  @param last the last index of the range
+ *  @param base the type of the elements
  *  @param dst the destination value
  *  @return dst */
-extern Value write_range(Value src, long long first, long long last, Value dst);
+extern Value write_range(Value src, long long first, long long last, 
+        Type base, Value dst);
 
 /** Writes to a range within a value but without overwrite with Z. 
  *  @param src the source value
  *  @param first the first index of the range
  *  @param last the last index of the range
+ *  @param base the type of the elements
  *  @param dst the destination value
  *  @return dst */
-extern Value write_range_no_z(Value src, long long first, long long last, Value dst);
+extern Value write_range_no_z(Value src, long long first, long long last,
+        Type base, Value dst);