HDLRuby 2.2.17 → 2.3.4

data/lib/HDLRuby/std/fixpoint.rb

@@ -15,50 +15,53 @@ module HDLRuby::High::Std
     def self.included(base)
         # Performs the previous included
         res = self.send(:_included_fixpoint,base)
-        # Now modify the Type class
-        ::HDLRuby::High::Type.class_eval do
-            # Saves the former type generation method.
-            alias_method :"_[]_fixpoint", :[]
+        # Now modify the Type class if not already modified.
+        unless ::HDLRuby::High::Type.instance_methods.include?(:"_[]_fixpoint") then
+            ::HDLRuby::High::Type.class_eval do
+                # Saves the former type generation method.
+                alias_method :"_[]_fixpoint", :[]
 
-            # Redefine the type generation method for supporting fixed point
-            # type generation.
-            def [](*args)
-                if args.size == 1 then
-                    return self.send(:"_[]_fixpoint",*args)
-                else
-                    # Handle the arguments.
-                    arg0,arg1 = *args
-                    if arg0.respond_to?(:to_i) then
-                        arg0 = (arg0.to_i.abs-1)..0
-                    end
-                    if arg1.respond_to?(:to_i) then
-                        arg1 = (arg1.to_i.abs-1)..0
-                    end
-                    # Compute the fix point sizes.
-                    isize = (arg0.first-arg0.last).abs+1
-                    fsize = (arg1.first-arg1.last).abs+1
-                    # Build the type.
-                    case(self.name)
-                    when :bit
-                        typ = bit[isize+fsize].typedef(::HDLRuby.uniq_name)
-                    when :unsigned
-                        typ = unsigned[isize+fsize].typedef(::HDLRuby.uniq_name)
-                    when :signed
-                        typ = signed[isize+fsize].typedef(::HDLRuby.uniq_name)
+                # Redefine the type generation method for supporting fixed point
+                # type generation.
+                def [](*args)
+                    if args.size == 1 then
+                        return self.send(:"_[]_fixpoint",*args)
                     else
-                        raise "Invalid type for generating a fixed point type: #{self.name}"
-                    end
-                    # Redefine the multiplication and division for fixed point.
-                    typ.define_operator(:*) do |left,right|
-                        (left.as([isize+fsize*2])*right) >> fsize
-                    end
-                    typ.define_operator(:/) do |left,right|
-                        (left.as([isize+fsize*2]) << fsize) / right
+                        # Handle the arguments and compute the fix point sizes.
+                        arg0,arg1 = *args
+                        if arg0.respond_to?(:to_i) then
+                            isize = arg0
+                        else
+                            isize = (arg0.first-arg0.last).abs+1
+                        end
+                        if arg1.respond_to?(:to_i) then
+                            fsize = arg1
+                        else
+                            fsize = (arg1.first-arg1.last).abs+1
+                        end
+                        # Build the type.
+                        case(self.name)
+                        when :bit
+                            typ = bit[isize+fsize].typedef(::HDLRuby.uniq_name)
+                        when :unsigned
+                            typ = unsigned[isize+fsize].typedef(::HDLRuby.uniq_name)
+                        when :signed
+                            typ = signed[isize+fsize].typedef(::HDLRuby.uniq_name)
+                        else
+                            raise "Invalid type for generating a fixed point type: #{self.name}"
+                        end
+                        # Redefine the multiplication and division for fixed point.
+                        typ.define_operator(:*) do |left,right|
+                            (left.as([isize+fsize*2])*right) >> fsize
+                        end
+                        typ.define_operator(:/) do |left,right|
+                            (left.as([isize+fsize*2]) << fsize) / right
+                        end
+                        typ
                     end
-                    typ
                 end
+                return res
             end
-            return res
         end
     end
 

data/lib/HDLRuby/std/linear.rb

@@ -244,6 +244,74 @@ module HDLRuby::High::Std
     end
 
 
+    # Declares a simple pipelined multiple mac with single right data.
+    #
+    # Can be used for the product of a martix-vector product.
+    function :mac_np do |typ,ev,req,ack,lefts, rights, last,
+        mul = proc { |x,y| x*y }, add = proc { |x,y| x+y }|
+        # Ensure ev is really an event.
+        ev = ev.posedge unless ev.is_a?(Event)
+        # Ensures lefts is an array.
+        lefts = lefts.to_a
+        # Ensures rights is an array.
+        rights = rights.to_a
+        # Get the size of the pipeline and ensure lefts and rights have the
+        # same.
+        size = lefts.size
+        if (rights.size != size) then
+            raise "Incompatible lefts and rights sizes: lefts size is #{size} and rights size is #{rights.size}"
+        end
+        # Declares the accumulators.
+        accs = size.times.map { |i| typ.inner :"acc#{i}" }
+        # Left value and right value.
+        lvs = lefts.each_with_index.map { |left,i| typ.inner :"lv#{i}" }
+        rvs = rights.each_with_index.map { |right,i| typ.inner :"rv#{i}" }
+        # typ.inner :rv
+        # lv and rv are valid.
+        lvoks = lefts.each_with_index.map { |left,i| inner :"lvok#{i}" }
+        # inner :rvok
+        rvoks = rights.each_with_index.map { |right,i| inner :"rvok#{i}" }
+        # Run flag
+        inner :run
+        par(ev) do
+            ack <= 0
+            run <= 0
+            hif(req | run) do
+                run <= 1
+                # Computation request.
+                lefts.zip(rights).each_with_index do |(left,right),i|
+                    left.read(lvs[i])  { lvoks[i] <= 1 }
+                    right.read(rvs[i]) { rvoks[i] <= 1 }
+                    hif(lvoks[i] & rvoks[i]) do
+                        ack <= 1
+                        run <= 0
+                        if (i < lefts.size-1) then
+                            if (i>0) then 
+                                accs[i] <= add.(accs[i],mul.(lvs[i],rvs[i])) +
+                                    accs[i-1]
+                            else
+                                accs[i] <= add.(accs[i],mul.(lvs[i],rvs[i]))
+                            end
+                        else
+                            # The last is reached
+                            seq do
+                                accs[i] <= add.(accs[i],mul.(lvs[i],rvs[i]))
+                                last.write(accs[i])
+                            end
+                        end
+                    end
+                end
+            end
+            helse do
+                lefts.each_with_index do |left,i|
+                    lvoks[i] <= 0
+                    rvoks[i] <= 0
+                    accs[i] <= 0
+                end
+            end
+        end
+    end
+
 
 
 end

data/lib/HDLRuby/std/loop.rb

@@ -0,0 +1,101 @@
+require 'std/task.rb'
+
+
+
+##
+# Standard HDLRuby::High library: loops encapsulated in tasks.
+# 
+########################################################################
+
+## While loop: loops until +condition+ is met execution +ruby_block+.
+#  The loop is synchronized on +clk_e+ and initialized by +init+.
+#  If +condition+ is nil, then +init+ is used as +condition+.
+HDLRuby::High::Std.task(:while_task) do |clk_e, init, condition, ruby_block|
+    # Ensure clk_e is an event, if not set it to a positive edge.
+    clk_e = clk_e.posedge unless clk_e.is_a?(Event)
+
+    # Ensures there is a condition.
+    unless condition then
+        condition = init
+        init = nil
+    end
+
+    # Transform condition into a proc if it is not the case.
+    unless condition.is_a?(Proc) then
+        condition_expr = condition
+        condition = proc { condition_expr }
+    end
+
+    # Ensures init to be a proc if not nil
+    init = init.to_proc unless init == nil
+
+    # Declares the signals for controlling the loop.
+    inner :req  # Signal to set to 1 for running the loop.
+
+    # Declares the runner signals.
+    runner_output :req
+
+    par(clk_e) do
+        # Performs the loop.
+        hif(req) do
+            # By default the loop is not finished.
+            # If the condition is still met go on looping.
+            hif(condition.call,&ruby_block)
+        end
+        # # if (init) then
+        # #     # There is an initialization, do it when there is no req.
+        # #     helse do
+        # #         init.call
+        # #     end
+        # # end
+    end
+
+    # The code for reseting the task.
+    if (init) then
+        # reseter(&init)
+        reseter do
+            req <= 0
+            init.call
+        end
+    end
+
+    # The code for running the task.
+    runner do
+        # top_block.unshift { req <= 0 }
+        req <= 1
+    end
+
+    # The code for checking the end of execution.
+    finisher do |blk|
+        hif(~condition.call,&blk)
+    end
+
+end
+
+
+
+## A simplified loop: loops until +condition+ is met execution +ruby_block+.
+#  The loop is synchronized on +clk_e+ and initialized by +init+.
+#  If +condition+ is nil, then +init+ is used as +condition+.
+def while_loop(clk_e, init, condition = nil, &ruby_block)
+    # Create the loop task.
+    tsk = while_task(clk_e,init,condition,ruby_block).(HDLRuby.uniq_name)
+    # Create the inner access port.
+    prt = tsk.inner HDLRuby.uniq_name
+    # Return the access port.
+    return prt
+end
+
+## Loop +num+ times executing +ruby_block+.
+#  The loop is synchronized on +clk_e+.
+def times_loop(clk_e, num, &ruby_block)
+    # Compute the width of the counter.
+    width = num.respond_to?(:width) ? num.width : num.type.width
+    # Declares the counter.
+    cnt = [width].inner(HDLRuby.uniq_name)
+    # Create the loop.
+    return while_loop(clk_e, proc{cnt<=0}, cnt<num) do
+        cnt <= cnt + 1
+        ruby_block.call
+    end
+end

data/lib/HDLRuby/std/memory.rb

@@ -170,6 +170,187 @@ HDLRuby::High::Std.channel(:mem_sync) do |n,typ,size,clk_e,rst,br_rsts = []|
 end
 
 
+# Flexible ROM memory of +size+ elements of +typ+ typ, syncrhonized on +clk+
+# (positive and negative edges) and reset on +rst+.
+# At each rising edge of +clk+ a read and a write is guaranteed to be
+# completed provided they are triggered.
+# +br_rsts+ are reset names on the branches, if not given, a reset input
+# is added and connected to rst.
+# The content of the ROM is passed through +content+ argument.
+#
+# NOTE:
+#
+# * such memories uses the following ports:
+#   - trig_r: read access trigger  (output)
+#   - trig_w: write access trigger (output)
+#   - dbus_r: read data bus        (input)
+#   - dbus_w: write data bus       (output)
+#
+# * The following branches are possible (only one read and one write can
+#   be used per channel)
+#   - raddr:   read by address, this channel adds the following port:
+#     abus_r:  read address bus (output)
+#   - waddr:   read by address, this channel adds the following port:
+#     abus_w:  write address bus (output)
+#   - rinc:    read by automatically incremented address.
+#   - winc:    write by automatically incremented address.
+#   - rdec:    read by automatically decremented address.
+#   - wdec:    write by automatically decremented address.
+#   - rque:    read in queue mode: automatically incremented address ensuring
+#              the read address is always different from the write address.
+#   - wque:    write in queue mode: automatically incremented address ensuring
+#              the write address is always differnet from the read address.
+#
+HDLRuby::High::Std.channel(:mem_rom) do |typ,size,clk,rst,content,
+    br_rsts = {}|
+    # Ensure typ is a type.
+    typ = typ.to_type
+    # Ensure size in an integer.
+    size = size.to_i
+    # Compute the address bus width from the size.
+    awidth = (size-1).width
+    # Process the table of reset mapping for the branches.
+    # Ensures br_srts is a hash.
+    br_rsts = br_rsts.to_hash
+
+    # Declare the control signals.
+    # Access trigger.
+    inner :trig_r
+    # Data bus
+    typ.inner :dbus_r
+    # Address bus (or simply register)
+    [awidth].inner :abus_r
+
+    # Declare the ROM with its inner content.
+    # typ[-size].constant mem: content.map { |val| val.to_expr }
+    typ[-size].constant mem: content
+
+    # Processes handling the memory access.
+    par(clk.negedge) do
+        dbus_r <= mem[abus_r]
+    end
+
+    # The address branches.
+    # Read with address
+    brancher(:raddr) do
+        reader_output :trig_r, :abus_r
+        reader_input :dbus_r
+        if br_rsts[:raddr] then
+            rst_name = br_rsts[:raddr].to_sym
+        else
+            rst_name = rst.name
+            reader_input rst_name
+        end
+
+        # Defines the read procedure at address +addr+
+        # using +target+ as target of access result.
+        reader do |blk,addr,target|
+            # By default the read trigger is 0.
+            top_block.unshift { trig_r <= 0 }
+            # The read procedure.
+            rst  = send(rst_name)
+            par do
+                hif(rst == 0) do
+                    # No reset, so can perform the read.
+                    hif(trig_r == 1) do
+                        # The trigger was previously set, read ok.
+                        target <= dbus_r
+                        trig_r <= 0
+                        blk.call if blk
+                    end
+                    helse do
+                        # Prepare the read.
+                        abus_r <= addr
+                        trig_r <= 1
+                    end
+                end
+            end
+        end
+    end
+
+    # The increment branches.
+    # Read with increment
+    brancher(:rinc) do
+        reader_output :trig_r, :abus_r
+        reader_input :dbus_r
+        if br_rsts[:rinc] then
+            rst_name = br_rsts[:rinc].to_sym
+        else
+            rst_name = rst.name
+            reader_input rst_name
+        end
+
+        # Defines the read procedure at address +addr+
+        # using +target+ as target of access result.
+        reader do |blk,target|
+            # On reset the read trigger is 0.
+            rst  = send(rst_name)
+            top_block.unshift do
+                # Initialize the address so that the next access is at address 0.
+                hif(rst==1) { abus_r <= -1 }
+                # Reset so switch of the access trigger.
+                trig_r <= 0
+            end
+            # The read procedure.
+            par do
+                hif(rst == 0) do
+                    # No reset, so can perform the read.
+                    hif(trig_r == 1) do
+                        # The trigger was previously set, read ok.
+                        target <= dbus_r
+                        blk.call if blk
+                    end
+                    # Prepare the read.
+                    abus_r <= abus_r + 1
+                    trig_r <= 1
+                end
+            end
+        end
+    end
+
+    # The decrement branches.
+    # Read with increment
+    brancher(:rdec) do
+        reader_output :trig_r, :abus_r
+        reader_input :dbus_r
+        if br_rsts[:rdec] then
+            rst_name = br_rsts[:rdec].to_sym
+        else
+            rst_name = rst.name
+            reader_input rst_name
+        end
+
+        # Defines the read procedure at address +addr+
+        # using +target+ as target of access result.
+        reader do |blk,target|
+            # On reset the read trigger is 0.
+            rst  = send(rst_name)
+            top_block.unshift do
+                # Initialize the address so that the next access is at address 0.
+                hif(rst==1) { abus_r <= 0 }
+                # Reset so switch of the access trigger.
+                trig_r <= 0
+            end
+            # The read procedure.
+            par do
+                hif(rst == 0) do
+                    # No reset, so can perform the read.
+                    hif(trig_r == 1) do
+                        # The trigger was previously set, read ok.
+                        target <= dbus_r
+                        blk.call if blk
+                    end
+                    # Prepare the read.
+                    abus_r <= abus_r - 1
+                    trig_r <= 1
+                end
+            end
+        end
+    end
+
+end
+
+
 
 
 
@@ -213,28 +394,32 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
     awidth = (size-1).width
     # Process the table of reset mapping for the branches.
     # puts "first br_rsts=#{br_rsts}"
-    if br_rsts.is_a?(Array) then
-        # It is a list, convert it to a hash with the following order:
-        # raddr, waddr, rinc, winc, rdec, wdec, rque, wque
-        # If there is only two entries they will be duplicated and mapped
-        # as follows:
-        # [raddr,waddr], [rinc,winc], [rdec,wdec], [rque,wque]
-        # If there is only one entry it will be duplicated and mapped as
-        # follows:
-        # raddr, rinc, rdec, rque
-        if br_rsts.size == 2 then
-            br_rsts = br_rsts * 4
-        elsif br_rsts.size == 1 then
-            br_rsts = br_rsts * 8
-        end
-        br_rsts = { raddr: br_rsts[0], waddr: br_rsts[1],
-                    rinc:  br_rsts[2], winc:  br_rsts[3],
-                    rdec:  br_rsts[4], wdec:  br_rsts[5],
-                    rque:  br_rsts[6], wque:  br_rsts[6] }
-    end
-    unless br_rsts.respond_to?(:[])
-        raise "Invalid reset mapping description: #{br_rsts}"
-    end
+    # if br_rsts.is_a?(Array) then
+    #     # It is a list, convert it to a hash with the following order:
+    #     # raddr, waddr, rinc, winc, rdec, wdec, rque, wque
+    #     # When not specified the reset is +rst+ by default.
+    #     # If there is only two entries they will be duplicated and mapped
+    #     # as follows:
+    #     # [raddr,waddr], [rinc,winc], [rdec,wdec], [rque,wque]
+    #     # If there is only one entry it will be duplicated and mapped as
+    #     # follows:
+    #     # raddr, rinc, rdec, rque
+    #     if br_rsts.size == 2 then
+    #         br_rsts = br_rsts * 4
+    #     elsif br_rsts.size == 1 then
+    #         br_rsts = br_rsts * 8
+    #     end
+    #     br_rsts = { raddr: br_rsts[0], waddr: br_rsts[1],
+    #                 rinc:  br_rsts[2], winc:  br_rsts[3],
+    #                 rdec:  br_rsts[4], wdec:  br_rsts[5],
+    #                 rque:  br_rsts[6], wque:  br_rsts[6] }
+    # end
+    # unless br_rsts.respond_to?(:[])
+    #     raise "Invalid reset mapping description: #{br_rsts}"
+    # end
+    #
+    # Ensures br_srts is a hash.
+    br_rsts = br_rsts.to_hash
 
     # Declare the control signals.
     # Access triggers.
@@ -342,7 +527,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
         # Defines the read procedure at address +addr+
         # using +target+ as target of access result.
         reader do |blk,target|
-            # By default the read trigger is 0.
+            # On reset the read trigger is 0.
             rst  = send(rst_name)
             top_block.unshift do
                 # Initialize the address so that the next access is at address 0.
@@ -382,7 +567,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
         # Defines the read procedure at address +addr+
         # using +target+ as target of access result.
         writer do |blk,target|
-            # By default the read trigger is 0.
+            # On reset the read trigger is 0.
             rst  = send(rst_name)
             top_block.unshift do
                 # Initialize the address so that the next access is at address 0.
@@ -420,7 +605,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
         # Defines the read procedure at address +addr+
         # using +target+ as target of access result.
         reader do |blk,target|
-            # By default the read trigger is 0.
+            # On reset the read trigger is 0.
             rst  = send(rst_name)
             top_block.unshift do
                 # Initialize the address so that the next access is at address 0.
@@ -460,7 +645,7 @@ HDLRuby::High::Std.channel(:mem_dual) do |typ,size,clk,rst,br_rsts = {}|
         # Defines the read procedure at address +addr+
         # using +target+ as target of access result.
         writer do |blk,target|
-            # By default the read trigger is 0.
+            # On reset the read trigger is 0.
             rst  = send(rst_name)
             top_block.unshift do
                 # Initialize the address so that the next access is at address 0.
@@ -675,7 +860,7 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
         # using +target+ as target of access result.
         reader do |blk,target|
             regs = size.times.map {|i| send(:"reg_#{i}") }
-            # By default the read trigger is 0.
+            # On reset the read trigger is 0.
             rst  = send(rst_name)
             top_block.unshift do
                 # Initialize the address so that the next access is at address 0.
@@ -704,17 +889,17 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             rst_name = br_rsts[:winc].to_sym
         else
             rst_name = rst.name
-            reader_input rst_name
+            writer_input rst_name
         end
         # Declares the address counter.
         [size.width-1].inner :abus_w
-        reader_inout :abus_w
+        writer_inout :abus_w
 
         # Defines the write procedure at address +addr+
         # using +target+ as target of access result.
         writer do |blk,target|
             regs = size.times.map {|i| send(:"reg_#{i}") }
-            # By default the read trigger is 0.
+            # On reset the read trigger is 0.
             rst  = send(rst_name)
             top_block.unshift do
                 # Initialize the address so that the next access is at address 0.
@@ -755,7 +940,7 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
         # using +target+ as target of access result.
         reader do |blk,target|
             regs = size.times.map {|i| send(:"reg_#{i}") }
-            # By default the read trigger is 0.
+            # On reset the read trigger is 0.
             rst  = send(rst_name)
             top_block.unshift do
                 # Initialize the address so that the next access is at address 0.
@@ -794,7 +979,7 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
         # using +target+ as target of access result.
         writer do |blk,target|
             regs = size.times.map {|i| send(:"reg_#{i}") }
-            # By default the read trigger is 0.
+            # On reset the read trigger is 0.
             rst  = send(rst_name)
             top_block.unshift do
                 # Initialize the address so that the next access is at address 0.
@@ -817,3 +1002,788 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
     end
 
 end
+
+
+
+
+# Multi-bank memory combining several dual-edge memories of +nbanks+ banks
+# of +size+ elements of +typ+ typ, syncrhonized on +clk+ (positive and
+# negative edges) and reset on +rst+.
+# at each rising edge of +clk+ a read and a write is guaranteed to be
+# completed provided they are triggered.
+# +br_rsts+ are reset names on the branches, if not given, a reset input
+# is added and connected to rst.
+#
+# NOTE:
+#
+# * such memories uses the following ports:
+#   - trig_r: read access trigger  (output)
+#   - trig_w: write access trigger (output)
+#   - dbus_r: read data bus        (input)
+#   - dbus_w: write data bus       (output)
+#
+# * The following branches are possible (only one read and one write can
+#   be used per channel)
+#   - raddr:   read by address, this channel adds the following port:
+#     abus_r:  read address bus (output)
+#   - waddr:   read by address, this channel adds the following port:
+#     abus_w:  write address bus (output)
+#   - rinc:    read by automatically incremented address.
+#   - winc:    write by automatically incremented address.
+#   - rdec:    read by automatically decremented address.
+#   - wdec:    write by automatically decremented address.
+#   - rque:    read in queue mode: automatically incremented address ensuring
+#              the read address is always different from the write address.
+#   - wque:    write in queue mode: automatically incremented address ensuring
+#              the write address is always differnet from the read address.
+HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
+    # Ensure typ is a type.
+    typ = typ.to_type
+    # Ensure size in an integer.
+    size = size.to_i
+    # Compute the address bus width from the size.
+    awidth = (size*nbanks-1).width
+    awidth_b = (size-1).width # Bank width
+    # Ensures br_srts is a hash.
+    br_rsts = br_rsts.to_hash
+
+    # The global buses and control signals.
+    [awidth].inner :abus_r, :abus_w
+    typ.inner :dbus_r, :dbus_w
+    inner :trig_r, :trig_w
+
+    # For each bank.
+    nbanks.times do |id|
+        # Declare the control signals.
+        # Access triggers.
+        inner :"trig_r_#{id}", :"trig_w_#{id}"
+        # Data buses
+        typ.inner :"dbus_r_#{id}", :"dbus_w_#{id}"
+        # Address buses (or simply registers)
+        [awidth_b].inner :"abus_r_#{id}", :"abus_w_#{id}"
+
+        # Declare the memory content.
+        typ[-size].inner :"mem_#{id}"
+
+        # Processes handling the memory access.
+        par(clk.negedge) do
+            send(:"dbus_r_#{id}") <= send(:"mem_#{id}")[send(:"abus_r_#{id}")]
+            hif(trig_w & ((abus_w % nbanks) == id)) do
+                send(:"mem_#{id}")[send(:"abus_w_#{id}")] <= dbus_w
+            end
+            helsif(send(:"trig_w_#{id}")) do
+                send(:"mem_#{id}")[send(:"abus_w_#{id}")] <= send(:"dbus_w_#{id}")
+            end
+        end
+    end
+    # Interconnect the buses and triggers
+    nbanks.times do |id|
+        send(:"abus_r_#{id}") <= abus_r / nbanks
+        send(:"abus_w_#{id}") <= abus_w / nbanks
+    end
+    par do
+        # By default triggers are off.
+        nbanks.times do |id|
+            send(:"trig_w_#{id}") <= 0
+            send(:"trig_r_#{id}") <= 0
+        end
+        # Set the read address bus and trigger if required.
+        hcase(abus_r % nbanks)
+        nbanks.times do |id|
+            hwhen(id) do
+                dbus_r <= send(:"dbus_r_#{id}")
+                send(:"trig_r_#{id}") <= trig_r
+            end
+        end
+    end
+
+
+    # The address branches.
+    # Read with address
+    brancher(:raddr) do
+        reader_output :trig_r, :abus_r
+        reader_input :dbus_r
+        if br_rsts[:raddr] then
+            rst_name = br_rsts[:raddr].to_sym
+        else
+            rst_name = rst.name
+            reader_input rst_name
+        end
+
+        # Defines the read procedure at address +addr+
+        # using +target+ as target of access result.
+        reader do |blk,addr,target|
+            # By default the read trigger is 0.
+            top_block.unshift { trig_r <= 0 }
+            # The read procedure.
+            rst  = send(rst_name)
+            par do
+                hif(rst == 0) do
+                    # No reset, so can perform the read.
+                    hif(trig_r == 1) do
+                        # The trigger was previously set, read ok.
+                        target <= dbus_r
+                        trig_r <= 0
+                        blk.call if blk
+                    end
+                    helse do
+                        # Prepare the read.
+                        abus_r <= addr
+                        trig_r <= 1
+                    end
+                end
+            end
+        end
+    end
+
+    # Write with address
+    brancher(:waddr) do
+        writer_output :trig_w, :abus_w, :dbus_w
+        if br_rsts[:waddr] then
+            rst_name = br_rsts[:waddr].to_sym
+        else
+            rst_name = rst.name
+            writer_input rst_name
+        end
+        # puts "br_rsts=#{br_rsts}"
+        # puts "rst_name=#{rst_name}"
+
+        # Defines the read procedure at address +addr+
+        # using +target+ as target of access result.
+        writer do |blk,addr,target|
+            # By default the read trigger is 0.
+            top_block.unshift { trig_w <= 0 }
+            # The write procedure.
+            rst  = send(rst_name)
+            par do
+                hif(rst == 0) do
+                    # No reset, so can perform the write.
+                    hif(trig_w == 1) do
+                        # The trigger was previously set, write ok.
+                        blk.call if blk
+                    end
+                    # Prepare the write.
+                    abus_w <= addr
+                    trig_w <= 1
+                    dbus_w <= target
+                end
+            end
+        end
+    end
+
+    # The increment branches.
+    # Read with increment
+    brancher(:rinc) do
+        reader_output :trig_r, :abus_r
+        reader_input :dbus_r
+        if br_rsts[:rinc] then
+            rst_name = br_rsts[:rinc].to_sym
+        else
+            rst_name = rst.name
+            reader_input rst_name
+        end
+
+        # Defines the read procedure at address +addr+
+        # using +target+ as target of access result.
+        reader do |blk,target|
+            # On reset the read trigger is 0.
+            rst  = send(rst_name)
+            top_block.unshift do
+                # Initialize the address so that the next access is at address 0.
+                hif(rst==1) { abus_r <= -1 }
+                # Reset so switch of the access trigger.
+                trig_r <= 0
+            end
+            # The read procedure.
+            par do
+                hif(rst == 0) do
+                    # No reset, so can perform the read.
+                    hif(trig_r == 1) do
+                        # The trigger was previously set, read ok.
+                        target <= dbus_r
+                        blk.call if blk
+                    end
+                    # Prepare the read.
+                    abus_r <= abus_r + 1
+                    trig_r <= 1
+                end
+            end
+        end
+    end
+
+    # Write with address
+    brancher(:winc) do
+        writer_output :trig_w, :abus_w, :dbus_w
+        if br_rsts[:winc] then
+            rst_name = br_rsts[:winc].to_sym
+        else
+            rst_name = rst.name
+            writer_input rst_name
+        end
+        # puts "br_rsts=#{br_rsts}"
+        # puts "rst_name=#{rst_name}"
+
+        # Defines the read procedure at address +addr+
+        # using +target+ as target of access result.
+        writer do |blk,target|
+            # On reset the read trigger is 0.
+            rst  = send(rst_name)
+            top_block.unshift do
+                # Initialize the address so that the next access is at address 0.
+                hif(rst == 1) { abus_w <= -1 }
+                # Reset so switch of the access trigger.
+                trig_w <= 0
+            end
+            # The write procedure.
+            par do
+                hif(rst == 0) do
+                    # No reset, so can perform the write.
+                    blk.call if blk
+                    # Prepare the write.
+                    abus_w <= abus_w + 1
+                    trig_w <= 1
+                    dbus_w <= target
+                end
+            end
+        end
+    end
+
+    # The decrement branches.
+    # Read with increment
+    brancher(:rdec) do
+        reader_output :trig_r, :abus_r
+        reader_input :dbus_r
+        if br_rsts[:rdec] then
+            rst_name = br_rsts[:rdec].to_sym
+        else
+            rst_name = rst.name
+            reader_input rst_name
+        end
+
+        # Defines the read procedure at address +addr+
+        # using +target+ as target of access result.
+        reader do |blk,target|
+            # On reset the read trigger is 0.
+            rst  = send(rst_name)
+            top_block.unshift do
+                # Initialize the address so that the next access is at address 0.
+                hif(rst==1) { abus_r <= 0 }
+                # Reset so switch of the access trigger.
+                trig_r <= 0
+            end
+            # The read procedure.
+            par do
+                hif(rst == 0) do
+                    # No reset, so can perform the read.
+                    hif(trig_r == 1) do
+                        # The trigger was previously set, read ok.
+                        target <= dbus_r
+                        blk.call if blk
+                    end
+                    # Prepare the read.
+                    abus_r <= abus_r - 1
+                    trig_r <= 1
+                end
+            end
+        end
+    end
+
+    # Write with address
+    brancher(:wdec) do
+        writer_output :trig_w, :abus_w, :dbus_w
+        if br_rsts[:wdec] then
+            rst_name = br_rsts[:wdec].to_sym
+        else
+            rst_name = rst.name
+            writer_input rst_name
+        end
+        # puts "br_rsts=#{br_rsts}"
+        # puts "rst_name=#{rst_name}"
+
+        # Defines the read procedure at address +addr+
+        # using +target+ as target of access result.
+        writer do |blk,target|
+            # On reset the read trigger is 0.
+            rst  = send(rst_name)
+            top_block.unshift do
+                # Initialize the address so that the next access is at address 0.
+                hif(rst == 1) { abus_w <= 0 }
+                # Reset so switch of the access trigger.
+                trig_w <= 0
+            end
+            # The write procedure.
+            par do
+                hif(rst == 0) do
+                    # No reset, so can perform the write.
+                    blk.call if blk
+                    # Prepare the write.
+                    abus_w <= abus_w - 1
+                    trig_w <= 1
+                    dbus_w <= target
+                end
+            end
+        end
+    end
+
+
+    # Declare the branchers for accessing directly the banks.
+    nbanks.times do |id|
+        # Read with address.
+        brancher(:"raddr_#{id}") do
+            reader_output :"trig_r_#{id}", :"abus_r_#{id}"
+            reader_input :"dbus_r_#{id}"
+            if br_rsts[:"raddr_#{id}"] then
+                rst_name = br_rsts[:"raddr_#{id}"].to_sym
+            else
+                rst_name = rst.name
+                reader_input rst_name
+            end
+
+            # Defines the read procedure at address +addr+
+            # using +target+ as target of access result.
+            reader do |blk,addr,target|
+                # By default the read trigger is 0.
+                top_block.unshift { send(:"trig_r_#{id}") <= 0 }
+                # The read procedure.
+                rst  = send(rst_name)
+                par do
+                    hif(rst == 0) do
+                        # No reset, so can perform the read.
+                        hif(send(:"trig_r_#{id}") == 1) do
+                            # The trigger was previously set, read ok.
+                            target <= send(:"dbus_r_#{id}")
+                            send(:"trig_r_#{id}") <= 0
+                            blk.call if blk
+                        end
+                        helse do
+                            # Prepare the read.
+                            send(:"abus_r_#{id}") <= addr
+                            send(:"trig_r_#{id}") <= 1
+                        end
+                    end
+                end
+            end
+        end
+
+        # Write with address
+        brancher(:"waddr_#{id}") do
+            writer_output :"trig_w_#{id}", :"abus_w_#{id}", :"dbus_w_#{id}"
+            if br_rsts[:"waddr_#{id}"] then
+                rst_name = br_rsts[:"waddr_#{id}"].to_sym
+            else
+                rst_name = rst.name
+                writer_input rst_name
+            end
+
+            # Defines the read procedure at address +addr+
+            # using +target+ as target of access result.
+            writer do |blk,addr,target|
+                # By default the read trigger is 0.
+                top_block.unshift { send(:"trig_w_#{id}") <= 0 }
+                # The write procedure.
+                rst  = send(rst_name)
+                par do
+                    hif(rst == 0) do
+                        # No reset, so can perform the write.
+                        hif(send(:"trig_w_#{id}") == 1) do
+                            # The trigger was previously set, write ok.
+                            blk.call if blk
+                        end
+                        # Prepare the write.
+                        send(:"abus_w_#{id}") <= addr
+                        send(:"trig_w_#{id}") <= 1
+                        send(:"dbus_w_#{id}") <= target
+                    end
+                end
+            end
+        end
+
+        # The increment branches.
+        # Read with increment
+        brancher(:"rinc_#{id}") do
+            reader_output :"trig_r_#{id}", :"abus_r_#{id}"
+            reader_input :"dbus_r_#{id}"
+            if br_rsts[:"rinc_#{id}"] then
+                rst_name = br_rsts[:"rinc_#{id}"].to_sym
+            else
+                rst_name = rst.name
+                reader_input rst_name
+            end
+
+            # Defines the read procedure at address +addr+
+            # using +target+ as target of access result.
+            reader do |blk,target|
+                # On reset the read trigger is 0.
+                rst  = send(rst_name)
+                top_block.unshift do
+                    # Initialize the address so that the next access is at address 0.
+                    hif(rst==1) { send(:"abus_r_#{id}") <= -1 }
+                    # Reset so switch of the access trigger.
+                    send(:"trig_r_#{id}") <= 0
+                end
+                # The read procedure.
+                par do
+                    hif(rst == 0) do
+                        # No reset, so can perform the read.
+                        hif(send(:"trig_r_#{id}") == 1) do
+                            # The trigger was previously set, read ok.
+                            target <= send(:"dbus_r_#{id}")
+                            blk.call if blk
+                        end
+                        # Prepare the read.
+                        send(:"abus_r_#{id}") <= send(:"abus_r_#{id}") + 1
+                        send(:"trig_r_#{id}") <= 1
+                    end
+                end
+            end
+        end
+
+        # Write with address
+        brancher(:"winc_#{id}") do
+            writer_output :"trig_w_#{id}", :"abus_w_#{id}", :"dbus_w_#{id}"
+            if br_rsts[:"winc_#{id}"] then
+                rst_name = br_rsts[:"winc_#{id}"].to_sym
+            else
+                rst_name = rst.name
+                writer_input rst_name
+            end
+
+            # Defines the read procedure at address +addr+
+            # using +target+ as target of access result.
+            writer do |blk,target|
+                # On reset the read trigger is 0.
+                rst  = send(rst_name)
+                top_block.unshift do
+                    # Initialize the address so that the next access is at address 0.
+                    hif(rst == 1) { send(:"abus_w_#{id}") <= -1 }
+                    # Reset so switch of the access trigger.
+                    send(:"trig_w_#{id}") <= 0
+                end
+                # The write procedure.
+                par do
+                    hif(rst == 0) do
+                        # No reset, so can perform the write.
+                        blk.call if blk
+                        # Prepare the write.
+                        send(:"abus_w_#{id}") <= send(:"abus_w_#{id}") + 1
+                        send(:"trig_w_#{id}") <= 1
+                        send(:"dbus_w_#{id}") <= target
+                    end
+                end
+            end
+        end
+
+        # The decrement branches.
+        # Read with increment
+        brancher(:"rdec_#{id}") do
+            reader_output :"trig_r_#{id}", :"abus_r_#{id}"
+            reader_input :"dbus_r_#{id}"
+            if br_rsts[:"rdec_#{id}"] then
+                rst_name = br_rsts[:"rdec_#{id}"].to_sym
+            else
+                rst_name = rst.name
+                reader_input rst_name
+            end
+
+            # Defines the read procedure at address +addr+
+            # using +target+ as target of access result.
+            reader do |blk,target|
+                # On reset the read trigger is 0.
+                rst  = send(rst_name)
+                top_block.unshift do
+                    # Initialize the address so that the next access is at address 0.
+                    hif(rst==1) { send(:"abus_r_#{id}") <= 0 }
+                    # Reset so switch of the access trigger.
+                    send(:"trig_r_#{id}") <= 0
+                end
+                # The read procedure.
+                par do
+                    hif(rst == 0) do
+                        # No reset, so can perform the read.
+                        hif(send(:"trig_r_#{id}") == 1) do
+                            # The trigger was previously set, read ok.
+                            target <= send(:"dbus_r_#{id}")
+                            blk.call if blk
+                        end
+                        # Prepare the read.
+                        send(:"abus_r_#{id}") <= send(:"abus_r_#{id}") - 1
+                        send(:"trig_r_#{id}") <= 1
+                    end
+                end
+            end
+        end
+
+        # Write with address
+        brancher(:"wdec_#{id}") do
+            writer_output :"trig_w_#{id}", :"abus_w_#{id}", :"dbus_w_#{id}"
+            if br_rsts[:"wdec_#{id}"] then
+                rst_name = br_rsts[:"wdec_#{id}"].to_sym
+            else
+                rst_name = rst.name
+                writer_input rst_name
+            end
+
+            # Defines the read procedure at address +addr+
+            # using +target+ as target of access result.
+            writer do |blk,target|
+                # On reset the read trigger is 0.
+                rst  = send(rst_name)
+                top_block.unshift do
+                    # Initialize the address so that the next access is at address 0.
+                    hif(rst == 1) { send(:"abus_w_#{id}") <= 0 }
+                    # Reset so switch of the access trigger.
+                    trig_w <= 0
+                end
+                # The write procedure.
+                par do
+                    hif(rst == 0) do
+                        # No reset, so can perform the write.
+                        blk.call if blk
+                        # Prepare the write.
+                        send(:"abus_w_#{id}") <= send(:"abus_w_#{id}") - 1
+                        send(:"trig_w_#{id}") <= 1
+                        send(:"dbus_w_#{id}") <= target
+                    end
+                end
+            end
+        end
+    end
+
+end
+
+# HDLRuby::High::Std.channel(:mem_bank) do |typ,nbanks,size,clk,rst,br_rsts = {}|
+#     # Ensure typ is a type.
+#     typ = typ.to_type
+#     # Ensure nbank is an integer.
+#     nbanks = nbanks.to_i
+#     # Ensure size in an integer.
+#     size = size.to_i
+#     # Compute the address bus width from the size.
+#     awidth = (size-1).width
+#     # # Process the table of reset mapping for the branches.
+#     # # puts "first br_rsts=#{br_rsts}"
+#     # if br_rsts.is_a?(Array) then
+#     #     # It is a list, convert it to a hash with the following order:
+#     #     # raddr, waddr, rinc, winc, rdec, wdec, rque, wque
+#     #     # If there is only two entries they will be duplicated and mapped
+#     #     # as follows:
+#     #     # [raddr,waddr], [rinc,winc], [rdec,wdec], [rque,wque]
+#     #     # If there is only one entry it will be duplicated and mapped as
+#     #     # follows:
+#     #     # raddr, rinc, rdec, rque
+#     #     if br_rsts.size == 2 then
+#     #         br_rsts = br_rsts * 4
+#     #     elsif br_rsts.size == 1 then
+#     #         br_rsts = br_rsts * 8
+#     #     end
+#     #     br_rsts = { raddr: br_rsts[0], waddr: br_rsts[1],
+#     #                 rinc:  br_rsts[2], winc:  br_rsts[3],
+#     #                 rdec:  br_rsts[4], wdec:  br_rsts[5],
+#     #                 rque:  br_rsts[6], wque:  br_rsts[6] }
+#     # end
+#     # unless br_rsts.respond_to?(:[])
+#     #     raise "Invalid reset mapping description: #{br_rsts}"
+#     # end
+#     # Ensures br_rsts is a hash.
+#     br_rsts = br_rsts.to_hash
+# 
+#     # Declares the banks.
+#     banks = nbanks.times.map do |id|
+#         # Extract the resets corresponding to the bank.
+#         cur_br_rsts = {}
+#         br_rsts.each do |k,v| 
+#             num = k.to_s[/\d+$/]
+#             if num && num.to_i == id then
+#                 cur_br_rsts[k.to_s.chomp[num]] = v
+#             end
+#         end
+#         # Declare the bank.
+#         mem_dual(typ,size,clk,rst, cur_br_rsts).(HDLRuby.uniq_name)
+#     end
+# 
+#     # Declare the branchers for accessing directly the banks.
+#     banks.each_with_index do |bank,id|
+#         brancher(id,bank)
+#     end
+# 
+#     # Generate the gobal access to the memory.
+#  
+#     # The address branches.
+#     # Read with address
+#     brancher(:raddr) do
+#         # Create the read branch for each bank.
+#         bank_brs = banks.map do |bank|
+#             bank.branch(:raddr).inner HDLRuby.uniq_name
+#         end
+#         # Defines the read procedure at address +addr+
+#         # using +target+ as target of access result.
+#         reader do |blk,addr,target|
+#             # Select the bank depending on the address.
+#             hcase(addr / nbanks)
+#             nbanks.times do |i|
+#                 hwhen(i) do
+#                     bank_brs[i].read(addr % nbanks,target,&blk)
+#                 end
+#             end
+#         end
+#     end
+#     # Write with address
+#     brancher(:waddr) do
+#         # Create the write branch for each bank.
+#         bank_brs = banks.map do |bank|
+#             bank.branch(:waddr).inner HDLRuby.uniq_name
+#         end
+#         # Defines the read procedure at address +addr+
+#         # using +target+ as target of access result.
+#         writer do |blk,addr,target|
+#             # Select the bank depending on the address.
+#             hcase(addr / nbanks)
+#             nbanks.times do |i|
+#                 hwhen(i) do
+#                     bank_brs[i].write(addr % nbanks,target,&blk)
+#                 end
+#             end
+#         end
+#     end
+# 
+# 
+#     # Address buses (or simply registers) for increment/decrement accesses
+#     [awidth].inner :abus_r, :abus_w
+# 
+#     # The increment branches.
+#     # Read with increment
+#     brancher(:rinc) do
+#         reader_output :abus_r
+#         if br_rsts[:rinc] then
+#             rst_name = br_rsts[:rinc].to_sym
+#         else
+#             rst_name = rst.name
+#             reader_input rst_name
+#         end
+#         # Create the write branch for each bank.
+#         bank_brs = banks.map do |bank|
+#             bank.branch(:raddr).inner HDLRuby.uniq_name
+#         end
+# 
+#         # Defines the read procedure at address +addr+
+#         # using +target+ as target of access result.
+#         reader do |blk,target|
+#             # On reset the read trigger is 0.
+#             rst  = send(rst_name)
+#             top_block.unshift do
+#                 # Initialize the address so that the next access is at address 0.
+#                 hif(rst==1) { abus_r <= 0 }
+#             end
+#             # Select the bank depending on the address.
+#             hcase(abus_r / nbanks)
+#             nbanks.times do |i|
+#                 hwhen(i) do
+#                     bank_brs[i].read(abus_r % nbanks,target) do
+#                         abus_r <= abus_r + 1 
+#                         blk.call
+#                     end
+#                 end
+#             end
+#         end
+#     end
+#     # Write with increment
+#     brancher(:winc) do
+#         reader_output :abus_w
+#         if br_rsts[:winc] then
+#             rst_name = br_rsts[:winc].to_sym
+#         else
+#             rst_name = rst.name
+#             writer_input rst_name
+#         end
+#         # Create the write branch for each bank.
+#         bank_brs = banks.map do |bank|
+#             bank.branch(:waddr).inner HDLRuby.uniq_name
+#         end
+# 
+#         # Defines the read procedure at address +addr+
+#         # using +target+ as target of access result.
+#         writer do |blk,target|
+#             # On reset the read trigger is 0.
+#             rst  = send(rst_name)
+#             top_block.unshift do
+#                 # Initialize the address so that the next access is at address 0.
+#                 hif(rst==1) { abus_w <= 0 }
+#             end
+#             # Select the bank depending on the address.
+#             hcase(abus_w / nbanks)
+#             nbanks.times do |i|
+#                 hwhen(i) do
+#                     bank_brs[i].read(abus_w % nbanks,target) do
+#                         abus_w <= abus_w + 1 
+#                         blk.call
+#                     end
+#                 end
+#             end
+#         end
+#     end
+# 
+#     # The decrement branches.
+#     # Read with decrement
+#     brancher(:rdec) do
+#         reader_output :abus_r
+#         if br_rsts[:rdec] then
+#             rst_name = br_rsts[:rdec].to_sym
+#         else
+#             rst_name = rst.name
+#             reader_input rst_name
+#         end
+# 
+#         # Defines the read procedure at address +addr+
+#         # using +target+ as target of access result.
+#         reader do |blk,target|
+#             # On reset the read trigger is 0.
+#             rst  = send(rst_name)
+#             top_block.unshift do
+#                 # Initialize the address so that the next access is at address 0.
+#                 hif(rst==1) { abus_r <= 0 }
+#             end
+#             # Select the bank depending on the address.
+#             hcase(abus_r / nbanks)
+#             nbanks.times do |i|
+#                 hwhen(i) do
+#                     banks[i].read(abus_r % nbanks,target) do
+#                         abus_r <= abus_r + 1 
+#                         blk.call
+#                     end
+#                 end
+#             end
+#         end
+#     end
+#     # Write with decrement
+#     brancher(:wdec) do
+#         reader_output :abus_w
+#         if br_rsts[:wdec] then
+#             rst_name = br_rsts[:wdec].to_sym
+#         else
+#             rst_name = rst.name
+#             writer_input rst_name
+#         end
+# 
+#         # Defines the read procedure at address +addr+
+#         # using +target+ as target of access result.
+#         writer do |blk,target|
+#             # On reset the read trigger is 0.
+#             rst  = send(rst_name)
+#             top_block.unshift do
+#                 # Initialize the address so that the next access is at address 0.
+#                 hif(rst==1) { abus_w <= 0 }
+#             end
+#             # Select the bank depending on the address.
+#             hcase(abus_w / nbanks)
+#             nbanks.times do |i|
+#                 hwhen(i) do
+#                     banks[i].read(abus_w % nbanks,target) do
+#                         abus_w <= abus_w + 1 
+#                         blk.call
+#                     end
+#                 end
+#             end
+#         end
+#     end
+# 
+# end