HDLRuby 2.2.17 → 2.3.4

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: f9512393bdc65c3c2ae471d471b30d911cb693b8c1bc18a20186320286f27602
-  data.tar.gz: 8a5bce50d367d52c181779ce834b2cfb3ecb14fe3c6ce96388eade344692e616
+  metadata.gz: b9bca5842e518422f5e7b7edb864a8eae5955df19238cd9582a776d4ef6c7a1e
+  data.tar.gz: 6c094ebf5d69c8dbf57ddd800eca16aca88b4bc324db11eecac3f15569b633e3
 SHA512:
-  metadata.gz: 8cc2e806c2eb5d5ea9e4bc2c5cc449f2a0f6ca7270b73232efcc3fb9ae7bacdd074e2995f9233547fc47dae4ccfd98ab9b41d3903cee87374247cc4f68e353e4
-  data.tar.gz: 698b4bd637fe294d0bf27fa163ef3c52528260cf443482d9e9a4922a56032db8400d8f95af67a3b62d67e949840c437869512514cb0db575c5b8c7b1b9b7fad9
+  metadata.gz: f01e2f703bcade0db355c42e78267205ca3662c8b30589c5676eab6acaf334fac2a86205b600122e50f11eef3e6a17182dacb59b9a7821c3fa9d7aed90ebd6b7
+  data.tar.gz: 5c3b80eddb70a3f25f2941bc26c8e95a8f3a30f5020cb17d6a4a199678aacaab4ce0c5c4ffcd347c23b53bd86fb15d58392818673e57ca3d108aec0c5b062ed0

data/README.md

@@ -2815,27 +2815,17 @@ This library provides a unified interface to complex communication protocols thr
 ### Using a channel
 
 A channel is used similarly to a pipe: it has an input where data can be written and an output where data can be read. The ordering of the data and the synchronization depend on the internals of the channel, e.g., a channel can be FIFO or LIFO. The interaction with the channel is done using the following methods:
- 
- * `input <name>`: generate ports in the system for reading from the channel amd associate them to `name`
- * `output <name>`: generate ports in the system for writing to the channel and associate them to `name`
- * `inout <name>`: generate ports in the system for reading and writing to the channel and associate them to `name`
- * `inner <name>`: generates inner signals for accessing directly the channel
-
-__Note__: `input`, `output`, `inout` and `inner` for channels work similarly to the ones of data types for declaring signals. In particular, `input`, `output` and `inout` are to be used in systems that do not include the channel and `inner` is to be used in the system that include the channel.
-
-When the channel ports are declared, they can be accessed using the following methods depending on whether they are writing or reading ports:
 
  * `write(<args>) <block>`: write to the channel and execute `block` when `write` completes. `args` is a list of arguments required for performing the write that depend on the channel.
  * `read(<args>) <block>`: read the channel and execute `block` when the read completes. `args` is a list of arguments required for performing the write that depend on the channel.
 
+
 For example, a system sending successive 8-bit values through a channel can be described as follows:
 
 ```ruby
 system :producer8 do |channel|
     # Inputs of the producer: clock and reset.
     input :clk, :rst
-    # Instantiate the channel ports
-    channel.output :chi
     # Inner 8-bit counter for generating values.
     [8].inner :counter
 
@@ -2843,7 +2833,7 @@ system :producer8 do |channel|
     par(clk.posedge) do
         hif(rst) { counter <= 0 }
         helse do
-            chi.write(counter) { counter <= counter + 1 }
+            channel.write(counter) { counter <= counter + 1 }
         end
     end
 end
@@ -2851,6 +2841,22 @@ end
 
 __Note__: In the code above, the channel is passed as generic argument of the system.
 
+The access points to a channel can also be handled individually by declaring ports using the following methods:
+ 
+ * `input <name>`: declares a port for reading from the channel and associate them to `name` if any
+ * `output <name>`: declares a port for writing to the channel and associate them to `name` if any
+ * `inout <name>`: declares a port for reading and writing to the channel and associate them to `name` if any
+
+Such port can then be accessed using the same `read` and `write` method of a channel, the difference being that they can also be configured for new access procedure using the `wrap` method:
+
+ * `wrap(<args>) <code>`: creates a new port whose read or write procedure has the elements of `<args>` and the ones produced by `<code>` assign to the arguments of the read or write procedure.
+
+For example, assuming `mem` is a channel whose read and write access have as argument the target address and data signals, the following code creates a port for always accessing at address 0:
+
+```ruby
+  addr0 = channel.input.wrap(0) 
+```
+
 ### Channel branches
 
 Some channel may include several branches, they are accessed by name using the following method:
@@ -2894,7 +2900,7 @@ Where `name` is the name of the channel and `block` is a procedure block describ
  The first argument of the block must be the following:
    - `blk`: the block to execute when the write completes.
  Other arguments can be freely defined, and will be required by the `write` command.
- * `brancher(name) <block>`: defines branch named +name+ described in `block`. The content of block can be any content valid for a channel, with the additional possiblity to access the internals of the upper channel.
+ * `brancher(name) <block>`: defines branch named +name+ described in `block`. The content of block can be any content valid for a channel, with the additional possibility to access the internals of the upper channel.
 
 For example, a channel implemented by a simple register of generic type `typ`, that can be set to 0 using the `reset` command can be described as follows:
 

data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb

@@ -0,0 +1,96 @@
+require 'std/memory.rb'
+require 'std/linear.rb'
+# require 'std/timing.rb'
+
+include HDLRuby::High::Std
+
+
+system :fir do |typ,iChannel,oChannel,coefs|
+    input :clk, :rst, :req
+    output :ack
+    # Declare the input port.
+    iChannel.input :iPort
+    # Declare the output port.
+    oChannel.output :oPort
+
+    # Declares the data registers.
+    datas = coefs.map.with_index do |coef,id|
+        coef.type.inner :"data_#{id}"
+    end
+
+    inner :req2
+    
+
+    # Generate the mac pipeline.
+    mac_np(typ,clk.posedge,req2,ack, 
+          datas.map{|data| channel_port(data) },
+          coefs.map{|coef| channel_port(coef) }, oPort)
+
+    # Generate the data transfer through the pipeline.
+    par(clk.posedge) do
+        req2 <= 0
+        hif(rst) { datas.each { |d| d <= 0 } }
+        hif(req) do
+            iPort.read(datas[0]) do
+                # datas.each_cons(2) { |d0,d1| d1 <= d0 }
+                datas[1..-1] <= datas[0..-2]
+            end
+            req2 <= 1
+        end
+    end
+end
+
+
+
+
+
+system :work do
+
+    inner :clk,:rst,:req,:ack
+
+    # The input memory.
+    mem_rom([8],8,clk,rst,
+            [_00000001,_00000010,_00000011,_00000100,
+             _00000101,_00000110,_00000111,_00001000]).(:iMem)
+    # The output memory.
+    mem_dual([8],8,clk,rst).(:oMem)
+    # The coefficients.
+    coefs = [_11001100,_00110011,_10101010,_01010101,
+             _11110000,_00001111,_11100011,_00011100]
+
+    # The filter
+    fir([8],iMem.branch(:rinc),oMem.branch(:winc),coefs).(:my_fir).(clk,rst,req,ack)
+
+    # iMem.branch(:rinc).inner :port
+    # [8].inner :a
+    # par(clk.posedge) do
+    #     hif(req) { port.read(a) }
+    # end
+
+    timed do
+        req <= 0
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        req <= 1
+        clk <= 0
+        64.times do
+            !10.ns
+            clk <= 1
+            !10.ns
+            clk <= 0
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_channel.rb

@@ -63,12 +63,13 @@ end
 
 
 # A system writing indefinitely to a channel.
+# Checking usage of channel without declaring a port.
 system :producer8 do |channel|
-    # puts "channel=#{channel}"
+    # puts "channel=#{channel}, channel methods=#{channel.methods}"
     # Inputs of the producer: clock and reset.
     input :clk, :rst
-    # Instantiate the channel ports
-    channel.output :ch
+    # # Instantiate the channel ports
+    # channel.output :ch
     # Inner 8-bit counter for generating values.
     [8].inner :counter
 
@@ -76,7 +77,8 @@ system :producer8 do |channel|
     par(clk.posedge) do
         hif(rst) { counter <= 0 }
         helse do
-            ch.write(counter) { counter <= counter + 1 }
+            # ch.write(counter) { counter <= counter + 1 }
+            channel.write(counter) { counter <= counter + 1 }
         end
     end
 end
@@ -96,20 +98,59 @@ system :consummer8 do |channel|
     end
 end
 
+# A system reading indefinitely from a channel.
+# Version without port declaration.
+system :consummer16 do |channel|
+    # Input of the consummer: a clock is enough.
+    input :clk
+    # # Instantiate the channel ports
+    # channel.input :ch
+    # Inner buffer for storing the cunsummed value.
+    [16].inner :buf
+
+    # The value consumption process
+    par(clk.posedge) do
+        # ch.read(buf)
+        channel.read(buf)
+    end
+end
+
 
 # A system testing the handshaker.
 system :hs_test do
     input :clk,:rst
 
-    # Declares the handshaker
-    handshaker([8]).(:hs)
+    # Declares two handshakers
+    handshaker([8]).(:hs0)
+    handshaker([16]).(:hs1)
 
     # # Sets the reset.
     # par(rst.posedge) { hs.reset }
+    
+    # For the first handshake
 
     # Instantiate the producer.
-    producer8(hs).(:producerI).(clk,rst)
+    producer8(hs0).(:producerI).(clk,rst)
 
     # Instantiate the consummer.
-    consummer8(hs).(:consummerI).(clk)
+    consummer8(hs0).(:consummerI).(clk)
+
+    # For the second handshaker
+    
+    # Instantiatethe consummer.
+    consummer16(hs1).(:consummer2I).(clk)
+
+    # Produce from within.
+    [16].inner :counter
+
+    # hs1.output :port
+
+    par(clk.posedge) do
+       hif(rst) { counter <= 0 }
+        helse do
+            # port.write(counter) { counter <= counter + 1 }
+            hs1.write(counter) { counter <= counter + 1 }
+        end
+    end
+
 end

data/lib/HDLRuby/hdr_samples/with_linear.rb

@@ -15,27 +15,36 @@ system :testmat do
     inner :clk,:rst, :req
 
     # Input memories
-    mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memL0)
+    # mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memL0)
+    # The first memory is 4-bank for testing purpose.
+    mem_bank([8],4,256/4,clk,rst, rinc: :rst,winc: :rst).(:memL0)
+    # The others are standard dual-edge memories.
     mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memL1)
     mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memR)
     # Access ports.
-    memL0.branch(:rinc).inner :readL0
-    memL1.branch(:rinc).inner :readL1
-    memR.branch(:rinc).inner :readR
+    # # memL0.branch(:rinc).inner :readL0
+    # # memL1.branch(:rinc).inner :readL1
+    # # memR.branch(:rinc).inner :readR
+    # memL0.branch(:rinc).input :readL0
+    # memL1.branch(:rinc).input :readL1
+    # memR.branch(:rinc).input :readR
 
     # Prepares the left and acc arrays.
-    lefts = [readL0, readL1]
+    # lefts = [readL0, readL1]
+    lefts = [memL0.branch(:rinc), memL1.branch(:rinc)]
 
     # Accumulators memory.
     mem_file([8],2,clk,rst,rinc: :rst).(:memAcc)
-    memAcc.branch(:anum).inner :accs
+    # # memAcc.branch(:anum).inner :accs
+    memAcc.branch(:anum).inout :accs
     accs_out = [accs.wrap(0), accs.wrap(1)]
 
     # Layer 0 ack.
     inner :ack0
     
     # Instantiate the matrix product.
-    mac_n1([8],clk,req,ack0,lefts,readR,accs_out)
+    # mac_n1([8],clk,req,ack0,lefts,readR,accs_out)
+    mac_n1([8],clk,req,ack0,lefts,memR.branch(:rinc),accs_out)
 
     # Translation.
     # Translation memory.
@@ -43,10 +52,12 @@ system :testmat do
     # Tarnslation result
     mem_file([8],2,clk,rst,rinc: :rst).(:memF)
     # Access ports.
-    memT.branch(:anum).inner :readT
-    memF.branch(:anum).inner :writeF
+    # # memT.branch(:anum).inner :readT
+    # # memF.branch(:anum).inner :writeF
+    memT.branch(:anum).input :readT
+    memF.branch(:anum).output :writeF
     regRs = [ readT.wrap(0), readT.wrap(1) ]
-    regLs = [ accs.wrap(0), accs.wrap(1) ]
+    regLs = accs_out
     regs =  [ writeF.wrap(0), writeF.wrap(1) ]
 
     # Translater ack.
@@ -61,9 +72,10 @@ system :testmat do
     # Input memories.
     mem_dual([8],2,clk,rst, rinc: :rst,winc: :rst).(:mem2L0)
     # Access ports.
-    mem2L0.branch(:rinc).inner :read2L0
-    # memAcc.branch(:rinc).inner :accsR
-    memF.branch(:rinc).inner :readF
+    # # mem2L0.branch(:rinc).inner :read2L0
+    # # memF.branch(:rinc).inner :readF
+    # mem2L0.branch(:rinc).input :read2L0
+    # memF.branch(:rinc).input :readF
 
     # Second layer ack.
     inner :ack1
@@ -73,29 +85,40 @@ system :testmat do
 
     sub do
         # Instantiate the second matrix product.
-        # mac([8],clk,req,read2L0,accsR,res)
-        mac([8],clk,ackT,ack1,read2L0,readF,channel_port(res))
+        # mac([8],clk,ackT,ack1,read2L0,readF,channel_port(res))
+        mac([8],clk,ackT,ack1,mem2L0.branch(:rinc),memF.branch(:rinc),
+            channel_port(res))
     end
 
 
 
     # The memory initializer.
-    memL0.branch(:winc).inner :writeL0
-    memL1.branch(:winc).inner :writeL1
-    memR.branch(:winc).inner :writeR
-    memT.branch(:winc).inner :writeT
-    mem2L0.branch(:winc).inner :write2L0
+    # # memL0.branch(:winc).inner :writeL0
+    # # memL1.branch(:winc).inner :writeL1
+    # # memR.branch(:winc).inner :writeR
+    # # memT.branch(:winc).inner :writeT
+    # # mem2L0.branch(:winc).inner :write2L0
+    # memL0.branch(:winc).output :writeL0
+    # memL1.branch(:winc).output :writeL1
+    # memR.branch(:winc).output :writeR
+    # mem2L0.branch(:winc).output :write2L0
+    # memT.branch(:winc).output :writeT
     inner :fill, :fill2
     [8].inner :val
     par(clk.posedge) do
         hif(fill) do
-            writeL0.write(val)
-            writeL1.write(val+1)
-            writeR.write(val+1)
+            # writeL0.write(val)
+            # writeL1.write(val+1)
+            # writeR.write(val+1)
+            memL0.branch(:winc).write(val)
+            memL1.branch(:winc).write(val+1)
+            memR.branch(:winc).write(val+1)
         end
         hif(fill2) do
-            write2L0.write(val+2)
-            writeT.write(val+2)
+            # write2L0.write(val+2)
+            # writeT.write(val+2)
+            mem2L0.branch(:winc).write(val+2)
+            memT.branch(:winc).write(val+2)
         end
     end
 

data/lib/HDLRuby/hdr_samples/with_loop.rb

@@ -0,0 +1,69 @@
+require 'std/loop.rb'
+
+include HDLRuby::High::Std
+
+system :with_loop do
+
+    # The clock and reset
+    inner :clk, :rst
+    # The running signals.
+    inner :doit0, :doit1
+    # The signal to check for finishing.
+    inner :over
+
+    # A counter.
+    [8].inner :count, :count2
+
+    # The first loop: basic while.
+    lp0 = while_loop(clk, proc{count<=0}, count<15) { count <= count + 1 }
+
+    # The second loop: 10 times.
+    lp1 = times_loop(clk,10) { count2 <= count2+2 }
+    # Control it using doit1 as req and over as ack.
+    rst_req_ack(clk.posedge,rst,doit1,over,lp1)
+
+    par(clk.posedge) do
+        doit1 <= 0
+        hif(rst) do
+            lp0.reset()
+            # lp1.reset()
+            # doit1 <= 0
+            count2 <= 0
+            over <= 0
+        end
+        helse do
+            hif(doit0) { lp0.run }
+            lp0.finish { doit0 <= 0; doit1 <= 1 }# ; lp1.run }
+            hif(doit1) { lp1.run; lp0.reset() }
+            # lp1.finish { over <= 1; doit1 <= 0 }
+            # Second pass for first loop.
+            hif(over)  { lp0.run }
+        end
+    end
+
+    timed do
+        clk <= 0
+        rst <= 0
+        doit0 <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        doit0 <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        64.times do
+            clk <= 0
+            !10.ns
+            clk <= 1
+            !10.ns
+        end
+    end
+end