HDLRuby 2.2.16 → 2.2.17

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -1301,14 +1301,7 @@ __The vector operator__ `[]` is used for building types representing vectors of
 <type>[<range>]
 ```
 
-The `<range>` of a vector type indicates the position of the starting and ending bits relatively to the radix point. If the position of the starting bit
-is on the left side of the range, the vector is big endian, otherwise it is little endian.  Negative values in a range are also possible and indicate positions bellow the radix point.  For example, the following code describes a big-endian fixed-point type with 8 bits above the radix point and 4 bits
-bellow:
-
-```ruby
-bit[7..-4]
-```
-
+The `<range>` of a vector type indicates the position of the starting and ending bits.
 A `n..0` range can also be abbreviated to `n+1`. For instance, the two following types are identical:
 
 ```ruby
@@ -2801,6 +2794,19 @@ bit[4,4].inner :sig
 
 When performing computation with fixed point types, HDLRuby ensures that the result's decimal point position is correct.
 
+In addition to the fixed point data type, a method is added to the literal objects (Numeric) to convert them to fixed point representation:
+
+```ruby
+<litteral>.to_fix(<number of bits after the decimal point>)
+```
+
+For example the following code converts a floating point value to a fixed point value with 16 bits after the decimal point:
+
+```
+3.178.to_fix(16)
+```
+
+
 ## Channel
 <a name="channel"></a>
 

data/lib/HDLRuby/hdr_samples/rom.rb

@@ -4,8 +4,8 @@ system :rom4_8 do
     [2..0].input :addr
     [7..0].output :data0,:data1,:data2
 
-    bit[7..0][0..7].constant content0: [1,2,3,4,5,6,7]
-    bit[7..0][-8].constant content1: [1,2,3,4,5,6,7]
+    bit[7..0][0..7].constant content0: [0,1,2,3,4,5,6,7]
+    bit[7..0][-8].constant content1: [0,1,2,3,4,5,6,7]
     bit[7..0][-8].constant content2: (8).times.to_a
 
     data0 <= content0[addr]

data/lib/HDLRuby/hdr_samples/with_fixpoint.rb

@@ -12,8 +12,9 @@ system :fix_test do
 
     # Performs calculation between then
     timed do
-        x <= _00110011
-        y <= _01000000
+        # x <= _00110011 # 3.1875
+        x <= 3.1875.to_fix(4)
+        y <= _01000000 # 4
         !10.ns
         z <= x + y
         !10.ns

data/lib/HDLRuby/hdrcc.rb

@@ -563,7 +563,7 @@ elsif $options[:clang] then
         end
         Dir.chdir($output)
         # Kernel.system("make -s")
-        Kernel.system("cc -o3 -o hruby_simulator *.c")
+        Kernel.system("cc -o3 -o hruby_simulator *.c -lpthread")
         Kernel.system("./hruby_simulator")
     end
 elsif $options[:verilog] then

data/lib/HDLRuby/hruby_low2high.rb

@@ -566,7 +566,7 @@ module HDLRuby::Low
         # +level+ is the hierachical level of the object.
         def to_high(level = 0)
             return self.child.to_high(level) + 
-                ".cast(" + self.type.to_high(level) + ")"
+                ".as(" + self.type.to_high(level) + ")"
         end
     end
 

data/lib/HDLRuby/hruby_low2vhd.rb

@@ -345,31 +345,34 @@ module HDLRuby::Low
             res << " " * (level*3)
             res << "entity #{Low2VHDL.entity_name(self.name)} is\n"
             # The ports
-            res << " " * ((level+1)*3)
-            res << "port (\n"
-            # Inputs
-            self.each_input do |input|
-                res << " " * ((level+2)*3)
-                res << Low2VHDL.vhdl_name(input.name) << ": in " 
-                res << input.type.to_vhdl << ";\n"
-            end
-            # Outputs
-            self.each_output do |output|
-                res << " " * ((level+2)*3)
-                res << Low2VHDL.vhdl_name(output.name) << ": out " 
-                res << output.type.to_vhdl << ";\n"
-            end
-            # Inouts
-            self.each_inout do |inout|
-                res << " " * ((level+2)*3)
-                res << Low2VHDL.vhdl_name(inout.name) << ": inout " 
-                res << inout.type.to_vhdl << ";\n"
+            if self.each_input.any? || self.each_output.any? ||
+                   self.each_inout.any? then
+                res << " " * ((level+1)*3)
+                res << "port (\n"
+                # Inputs
+                self.each_input do |input|
+                    res << " " * ((level+2)*3)
+                    res << Low2VHDL.vhdl_name(input.name) << ": in " 
+                    res << input.type.to_vhdl << ";\n"
+                end
+                # Outputs
+                self.each_output do |output|
+                    res << " " * ((level+2)*3)
+                    res << Low2VHDL.vhdl_name(output.name) << ": out " 
+                    res << output.type.to_vhdl << ";\n"
+                end
+                # Inouts
+                self.each_inout do |inout|
+                    res << " " * ((level+2)*3)
+                    res << Low2VHDL.vhdl_name(inout.name) << ": inout " 
+                    res << inout.type.to_vhdl << ";\n"
+                end
+                # Remove the last ";" for conforming with VHDL syntax.
+                res[-2..-1] = "\n" if res[-2] == ";"
+                res << " " * ((level+1)*3)
+                # Close the port declaration.
+                res << ");\n"
             end
-            # Remove the last ";" for conforming with VHDL syntax.
-            res[-2..-1] = "\n" if res[-2] == ";"
-            res << " " * ((level+1)*3)
-            # Close the port declaration.
-            res << ");\n"
             # Close the entity
             res << " " * (level*3)
             res << "end #{Low2VHDL.entity_name(self.name)};\n\n"
@@ -617,7 +620,17 @@ module HDLRuby::Low
             # # Simply generates the redefined type.
             # return self.def.to_vhdl(level)
             # Simply use the name of the type.
-            return Low2VHDL.vhdl_name(self.name)
+            # Is it a composite type?
+            if (self.def.is_a?(TypeStruct) ||
+              (self.def.is_a?(TypeVector) && 
+                    (self.def.base.is_a?(TypeVector) || 
+                     self.def.base.is_a?(TypeStruct))))
+                # Yes, generate a VHDL type definition.
+                return Low2VHDL.vhdl_name(self.name)
+            else
+                # No, generates the defined type.
+                return self.def.to_vhdl(level)
+            end
         end
     end
 
@@ -745,29 +758,31 @@ module HDLRuby::Low
                 res << Low2VHDL.vhdl_name(self.block.name) << ": "
             end
             res << "process "
-            # Generate the senitivity list.
-            if self.each_event.any? then
-                # If there is a clock.
-                res << "("
-                res << self.each_event.map do |event|
-                    event.ref.to_vhdl(level)
-                end.join(", ")
-                res << ")"
-            else
-                # If no clock, generate the sensitivity list from the right
-                # values.
-                list = self.block.each_node_deep.select do |node|
-                    node.is_a?(RefName) && !node.leftvalue? && 
-                        !node.parent.is_a?(RefName) &&
-                        # Also skip the variables
-                        !vars.find {|var| var.name == node.name }
-                end.to_a
-                # Keep only one ref per signal.
-                list.uniq! { |node| node.name }
-                # Generate the sensitivity list from it.
-                res << "("
-                res << list.map {|node| node.to_vhdl(level) }.join(", ")
-                res << ")"
+            # Generate the senitivity list if not a timed block.
+            unless self.block.is_a?(TimeBlock) then
+                if self.each_event.any? then
+                    # If there is a clock.
+                    res << "("
+                    res << self.each_event.map do |event|
+                        event.ref.to_vhdl(level)
+                    end.join(", ")
+                    res << ")"
+                else
+                    # If no clock, generate the sensitivity list from the right
+                    # values.
+                    list = self.block.each_node_deep.select do |node|
+                        node.is_a?(RefName) && !node.leftvalue? && 
+                            !node.parent.is_a?(RefName) &&
+                            # Also skip the variables
+                            !vars.find {|var| var.name == node.name }
+                    end.to_a
+                    # Keep only one ref per signal.
+                    list.uniq! { |node| node.name }
+                    # Generate the sensitivity list from it.
+                    res << "("
+                    res << list.map {|node| node.to_vhdl(level) }.join(", ")
+                    res << ")"
+                end
             end
             res << "\n"
             # Generate the variables.

data/lib/HDLRuby/hruby_verilog.rb

@@ -1630,12 +1630,20 @@ end
 # If it is signed, it outputs signed.
 # Enhance Type with generation of verilog code.
 class Type
-    # Converts the system to Verilog code.
+    # Converts the type to Verilog code.
     def to_verilog
         return self.name == :signed ? "#{self.name.to_s} " : ""
     end
 end
 
+# Replace type by refered type.
+class TypeDef
+    # Converts the type to verilog code.
+    def to_verilog
+        return self.def.to_verilog
+    end
+end
+
 # Use it when collecting.
 class Concat
     def to_verilog    

data/lib/HDLRuby/sim/hruby_sim_calc.c

@@ -5,6 +5,10 @@
 #include <limits.h>
 #include "hruby_sim.h"
 
+#ifndef alloca
+#define alloca(x)  __builtin_alloca(x)
+#endif
+
 
 /**
  *  The HDLRuby simulation calculation engine, to be used with C code

data/lib/HDLRuby/std/fixpoint.rb

@@ -62,6 +62,14 @@ module HDLRuby::High::Std
         end
     end
 
+    # Extends the Numeric class for conversion to fixed point litteral.
+    class ::Numeric
+        # Convert to fixed point value with +dec+ digits after the decimal
+        # point.
+        def to_fix(dec)
+            return (self * (2**dec.to_i)).to_i
+        end
+    end
 
 
 end

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.2.16"
+  VERSION = "2.2.17"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.2.16
+  version: 2.2.17
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-04-01 00:00:00.000000000 Z
+date: 2020-04-22 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler