HDLRuby 2.2.16 → 2.2.17
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- checksums.yaml +4 -4
- data/README.md +14 -8
- data/lib/HDLRuby/hdr_samples/rom.rb +2 -2
- data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +3 -2
- data/lib/HDLRuby/hdrcc.rb +1 -1
- data/lib/HDLRuby/hruby_low2high.rb +1 -1
- data/lib/HDLRuby/hruby_low2vhd.rb +63 -48
- data/lib/HDLRuby/hruby_verilog.rb +9 -1
- data/lib/HDLRuby/sim/hruby_sim_calc.c +4 -0
- data/lib/HDLRuby/std/fixpoint.rb +8 -0
- data/lib/HDLRuby/version.rb +1 -1
- metadata +2 -2
checksums.yaml
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: f9512393bdc65c3c2ae471d471b30d911cb693b8c1bc18a20186320286f27602
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data.tar.gz: 8a5bce50d367d52c181779ce834b2cfb3ecb14fe3c6ce96388eade344692e616
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 8cc2e806c2eb5d5ea9e4bc2c5cc449f2a0f6ca7270b73232efcc3fb9ae7bacdd074e2995f9233547fc47dae4ccfd98ab9b41d3903cee87374247cc4f68e353e4
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data.tar.gz: 698b4bd637fe294d0bf27fa163ef3c52528260cf443482d9e9a4922a56032db8400d8f95af67a3b62d67e949840c437869512514cb0db575c5b8c7b1b9b7fad9
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data/README.md
CHANGED
@@ -1301,14 +1301,7 @@ __The vector operator__ `[]` is used for building types representing vectors of
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<type>[<range>]
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```
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-
The `<range>` of a vector type indicates the position of the starting and ending bits
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is on the left side of the range, the vector is big endian, otherwise it is little endian. Negative values in a range are also possible and indicate positions bellow the radix point. For example, the following code describes a big-endian fixed-point type with 8 bits above the radix point and 4 bits
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bellow:
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```ruby
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bit[7..-4]
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```
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-
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The `<range>` of a vector type indicates the position of the starting and ending bits.
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A `n..0` range can also be abbreviated to `n+1`. For instance, the two following types are identical:
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```ruby
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@@ -2801,6 +2794,19 @@ bit[4,4].inner :sig
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When performing computation with fixed point types, HDLRuby ensures that the result's decimal point position is correct.
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In addition to the fixed point data type, a method is added to the literal objects (Numeric) to convert them to fixed point representation:
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```ruby
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2800
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<litteral>.to_fix(<number of bits after the decimal point>)
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```
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For example the following code converts a floating point value to a fixed point value with 16 bits after the decimal point:
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```
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2806
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3.178.to_fix(16)
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```
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## Channel
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<a name="channel"></a>
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@@ -4,8 +4,8 @@ system :rom4_8 do
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4
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[2..0].input :addr
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[7..0].output :data0,:data1,:data2
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bit[7..0][0..7].constant content0: [1,2,3,4,5,6,7]
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bit[7..0][-8].constant content1: [1,2,3,4,5,6,7]
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bit[7..0][0..7].constant content0: [0,1,2,3,4,5,6,7]
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bit[7..0][-8].constant content1: [0,1,2,3,4,5,6,7]
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bit[7..0][-8].constant content2: (8).times.to_a
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data0 <= content0[addr]
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data/lib/HDLRuby/hdrcc.rb
CHANGED
@@ -563,7 +563,7 @@ elsif $options[:clang] then
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end
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Dir.chdir($output)
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# Kernel.system("make -s")
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Kernel.system("cc -o3 -o hruby_simulator *.c")
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Kernel.system("cc -o3 -o hruby_simulator *.c -lpthread")
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Kernel.system("./hruby_simulator")
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end
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elsif $options[:verilog] then
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@@ -345,31 +345,34 @@ module HDLRuby::Low
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res << " " * (level*3)
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res << "entity #{Low2VHDL.entity_name(self.name)} is\n"
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# The ports
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-
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if self.each_input.any? || self.each_output.any? ||
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self.each_inout.any? then
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res << " " * ((level+1)*3)
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res << "port (\n"
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# Inputs
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self.each_input do |input|
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res << " " * ((level+2)*3)
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res << Low2VHDL.vhdl_name(input.name) << ": in "
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res << input.type.to_vhdl << ";\n"
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end
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# Outputs
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self.each_output do |output|
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res << " " * ((level+2)*3)
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res << Low2VHDL.vhdl_name(output.name) << ": out "
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res << output.type.to_vhdl << ";\n"
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end
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# Inouts
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self.each_inout do |inout|
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res << " " * ((level+2)*3)
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res << Low2VHDL.vhdl_name(inout.name) << ": inout "
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res << inout.type.to_vhdl << ";\n"
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end
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# Remove the last ";" for conforming with VHDL syntax.
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res[-2..-1] = "\n" if res[-2] == ";"
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res << " " * ((level+1)*3)
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# Close the port declaration.
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res << ");\n"
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end
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# Remove the last ";" for conforming with VHDL syntax.
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-
res[-2..-1] = "\n" if res[-2] == ";"
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res << " " * ((level+1)*3)
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# Close the port declaration.
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res << ");\n"
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# Close the entity
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res << " " * (level*3)
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res << "end #{Low2VHDL.entity_name(self.name)};\n\n"
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@@ -617,7 +620,17 @@ module HDLRuby::Low
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# # Simply generates the redefined type.
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# return self.def.to_vhdl(level)
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# Simply use the name of the type.
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-
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# Is it a composite type?
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if (self.def.is_a?(TypeStruct) ||
|
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(self.def.is_a?(TypeVector) &&
|
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(self.def.base.is_a?(TypeVector) ||
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self.def.base.is_a?(TypeStruct))))
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# Yes, generate a VHDL type definition.
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return Low2VHDL.vhdl_name(self.name)
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else
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# No, generates the defined type.
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return self.def.to_vhdl(level)
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end
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end
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end
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@@ -745,29 +758,31 @@ module HDLRuby::Low
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res << Low2VHDL.vhdl_name(self.block.name) << ": "
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end
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res << "process "
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# Generate the senitivity list.
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-
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-
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-
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-
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# Generate the senitivity list if not a timed block.
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unless self.block.is_a?(TimeBlock) then
|
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if self.each_event.any? then
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# If there is a clock.
|
765
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res << "("
|
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res << self.each_event.map do |event|
|
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event.ref.to_vhdl(level)
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end.join(", ")
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res << ")"
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else
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# If no clock, generate the sensitivity list from the right
|
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# values.
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list = self.block.each_node_deep.select do |node|
|
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node.is_a?(RefName) && !node.leftvalue? &&
|
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!node.parent.is_a?(RefName) &&
|
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# Also skip the variables
|
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!vars.find {|var| var.name == node.name }
|
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end.to_a
|
779
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+
# Keep only one ref per signal.
|
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+
list.uniq! { |node| node.name }
|
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+
# Generate the sensitivity list from it.
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+
res << "("
|
783
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+
res << list.map {|node| node.to_vhdl(level) }.join(", ")
|
784
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res << ")"
|
785
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+
end
|
771
786
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end
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res << "\n"
|
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# Generate the variables.
|
@@ -1630,12 +1630,20 @@ end
|
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# If it is signed, it outputs signed.
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# Enhance Type with generation of verilog code.
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class Type
|
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-
# Converts the
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# Converts the type to Verilog code.
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1634
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def to_verilog
|
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1635
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return self.name == :signed ? "#{self.name.to_s} " : ""
|
1636
1636
|
end
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1637
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end
|
1638
1638
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1639
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# Replace type by refered type.
|
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+
class TypeDef
|
1641
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+
# Converts the type to verilog code.
|
1642
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+
def to_verilog
|
1643
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+
return self.def.to_verilog
|
1644
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+
end
|
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end
|
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# Use it when collecting.
|
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class Concat
|
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def to_verilog
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data/lib/HDLRuby/std/fixpoint.rb
CHANGED
@@ -62,6 +62,14 @@ module HDLRuby::High::Std
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end
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end
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65
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# Extends the Numeric class for conversion to fixed point litteral.
|
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class ::Numeric
|
67
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+
# Convert to fixed point value with +dec+ digits after the decimal
|
68
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+
# point.
|
69
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+
def to_fix(dec)
|
70
|
+
return (self * (2**dec.to_i)).to_i
|
71
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+
end
|
72
|
+
end
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end
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data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
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1
1
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--- !ruby/object:Gem::Specification
|
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2
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name: HDLRuby
|
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version: !ruby/object:Gem::Version
|
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-
version: 2.2.
|
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version: 2.2.17
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platform: ruby
|
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authors:
|
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- Lovic Gauthier
|
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autorequire:
|
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bindir: exe
|
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cert_chain: []
|
11
|
-
date: 2020-04-
|
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+
date: 2020-04-22 00:00:00.000000000 Z
|
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dependencies:
|
13
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- !ruby/object:Gem::Dependency
|
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name: bundler
|