HDLRuby 2.2.14 → 2.3.1
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- checksums.yaml +4 -4
- data/README.md +14 -8
- data/lib/HDLRuby/hdr_samples/linear_test.rb +235 -0
- data/lib/HDLRuby/hdr_samples/rom.rb +2 -2
- data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb +96 -0
- data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +3 -2
- data/lib/HDLRuby/hdr_samples/with_linear.rb +166 -0
- data/lib/HDLRuby/hdr_samples/with_loop.rb +69 -0
- data/lib/HDLRuby/hdr_samples/with_memory.rb +13 -3
- data/lib/HDLRuby/hdrcc.rb +1 -1
- data/lib/HDLRuby/hruby_high.rb +12 -4
- data/lib/HDLRuby/hruby_low.rb +25 -28
- data/lib/HDLRuby/hruby_low2c.rb +10 -5
- data/lib/HDLRuby/hruby_low2high.rb +1 -1
- data/lib/HDLRuby/hruby_low2vhd.rb +63 -48
- data/lib/HDLRuby/hruby_low_fix_types.rb +6 -2
- data/lib/HDLRuby/hruby_low_mutable.rb +2 -1
- data/lib/HDLRuby/hruby_low_resolve.rb +7 -4
- data/lib/HDLRuby/hruby_low_without_concat.rb +8 -4
- data/lib/HDLRuby/hruby_types.rb +82 -72
- data/lib/HDLRuby/hruby_verilog.rb +9 -1
- data/lib/HDLRuby/sim/hruby_sim.h +21 -0
- data/lib/HDLRuby/sim/hruby_sim_calc.c +254 -18
- data/lib/HDLRuby/std/channel.rb +103 -32
- data/lib/HDLRuby/std/fixpoint.rb +15 -6
- data/lib/HDLRuby/std/linear.rb +317 -0
- data/lib/HDLRuby/std/loop.rb +101 -0
- data/lib/HDLRuby/std/memory.rb +1000 -30
- data/lib/HDLRuby/std/task.rb +850 -0
- data/lib/HDLRuby/version.rb +1 -1
- metadata +9 -2
@@ -0,0 +1,69 @@
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require 'std/loop.rb'
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include HDLRuby::High::Std
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system :with_loop do
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# The clock and reset
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inner :clk, :rst
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# The running signals.
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inner :doit0, :doit1
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# The signal to check for finishing.
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inner :over
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# A counter.
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[8].inner :count, :count2
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# The first loop: basic while.
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lp0 = while_loop(clk, proc{count<=0}, count<15) { count <= count + 1 }
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# The second loop: 10 times.
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lp1 = times_loop(clk,10) { count2 <= count2+2 }
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# Control it using doit1 as req and over as ack.
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rst_req_ack(clk.posedge,rst,doit1,over,lp1)
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par(clk.posedge) do
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doit1 <= 0
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hif(rst) do
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lp0.reset()
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# lp1.reset()
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# doit1 <= 0
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count2 <= 0
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over <= 0
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end
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helse do
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hif(doit0) { lp0.run }
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lp0.finish { doit0 <= 0; doit1 <= 1 }# ; lp1.run }
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hif(doit1) { lp1.run; lp0.reset() }
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# lp1.finish { over <= 1; doit1 <= 0 }
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# Second pass for first loop.
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hif(over) { lp0.run }
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end
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end
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timed do
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clk <= 0
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rst <= 0
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doit0 <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 1
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 0
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doit0 <= 1
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!10.ns
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clk <= 1
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!10.ns
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64.times do
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clk <= 0
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!10.ns
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clk <= 1
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!10.ns
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end
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end
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end
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@@ -108,16 +108,26 @@ system :mem_test do
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end
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[8].inner :
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[8].inner :sum0, :sum1
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# Declares a dual edge 8-bit data and address memory.
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mem_dual([8],256,clk,rst, raddr: :rst,waddr: :rst).(:memDI)
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# Instantiate the producer to access port waddr of the memory.
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producer(memDI.branch(:waddr)).(:
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producer(memDI.branch(:waddr)).(:producerI0).(clk,rst)
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# Instantiate the producer to access port raddr of the memory.
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consumer(memDI.branch(:raddr)).(:
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consumer(memDI.branch(:raddr)).(:consumerI0).(clk,rst,sum0)
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# Declares a 4-bank 8-bit data and address memory.
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mem_bank([8],4,256/4,clk,rst, raddr: :rst, waddr: :rst).(:memBI)
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# Instantiate the producer to access port waddr of the memory.
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producer(memBI.branch(:waddr)).(:producerI1).(clk,rst)
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# Instantiate the producer to access port raddr of the memory.
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consumer(memBI.branch(:raddr)).(:consumerI1).(clk,rst,sum1)
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end
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data/lib/HDLRuby/hdrcc.rb
CHANGED
@@ -563,7 +563,7 @@ elsif $options[:clang] then
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end
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Dir.chdir($output)
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# Kernel.system("make -s")
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-
Kernel.system("cc -o3 -o hruby_simulator *.c")
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Kernel.system("cc -o3 -o hruby_simulator *.c -lpthread")
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Kernel.system("./hruby_simulator")
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end
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elsif $options[:verilog] then
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data/lib/HDLRuby/hruby_high.rb
CHANGED
@@ -1308,6 +1308,12 @@ module HDLRuby::High
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return true
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end
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# Converts to a type.
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# Returns self since it is already a type.
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def to_type
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return self
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end
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# Sets the +name+.
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#
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# NOTE: can only be done if the name is not already set.
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@@ -1851,16 +1857,18 @@ module HDLRuby::High
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# NOTE: a function is a short-cut for a method that creates a scope.
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def function(name, &ruby_block)
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if HDLRuby::High.in_system? then
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define_singleton_method(name.to_sym) do |*args|
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define_singleton_method(name.to_sym) do |*args,&other_block|
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sub do
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HDLRuby::High.top_user.instance_exec(*args
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HDLRuby::High.top_user.instance_exec(*args,*other_block,
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&ruby_block)
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# ruby_block.call(*args)
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end
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end
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else
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define_method(name.to_sym) do |*args|
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define_method(name.to_sym) do |*args,&other_block|
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sub do
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HDLRuby::High.top_user.instance_exec(*args
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HDLRuby::High.top_user.instance_exec(*args,*other_block,
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&ruby_block)
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end
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end
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end
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data/lib/HDLRuby/hruby_low.rb
CHANGED
@@ -1385,7 +1385,8 @@ module HDLRuby::Low
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# NOTE: type definition are actually type with a name refering to another
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# type (and equivalent to it).
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class TypeDef < Type
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-
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# Moved to constructor
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# extend Forwardable
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# The definition of the type.
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attr_reader :def
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@@ -1402,6 +1403,19 @@ module HDLRuby::Low
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end
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# Set the referened type.
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@def = type
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# Sets the delegations
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self.extend Forwardable
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[ :signed?, :unsigned?, :fixed?, :float?, :leaf?,
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:width, :range?, :range, :base?, :base, :types?,
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:get_all_types, :get_type, :each, :each_type,
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:regular?,
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:each_name,
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:equivalent? ].each do |meth|
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if @def.respond_to?(meth)
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self.def_delegator :@def, meth
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end
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end
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end
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# Comparison for hash: structural comparison.
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@def.each_type_deep(&ruby_block)
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end
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#
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# Moved to constructor
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# # Delegate the type methods to the ref.
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# def_delegators :@def,
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# :signed?, :unsigned?, :fixed?, :float?, :leaf?,
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# :width, :range?, :range, :base?, :base, :types?,
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# :get_all_types, :get_type, :each, :each_type,
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# :regular?,
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# :each_name,
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# :equivalent?
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end
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@@ -3059,24 +3074,6 @@ module HDLRuby::Low
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return [@value,@whens,@default].hash
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end
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# # Adds a possible +match+ for the case's value that lead to the
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# # execution of +statement+.
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# def add_when(match,statement)
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# # Checks the match.
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# unless match.is_a?(Expression)
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# raise AnyError, "Invalid class for a case match: #{match.class}"
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# end
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# # Checks statement.
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# unless statement.is_a?(Statement)
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# raise AnyError, "Invalid class for a statement: #{statement.class}"
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# end
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# # Add the case.
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# @whens << [match,statement]
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# # And set their parents.
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# match.parent = statement.parent = self
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# [match,statement]
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# end
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# Adds possible when case +w+.
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def add_when(w)
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# Check +w+.
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# Clones the Case (deeply)
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def clone
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# Clone the default if any.
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-
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default = @default ? @default.clone : nil
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# Clone the case.
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return Case.new(@value.clone,default,(@whens.map do |w|
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w.clone
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data/lib/HDLRuby/hruby_low2c.rb
CHANGED
@@ -546,9 +546,10 @@ module HDLRuby::Low
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#
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# NOTE: type tuples are converted to bit vector of their contents.
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def to_c(level = 0)
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return "get_type_tuple(#{self.each.join(",") do |type|
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-
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end})"
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# return "get_type_tuple(#{self.each.to_a.join(",") do |type|
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# type.to_c(level+1)
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# end})"
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return self.to_vector.to_c(level)
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end
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end
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@@ -1872,7 +1873,8 @@ module HDLRuby::Low
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res << "idx = value2integer(#{self.index.to_c(level+2)});\n"
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# Make the access.
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res << (" " * ((level+1)*3))
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res << "dst = read_range(ref,idx,idx,#{self.ref.type.base.to_c(level)},dst);\n"
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# res << "dst = read_range(ref,idx,idx,#{self.ref.type.base.to_c(level)},dst);\n"
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res << "dst = read_range(ref,idx,idx,#{self.type.to_c(level)},dst);\n"
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# Restore the state of the value pool.
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res << (" " * ((level+1)*3))
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res << "set_value_pos(pool_state);\n"
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@@ -1930,7 +1932,9 @@ module HDLRuby::Low
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res << "last = value2integer(#{self.range.last.to_c(level+2)});\n"
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# Make the access.
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res << (" " * ((level+1)*3))
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-
res << "dst = #{command}_range(ref,first,last,#{self.ref.type.base.to_c(level)},dst);\n"
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# res << "dst = #{command}_range(ref,first,last,#{self.ref.type.base.to_c(level)},dst);\n"
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# puts "will read_range for #{self.ref.name} with width=#{self.ref.type.width} with base width=#{self.ref.type.base.width} with range=#{self.ref.type.range} with range=#{self.range.first.content}..#{self.range.last.content}"
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res << "dst = #{command}_range(ref,first,last,#{self.type.base.to_c(level)},dst);\n"
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# Restore the state of the value pool.
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res << (" " * ((level+1)*3))
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res << "set_value_pos(pool_state);\n"
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@@ -1961,6 +1965,7 @@ module HDLRuby::Low
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# Generates the C text for reference as left value to a signal.
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# +level+ is the hierarchical level of the object.
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def to_c_signal(level = 0)
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# puts "to_c_signal with self=#{self.name}, resolve=#{self.resolve}"
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return "#{self.resolve.to_c_signal(level+1)}"
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end
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end
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@@ -345,31 +345,34 @@ module HDLRuby::Low
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res << " " * (level*3)
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res << "entity #{Low2VHDL.entity_name(self.name)} is\n"
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# The ports
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-
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-
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-
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-
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+
if self.each_input.any? || self.each_output.any? ||
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self.each_inout.any? then
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res << " " * ((level+1)*3)
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res << "port (\n"
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# Inputs
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self.each_input do |input|
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res << " " * ((level+2)*3)
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res << Low2VHDL.vhdl_name(input.name) << ": in "
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res << input.type.to_vhdl << ";\n"
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+
end
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# Outputs
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359
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+
self.each_output do |output|
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+
res << " " * ((level+2)*3)
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res << Low2VHDL.vhdl_name(output.name) << ": out "
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res << output.type.to_vhdl << ";\n"
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+
end
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# Inouts
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365
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self.each_inout do |inout|
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+
res << " " * ((level+2)*3)
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res << Low2VHDL.vhdl_name(inout.name) << ": inout "
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res << inout.type.to_vhdl << ";\n"
|
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+
end
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+
# Remove the last ";" for conforming with VHDL syntax.
|
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+
res[-2..-1] = "\n" if res[-2] == ";"
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+
res << " " * ((level+1)*3)
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+
# Close the port declaration.
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+
res << ");\n"
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367
375
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end
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368
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-
# Remove the last ";" for conforming with VHDL syntax.
|
369
|
-
res[-2..-1] = "\n" if res[-2] == ";"
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-
res << " " * ((level+1)*3)
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-
# Close the port declaration.
|
372
|
-
res << ");\n"
|
373
376
|
# Close the entity
|
374
377
|
res << " " * (level*3)
|
375
378
|
res << "end #{Low2VHDL.entity_name(self.name)};\n\n"
|
@@ -617,7 +620,17 @@ module HDLRuby::Low
|
|
617
620
|
# # Simply generates the redefined type.
|
618
621
|
# return self.def.to_vhdl(level)
|
619
622
|
# Simply use the name of the type.
|
620
|
-
|
623
|
+
# Is it a composite type?
|
624
|
+
if (self.def.is_a?(TypeStruct) ||
|
625
|
+
(self.def.is_a?(TypeVector) &&
|
626
|
+
(self.def.base.is_a?(TypeVector) ||
|
627
|
+
self.def.base.is_a?(TypeStruct))))
|
628
|
+
# Yes, generate a VHDL type definition.
|
629
|
+
return Low2VHDL.vhdl_name(self.name)
|
630
|
+
else
|
631
|
+
# No, generates the defined type.
|
632
|
+
return self.def.to_vhdl(level)
|
633
|
+
end
|
621
634
|
end
|
622
635
|
end
|
623
636
|
|
@@ -745,29 +758,31 @@ module HDLRuby::Low
|
|
745
758
|
res << Low2VHDL.vhdl_name(self.block.name) << ": "
|
746
759
|
end
|
747
760
|
res << "process "
|
748
|
-
# Generate the senitivity list.
|
749
|
-
|
750
|
-
|
751
|
-
|
752
|
-
|
753
|
-
|
754
|
-
|
755
|
-
|
756
|
-
|
757
|
-
|
758
|
-
|
759
|
-
|
760
|
-
|
761
|
-
|
762
|
-
|
763
|
-
|
764
|
-
|
765
|
-
|
766
|
-
|
767
|
-
|
768
|
-
|
769
|
-
|
770
|
-
|
761
|
+
# Generate the senitivity list if not a timed block.
|
762
|
+
unless self.block.is_a?(TimeBlock) then
|
763
|
+
if self.each_event.any? then
|
764
|
+
# If there is a clock.
|
765
|
+
res << "("
|
766
|
+
res << self.each_event.map do |event|
|
767
|
+
event.ref.to_vhdl(level)
|
768
|
+
end.join(", ")
|
769
|
+
res << ")"
|
770
|
+
else
|
771
|
+
# If no clock, generate the sensitivity list from the right
|
772
|
+
# values.
|
773
|
+
list = self.block.each_node_deep.select do |node|
|
774
|
+
node.is_a?(RefName) && !node.leftvalue? &&
|
775
|
+
!node.parent.is_a?(RefName) &&
|
776
|
+
# Also skip the variables
|
777
|
+
!vars.find {|var| var.name == node.name }
|
778
|
+
end.to_a
|
779
|
+
# Keep only one ref per signal.
|
780
|
+
list.uniq! { |node| node.name }
|
781
|
+
# Generate the sensitivity list from it.
|
782
|
+
res << "("
|
783
|
+
res << list.map {|node| node.to_vhdl(level) }.join(", ")
|
784
|
+
res << ")"
|
785
|
+
end
|
771
786
|
end
|
772
787
|
res << "\n"
|
773
788
|
# Generate the variables.
|
@@ -294,6 +294,8 @@ module HDLRuby::Low
|
|
294
294
|
# Is there a type to match?
|
295
295
|
if type then
|
296
296
|
# Yes, update the concat to the type.
|
297
|
+
# Get the real type in case of typedef.
|
298
|
+
type = type.def while type.is_a?(TypeDef)
|
297
299
|
# Is it an array type?
|
298
300
|
if type.is_a?(TypeVector) then
|
299
301
|
# Yes, update the concat without subcasting.
|
@@ -302,14 +304,16 @@ module HDLRuby::Low
|
|
302
304
|
end)
|
303
305
|
else
|
304
306
|
# No, it should be a tuple.
|
305
|
-
return Concat.new(type,
|
307
|
+
return Concat.new(type,
|
308
|
+
self.each_expression.map.with_index do
|
306
309
|
|expr,i|
|
307
310
|
expr.explicit_types(type.get_type(i))
|
308
311
|
end)
|
309
312
|
end
|
310
313
|
else
|
311
314
|
# No, recurse on the sub expressions.
|
312
|
-
return Concat.new(self.type,
|
315
|
+
return Concat.new(self.type,
|
316
|
+
self.each_expression.map do |expr|
|
313
317
|
expr.explicit_types
|
314
318
|
end)
|
315
319
|
end
|
@@ -1069,7 +1069,8 @@ module HDLRuby::Low
|
|
1069
1069
|
node2rep = node2reassign.map {|n,r| [n,r[0]] }.to_h
|
1070
1070
|
|
1071
1071
|
# First recurse on the sub blocks.
|
1072
|
-
self.each_block { |block| block.reassign_expressions!(node2rep) }
|
1072
|
+
# self.each_block { |block| block.reassign_expressions!(node2rep) }
|
1073
|
+
self.each_block { |block| block.reassign_expressions!(node2reassign) }
|
1073
1074
|
|
1074
1075
|
# Now work on the block.
|
1075
1076
|
# Replace on the statements.
|