HDLRuby 2.2.14 → 2.3.1
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/README.md +14 -8
- data/lib/HDLRuby/hdr_samples/linear_test.rb +235 -0
- data/lib/HDLRuby/hdr_samples/rom.rb +2 -2
- data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb +96 -0
- data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +3 -2
- data/lib/HDLRuby/hdr_samples/with_linear.rb +166 -0
- data/lib/HDLRuby/hdr_samples/with_loop.rb +69 -0
- data/lib/HDLRuby/hdr_samples/with_memory.rb +13 -3
- data/lib/HDLRuby/hdrcc.rb +1 -1
- data/lib/HDLRuby/hruby_high.rb +12 -4
- data/lib/HDLRuby/hruby_low.rb +25 -28
- data/lib/HDLRuby/hruby_low2c.rb +10 -5
- data/lib/HDLRuby/hruby_low2high.rb +1 -1
- data/lib/HDLRuby/hruby_low2vhd.rb +63 -48
- data/lib/HDLRuby/hruby_low_fix_types.rb +6 -2
- data/lib/HDLRuby/hruby_low_mutable.rb +2 -1
- data/lib/HDLRuby/hruby_low_resolve.rb +7 -4
- data/lib/HDLRuby/hruby_low_without_concat.rb +8 -4
- data/lib/HDLRuby/hruby_types.rb +82 -72
- data/lib/HDLRuby/hruby_verilog.rb +9 -1
- data/lib/HDLRuby/sim/hruby_sim.h +21 -0
- data/lib/HDLRuby/sim/hruby_sim_calc.c +254 -18
- data/lib/HDLRuby/std/channel.rb +103 -32
- data/lib/HDLRuby/std/fixpoint.rb +15 -6
- data/lib/HDLRuby/std/linear.rb +317 -0
- data/lib/HDLRuby/std/loop.rb +101 -0
- data/lib/HDLRuby/std/memory.rb +1000 -30
- data/lib/HDLRuby/std/task.rb +850 -0
- data/lib/HDLRuby/version.rb +1 -1
- metadata +9 -2
@@ -0,0 +1,69 @@
|
|
1
|
+
require 'std/loop.rb'
|
2
|
+
|
3
|
+
include HDLRuby::High::Std
|
4
|
+
|
5
|
+
system :with_loop do
|
6
|
+
|
7
|
+
# The clock and reset
|
8
|
+
inner :clk, :rst
|
9
|
+
# The running signals.
|
10
|
+
inner :doit0, :doit1
|
11
|
+
# The signal to check for finishing.
|
12
|
+
inner :over
|
13
|
+
|
14
|
+
# A counter.
|
15
|
+
[8].inner :count, :count2
|
16
|
+
|
17
|
+
# The first loop: basic while.
|
18
|
+
lp0 = while_loop(clk, proc{count<=0}, count<15) { count <= count + 1 }
|
19
|
+
|
20
|
+
# The second loop: 10 times.
|
21
|
+
lp1 = times_loop(clk,10) { count2 <= count2+2 }
|
22
|
+
# Control it using doit1 as req and over as ack.
|
23
|
+
rst_req_ack(clk.posedge,rst,doit1,over,lp1)
|
24
|
+
|
25
|
+
par(clk.posedge) do
|
26
|
+
doit1 <= 0
|
27
|
+
hif(rst) do
|
28
|
+
lp0.reset()
|
29
|
+
# lp1.reset()
|
30
|
+
# doit1 <= 0
|
31
|
+
count2 <= 0
|
32
|
+
over <= 0
|
33
|
+
end
|
34
|
+
helse do
|
35
|
+
hif(doit0) { lp0.run }
|
36
|
+
lp0.finish { doit0 <= 0; doit1 <= 1 }# ; lp1.run }
|
37
|
+
hif(doit1) { lp1.run; lp0.reset() }
|
38
|
+
# lp1.finish { over <= 1; doit1 <= 0 }
|
39
|
+
# Second pass for first loop.
|
40
|
+
hif(over) { lp0.run }
|
41
|
+
end
|
42
|
+
end
|
43
|
+
|
44
|
+
timed do
|
45
|
+
clk <= 0
|
46
|
+
rst <= 0
|
47
|
+
doit0 <= 0
|
48
|
+
!10.ns
|
49
|
+
clk <= 1
|
50
|
+
!10.ns
|
51
|
+
clk <= 0
|
52
|
+
rst <= 1
|
53
|
+
!10.ns
|
54
|
+
clk <= 1
|
55
|
+
!10.ns
|
56
|
+
clk <= 0
|
57
|
+
rst <= 0
|
58
|
+
doit0 <= 1
|
59
|
+
!10.ns
|
60
|
+
clk <= 1
|
61
|
+
!10.ns
|
62
|
+
64.times do
|
63
|
+
clk <= 0
|
64
|
+
!10.ns
|
65
|
+
clk <= 1
|
66
|
+
!10.ns
|
67
|
+
end
|
68
|
+
end
|
69
|
+
end
|
@@ -108,16 +108,26 @@ system :mem_test do
|
|
108
108
|
end
|
109
109
|
|
110
110
|
|
111
|
-
[8].inner :
|
111
|
+
[8].inner :sum0, :sum1
|
112
112
|
|
113
113
|
# Declares a dual edge 8-bit data and address memory.
|
114
114
|
mem_dual([8],256,clk,rst, raddr: :rst,waddr: :rst).(:memDI)
|
115
115
|
|
116
116
|
# Instantiate the producer to access port waddr of the memory.
|
117
|
-
producer(memDI.branch(:waddr)).(:
|
117
|
+
producer(memDI.branch(:waddr)).(:producerI0).(clk,rst)
|
118
118
|
|
119
119
|
# Instantiate the producer to access port raddr of the memory.
|
120
|
-
consumer(memDI.branch(:raddr)).(:
|
120
|
+
consumer(memDI.branch(:raddr)).(:consumerI0).(clk,rst,sum0)
|
121
|
+
|
122
|
+
|
123
|
+
# Declares a 4-bank 8-bit data and address memory.
|
124
|
+
mem_bank([8],4,256/4,clk,rst, raddr: :rst, waddr: :rst).(:memBI)
|
125
|
+
|
126
|
+
# Instantiate the producer to access port waddr of the memory.
|
127
|
+
producer(memBI.branch(:waddr)).(:producerI1).(clk,rst)
|
128
|
+
|
129
|
+
# Instantiate the producer to access port raddr of the memory.
|
130
|
+
consumer(memBI.branch(:raddr)).(:consumerI1).(clk,rst,sum1)
|
121
131
|
|
122
132
|
|
123
133
|
end
|
data/lib/HDLRuby/hdrcc.rb
CHANGED
@@ -563,7 +563,7 @@ elsif $options[:clang] then
|
|
563
563
|
end
|
564
564
|
Dir.chdir($output)
|
565
565
|
# Kernel.system("make -s")
|
566
|
-
Kernel.system("cc -o3 -o hruby_simulator *.c")
|
566
|
+
Kernel.system("cc -o3 -o hruby_simulator *.c -lpthread")
|
567
567
|
Kernel.system("./hruby_simulator")
|
568
568
|
end
|
569
569
|
elsif $options[:verilog] then
|
data/lib/HDLRuby/hruby_high.rb
CHANGED
@@ -1308,6 +1308,12 @@ module HDLRuby::High
|
|
1308
1308
|
return true
|
1309
1309
|
end
|
1310
1310
|
|
1311
|
+
# Converts to a type.
|
1312
|
+
# Returns self since it is already a type.
|
1313
|
+
def to_type
|
1314
|
+
return self
|
1315
|
+
end
|
1316
|
+
|
1311
1317
|
# Sets the +name+.
|
1312
1318
|
#
|
1313
1319
|
# NOTE: can only be done if the name is not already set.
|
@@ -1851,16 +1857,18 @@ module HDLRuby::High
|
|
1851
1857
|
# NOTE: a function is a short-cut for a method that creates a scope.
|
1852
1858
|
def function(name, &ruby_block)
|
1853
1859
|
if HDLRuby::High.in_system? then
|
1854
|
-
define_singleton_method(name.to_sym) do |*args|
|
1860
|
+
define_singleton_method(name.to_sym) do |*args,&other_block|
|
1855
1861
|
sub do
|
1856
|
-
HDLRuby::High.top_user.instance_exec(*args
|
1862
|
+
HDLRuby::High.top_user.instance_exec(*args,*other_block,
|
1863
|
+
&ruby_block)
|
1857
1864
|
# ruby_block.call(*args)
|
1858
1865
|
end
|
1859
1866
|
end
|
1860
1867
|
else
|
1861
|
-
define_method(name.to_sym) do |*args|
|
1868
|
+
define_method(name.to_sym) do |*args,&other_block|
|
1862
1869
|
sub do
|
1863
|
-
HDLRuby::High.top_user.instance_exec(*args
|
1870
|
+
HDLRuby::High.top_user.instance_exec(*args,*other_block,
|
1871
|
+
&ruby_block)
|
1864
1872
|
end
|
1865
1873
|
end
|
1866
1874
|
end
|
data/lib/HDLRuby/hruby_low.rb
CHANGED
@@ -1385,7 +1385,8 @@ module HDLRuby::Low
|
|
1385
1385
|
# NOTE: type definition are actually type with a name refering to another
|
1386
1386
|
# type (and equivalent to it).
|
1387
1387
|
class TypeDef < Type
|
1388
|
-
|
1388
|
+
# Moved to constructor
|
1389
|
+
# extend Forwardable
|
1389
1390
|
|
1390
1391
|
# The definition of the type.
|
1391
1392
|
attr_reader :def
|
@@ -1402,6 +1403,19 @@ module HDLRuby::Low
|
|
1402
1403
|
end
|
1403
1404
|
# Set the referened type.
|
1404
1405
|
@def = type
|
1406
|
+
|
1407
|
+
# Sets the delegations
|
1408
|
+
self.extend Forwardable
|
1409
|
+
[ :signed?, :unsigned?, :fixed?, :float?, :leaf?,
|
1410
|
+
:width, :range?, :range, :base?, :base, :types?,
|
1411
|
+
:get_all_types, :get_type, :each, :each_type,
|
1412
|
+
:regular?,
|
1413
|
+
:each_name,
|
1414
|
+
:equivalent? ].each do |meth|
|
1415
|
+
if @def.respond_to?(meth)
|
1416
|
+
self.def_delegator :@def, meth
|
1417
|
+
end
|
1418
|
+
end
|
1405
1419
|
end
|
1406
1420
|
|
1407
1421
|
# Comparison for hash: structural comparison.
|
@@ -1429,14 +1443,15 @@ module HDLRuby::Low
|
|
1429
1443
|
@def.each_type_deep(&ruby_block)
|
1430
1444
|
end
|
1431
1445
|
|
1432
|
-
#
|
1433
|
-
|
1434
|
-
|
1435
|
-
|
1436
|
-
|
1437
|
-
|
1438
|
-
|
1439
|
-
|
1446
|
+
# Moved to constructor
|
1447
|
+
# # Delegate the type methods to the ref.
|
1448
|
+
# def_delegators :@def,
|
1449
|
+
# :signed?, :unsigned?, :fixed?, :float?, :leaf?,
|
1450
|
+
# :width, :range?, :range, :base?, :base, :types?,
|
1451
|
+
# :get_all_types, :get_type, :each, :each_type,
|
1452
|
+
# :regular?,
|
1453
|
+
# :each_name,
|
1454
|
+
# :equivalent?
|
1440
1455
|
end
|
1441
1456
|
|
1442
1457
|
|
@@ -3059,24 +3074,6 @@ module HDLRuby::Low
|
|
3059
3074
|
return [@value,@whens,@default].hash
|
3060
3075
|
end
|
3061
3076
|
|
3062
|
-
# # Adds a possible +match+ for the case's value that lead to the
|
3063
|
-
# # execution of +statement+.
|
3064
|
-
# def add_when(match,statement)
|
3065
|
-
# # Checks the match.
|
3066
|
-
# unless match.is_a?(Expression)
|
3067
|
-
# raise AnyError, "Invalid class for a case match: #{match.class}"
|
3068
|
-
# end
|
3069
|
-
# # Checks statement.
|
3070
|
-
# unless statement.is_a?(Statement)
|
3071
|
-
# raise AnyError, "Invalid class for a statement: #{statement.class}"
|
3072
|
-
# end
|
3073
|
-
# # Add the case.
|
3074
|
-
# @whens << [match,statement]
|
3075
|
-
# # And set their parents.
|
3076
|
-
# match.parent = statement.parent = self
|
3077
|
-
# [match,statement]
|
3078
|
-
# end
|
3079
|
-
|
3080
3077
|
# Adds possible when case +w+.
|
3081
3078
|
def add_when(w)
|
3082
3079
|
# Check +w+.
|
@@ -3178,7 +3175,7 @@ module HDLRuby::Low
|
|
3178
3175
|
# Clones the Case (deeply)
|
3179
3176
|
def clone
|
3180
3177
|
# Clone the default if any.
|
3181
|
-
|
3178
|
+
default = @default ? @default.clone : nil
|
3182
3179
|
# Clone the case.
|
3183
3180
|
return Case.new(@value.clone,default,(@whens.map do |w|
|
3184
3181
|
w.clone
|
data/lib/HDLRuby/hruby_low2c.rb
CHANGED
@@ -546,9 +546,10 @@ module HDLRuby::Low
|
|
546
546
|
#
|
547
547
|
# NOTE: type tuples are converted to bit vector of their contents.
|
548
548
|
def to_c(level = 0)
|
549
|
-
return "get_type_tuple(#{self.each.join(",") do |type|
|
550
|
-
|
551
|
-
end})"
|
549
|
+
# return "get_type_tuple(#{self.each.to_a.join(",") do |type|
|
550
|
+
# type.to_c(level+1)
|
551
|
+
# end})"
|
552
|
+
return self.to_vector.to_c(level)
|
552
553
|
end
|
553
554
|
end
|
554
555
|
|
@@ -1872,7 +1873,8 @@ module HDLRuby::Low
|
|
1872
1873
|
res << "idx = value2integer(#{self.index.to_c(level+2)});\n"
|
1873
1874
|
# Make the access.
|
1874
1875
|
res << (" " * ((level+1)*3))
|
1875
|
-
res << "dst = read_range(ref,idx,idx,#{self.ref.type.base.to_c(level)},dst);\n"
|
1876
|
+
# res << "dst = read_range(ref,idx,idx,#{self.ref.type.base.to_c(level)},dst);\n"
|
1877
|
+
res << "dst = read_range(ref,idx,idx,#{self.type.to_c(level)},dst);\n"
|
1876
1878
|
# Restore the state of the value pool.
|
1877
1879
|
res << (" " * ((level+1)*3))
|
1878
1880
|
res << "set_value_pos(pool_state);\n"
|
@@ -1930,7 +1932,9 @@ module HDLRuby::Low
|
|
1930
1932
|
res << "last = value2integer(#{self.range.last.to_c(level+2)});\n"
|
1931
1933
|
# Make the access.
|
1932
1934
|
res << (" " * ((level+1)*3))
|
1933
|
-
res << "dst = #{command}_range(ref,first,last,#{self.ref.type.base.to_c(level)},dst);\n"
|
1935
|
+
# res << "dst = #{command}_range(ref,first,last,#{self.ref.type.base.to_c(level)},dst);\n"
|
1936
|
+
# puts "will read_range for #{self.ref.name} with width=#{self.ref.type.width} with base width=#{self.ref.type.base.width} with range=#{self.ref.type.range} with range=#{self.range.first.content}..#{self.range.last.content}"
|
1937
|
+
res << "dst = #{command}_range(ref,first,last,#{self.type.base.to_c(level)},dst);\n"
|
1934
1938
|
# Restore the state of the value pool.
|
1935
1939
|
res << (" " * ((level+1)*3))
|
1936
1940
|
res << "set_value_pos(pool_state);\n"
|
@@ -1961,6 +1965,7 @@ module HDLRuby::Low
|
|
1961
1965
|
# Generates the C text for reference as left value to a signal.
|
1962
1966
|
# +level+ is the hierarchical level of the object.
|
1963
1967
|
def to_c_signal(level = 0)
|
1968
|
+
# puts "to_c_signal with self=#{self.name}, resolve=#{self.resolve}"
|
1964
1969
|
return "#{self.resolve.to_c_signal(level+1)}"
|
1965
1970
|
end
|
1966
1971
|
end
|
@@ -345,31 +345,34 @@ module HDLRuby::Low
|
|
345
345
|
res << " " * (level*3)
|
346
346
|
res << "entity #{Low2VHDL.entity_name(self.name)} is\n"
|
347
347
|
# The ports
|
348
|
-
|
349
|
-
|
350
|
-
|
351
|
-
|
352
|
-
|
353
|
-
|
354
|
-
|
355
|
-
|
356
|
-
|
357
|
-
|
358
|
-
|
359
|
-
|
360
|
-
|
361
|
-
|
362
|
-
|
363
|
-
|
364
|
-
|
365
|
-
|
366
|
-
|
348
|
+
if self.each_input.any? || self.each_output.any? ||
|
349
|
+
self.each_inout.any? then
|
350
|
+
res << " " * ((level+1)*3)
|
351
|
+
res << "port (\n"
|
352
|
+
# Inputs
|
353
|
+
self.each_input do |input|
|
354
|
+
res << " " * ((level+2)*3)
|
355
|
+
res << Low2VHDL.vhdl_name(input.name) << ": in "
|
356
|
+
res << input.type.to_vhdl << ";\n"
|
357
|
+
end
|
358
|
+
# Outputs
|
359
|
+
self.each_output do |output|
|
360
|
+
res << " " * ((level+2)*3)
|
361
|
+
res << Low2VHDL.vhdl_name(output.name) << ": out "
|
362
|
+
res << output.type.to_vhdl << ";\n"
|
363
|
+
end
|
364
|
+
# Inouts
|
365
|
+
self.each_inout do |inout|
|
366
|
+
res << " " * ((level+2)*3)
|
367
|
+
res << Low2VHDL.vhdl_name(inout.name) << ": inout "
|
368
|
+
res << inout.type.to_vhdl << ";\n"
|
369
|
+
end
|
370
|
+
# Remove the last ";" for conforming with VHDL syntax.
|
371
|
+
res[-2..-1] = "\n" if res[-2] == ";"
|
372
|
+
res << " " * ((level+1)*3)
|
373
|
+
# Close the port declaration.
|
374
|
+
res << ");\n"
|
367
375
|
end
|
368
|
-
# Remove the last ";" for conforming with VHDL syntax.
|
369
|
-
res[-2..-1] = "\n" if res[-2] == ";"
|
370
|
-
res << " " * ((level+1)*3)
|
371
|
-
# Close the port declaration.
|
372
|
-
res << ");\n"
|
373
376
|
# Close the entity
|
374
377
|
res << " " * (level*3)
|
375
378
|
res << "end #{Low2VHDL.entity_name(self.name)};\n\n"
|
@@ -617,7 +620,17 @@ module HDLRuby::Low
|
|
617
620
|
# # Simply generates the redefined type.
|
618
621
|
# return self.def.to_vhdl(level)
|
619
622
|
# Simply use the name of the type.
|
620
|
-
|
623
|
+
# Is it a composite type?
|
624
|
+
if (self.def.is_a?(TypeStruct) ||
|
625
|
+
(self.def.is_a?(TypeVector) &&
|
626
|
+
(self.def.base.is_a?(TypeVector) ||
|
627
|
+
self.def.base.is_a?(TypeStruct))))
|
628
|
+
# Yes, generate a VHDL type definition.
|
629
|
+
return Low2VHDL.vhdl_name(self.name)
|
630
|
+
else
|
631
|
+
# No, generates the defined type.
|
632
|
+
return self.def.to_vhdl(level)
|
633
|
+
end
|
621
634
|
end
|
622
635
|
end
|
623
636
|
|
@@ -745,29 +758,31 @@ module HDLRuby::Low
|
|
745
758
|
res << Low2VHDL.vhdl_name(self.block.name) << ": "
|
746
759
|
end
|
747
760
|
res << "process "
|
748
|
-
# Generate the senitivity list.
|
749
|
-
|
750
|
-
|
751
|
-
|
752
|
-
|
753
|
-
|
754
|
-
|
755
|
-
|
756
|
-
|
757
|
-
|
758
|
-
|
759
|
-
|
760
|
-
|
761
|
-
|
762
|
-
|
763
|
-
|
764
|
-
|
765
|
-
|
766
|
-
|
767
|
-
|
768
|
-
|
769
|
-
|
770
|
-
|
761
|
+
# Generate the senitivity list if not a timed block.
|
762
|
+
unless self.block.is_a?(TimeBlock) then
|
763
|
+
if self.each_event.any? then
|
764
|
+
# If there is a clock.
|
765
|
+
res << "("
|
766
|
+
res << self.each_event.map do |event|
|
767
|
+
event.ref.to_vhdl(level)
|
768
|
+
end.join(", ")
|
769
|
+
res << ")"
|
770
|
+
else
|
771
|
+
# If no clock, generate the sensitivity list from the right
|
772
|
+
# values.
|
773
|
+
list = self.block.each_node_deep.select do |node|
|
774
|
+
node.is_a?(RefName) && !node.leftvalue? &&
|
775
|
+
!node.parent.is_a?(RefName) &&
|
776
|
+
# Also skip the variables
|
777
|
+
!vars.find {|var| var.name == node.name }
|
778
|
+
end.to_a
|
779
|
+
# Keep only one ref per signal.
|
780
|
+
list.uniq! { |node| node.name }
|
781
|
+
# Generate the sensitivity list from it.
|
782
|
+
res << "("
|
783
|
+
res << list.map {|node| node.to_vhdl(level) }.join(", ")
|
784
|
+
res << ")"
|
785
|
+
end
|
771
786
|
end
|
772
787
|
res << "\n"
|
773
788
|
# Generate the variables.
|
@@ -294,6 +294,8 @@ module HDLRuby::Low
|
|
294
294
|
# Is there a type to match?
|
295
295
|
if type then
|
296
296
|
# Yes, update the concat to the type.
|
297
|
+
# Get the real type in case of typedef.
|
298
|
+
type = type.def while type.is_a?(TypeDef)
|
297
299
|
# Is it an array type?
|
298
300
|
if type.is_a?(TypeVector) then
|
299
301
|
# Yes, update the concat without subcasting.
|
@@ -302,14 +304,16 @@ module HDLRuby::Low
|
|
302
304
|
end)
|
303
305
|
else
|
304
306
|
# No, it should be a tuple.
|
305
|
-
return Concat.new(type,
|
307
|
+
return Concat.new(type,
|
308
|
+
self.each_expression.map.with_index do
|
306
309
|
|expr,i|
|
307
310
|
expr.explicit_types(type.get_type(i))
|
308
311
|
end)
|
309
312
|
end
|
310
313
|
else
|
311
314
|
# No, recurse on the sub expressions.
|
312
|
-
return Concat.new(self.type,
|
315
|
+
return Concat.new(self.type,
|
316
|
+
self.each_expression.map do |expr|
|
313
317
|
expr.explicit_types
|
314
318
|
end)
|
315
319
|
end
|
@@ -1069,7 +1069,8 @@ module HDLRuby::Low
|
|
1069
1069
|
node2rep = node2reassign.map {|n,r| [n,r[0]] }.to_h
|
1070
1070
|
|
1071
1071
|
# First recurse on the sub blocks.
|
1072
|
-
self.each_block { |block| block.reassign_expressions!(node2rep) }
|
1072
|
+
# self.each_block { |block| block.reassign_expressions!(node2rep) }
|
1073
|
+
self.each_block { |block| block.reassign_expressions!(node2reassign) }
|
1073
1074
|
|
1074
1075
|
# Now work on the block.
|
1075
1076
|
# Replace on the statements.
|