HDLRuby 2.2.14 → 2.3.1

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data/README.md

@@ -1301,14 +1301,7 @@ __The vector operator__ `[]` is used for building types representing vectors of
 <type>[<range>]
 ```
 
-The `<range>` of a vector type indicates the position of the starting and ending bits relatively to the radix point. If the position of the starting bit
-is on the left side of the range, the vector is big endian, otherwise it is little endian.  Negative values in a range are also possible and indicate positions bellow the radix point.  For example, the following code describes a big-endian fixed-point type with 8 bits above the radix point and 4 bits
-bellow:
-
-```ruby
-bit[7..-4]
-```
-
+The `<range>` of a vector type indicates the position of the starting and ending bits.
 A `n..0` range can also be abbreviated to `n+1`. For instance, the two following types are identical:
 
 ```ruby
@@ -2801,6 +2794,19 @@ bit[4,4].inner :sig
 
 When performing computation with fixed point types, HDLRuby ensures that the result's decimal point position is correct.
 
+In addition to the fixed point data type, a method is added to the literal objects (Numeric) to convert them to fixed point representation:
+
+```ruby
+<litteral>.to_fix(<number of bits after the decimal point>)
+```
+
+For example the following code converts a floating point value to a fixed point value with 16 bits after the decimal point:
+
+```
+3.178.to_fix(16)
+```
+
+
 ## Channel
 <a name="channel"></a>
 

data/lib/HDLRuby/hdr_samples/linear_test.rb

@@ -0,0 +1,235 @@
+require 'std/memory.rb'
+require 'std/linear.rb'
+
+include HDLRuby::High::Std
+
+# Tries for matrix-vector product.
+
+
+
+
+
+# Sample code for testing the linear library.
+
+system :linear_test do
+
+    # Clock and reset.
+    inner :clk,:rst
+
+    # Request and acknoledge signals.
+    inner :req
+    [8].inner :ack
+
+
+    # Circuit for testing the scaling.
+
+    # Input memory
+    mem_file([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_scale_in)
+    # Output memory
+    mem_file([8],8,clk,rst, winc: :rst).(:mem_scale_out)
+    # Access ports.
+    mem_scale_in.branch(:anum).inner :mem_scale_inP
+    mem_scale_inPs = 8.times.map { |i| mem_scale_inP.wrap(i) }
+    mem_scale_out.branch(:anum).inner :mem_scale_outP
+    mem_scale_outPs = 8.times.map { |i| mem_scale_outP.wrap(i) }
+
+    # Build the scaler.
+    scale([8],clk.posedge,req,ack[0],channel_port(3),
+          mem_scale_inPs,mem_scale_outPs)
+
+
+    # Circuit for testing the parallel addition.
+
+    # Input memories
+    mem_file([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_addn_left_in)
+    mem_file([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_addn_right_in)
+    # Output memory
+    mem_file([8],8,clk,rst, winc: :rst).(:mem_addn_out)
+    # Access ports.
+    mem_addn_left_in.branch(:anum).inner :mem_addn_left_inP
+    mem_addn_left_inPs = 8.times.map { |i| mem_addn_left_inP.wrap(i) }
+    mem_addn_right_in.branch(:anum).inner :mem_addn_right_inP
+    mem_addn_right_inPs = 8.times.map { |i| mem_addn_right_inP.wrap(i) }
+    mem_addn_out.branch(:anum).inner :mem_addn_outP
+    mem_addn_outPs = 8.times.map { |i| mem_addn_outP.wrap(i) }
+
+    # Build the adder.
+    add_n([8],clk.posedge,ack[0],ack[1],mem_addn_left_inPs,
+          mem_addn_right_inPs,mem_addn_outPs)
+
+
+    # Circuit for testing the parallel multiplication.
+
+    # Input memories
+    mem_file([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_muln_left_in)
+    mem_file([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_muln_right_in)
+    # Output memory
+    mem_file([8],8,clk,rst, winc: :rst).(:mem_muln_out)
+    # Access ports.
+    mem_muln_left_in.branch(:anum).inner :mem_muln_left_inP
+    mem_muln_left_inPs = 8.times.map { |i| mem_muln_left_inP.wrap(i) }
+    mem_muln_right_in.branch(:anum).inner :mem_muln_right_inP
+    mem_muln_right_inPs = 8.times.map { |i| mem_muln_right_inP.wrap(i) }
+    mem_muln_out.branch(:anum).inner :mem_muln_outP
+    mem_muln_outPs = 8.times.map { |i| mem_muln_outP.wrap(i) }
+
+    # Build the multer.
+    mul_n([8],clk.posedge,ack[1],ack[2],mem_muln_left_inPs,
+          mem_muln_right_inPs,mem_muln_outPs)
+
+
+    # Circuit for testing the mac
+    # Output signal.
+    [8].inner :acc
+
+    # Build the mac.
+    mac([8],clk.posedge,ack[2],ack[3],channel_port(5), channel_port(6), 
+        channel_port(acc))
+
+
+    # Circuit for testing the parallel mac.
+    # Input memory
+    mem_file([8],8,clk,rst, winc: :rst).(:mem_macn1_left_in)
+    # Output memory
+    mem_file([8],8,clk,rst, winc: :rst).(:mem_macn1_out)
+    # Access ports.
+    mem_macn1_left_in.branch(:anum).inner :mem_macn1_left_inP
+    mem_macn1_left_inPs = 8.times.map { |i| mem_macn1_left_inP.wrap(i) }
+    mem_macn1_out.branch(:anum).inner :mem_macn1_outP
+    mem_macn1_outPs = 8.times.map { |i| mem_macn1_outP.wrap(i) }
+
+    # Build the mac.
+    mac_n1([8],clk.posedge,ack[3],ack[4], mem_macn1_left_inPs,
+          channel_port(5), mem_macn1_outPs)
+
+    # Circuit for testing the linearun with mac.
+    # Input memories
+    mem_dual([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_macrn_left_in)
+    mem_dual([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_macrn_right_in)
+    # Access ports.
+    mem_macrn_left_in.branch(:rinc).inner :mem_macrn_left_in_readP
+    mem_macrn_right_in.branch(:rinc).inner :mem_macrn_right_in_readP
+    # Output signal.
+    [8].inner :accr
+
+    # Build the linearun mac.
+    linearun(8,clk.posedge,ack[4],ack[5]) do |ev,req,ack|
+        mac([8],ev,req,ack,mem_macrn_left_in_readP,mem_macrn_right_in_readP, 
+            channel_port(accr))
+    end
+
+
+    # The memory initializer.
+    # Writing ports
+    mem_scale_in.branch(:winc).inner :mem_scale_in_writeP
+    mem_addn_left_in.branch(:winc).inner :mem_addn_left_in_writeP
+    mem_addn_right_in.branch(:winc).inner :mem_addn_right_in_writeP
+    mem_muln_left_in.branch(:winc).inner :mem_muln_left_in_writeP
+    mem_muln_right_in.branch(:winc).inner :mem_muln_right_in_writeP
+    mem_macn1_left_in.branch(:winc).inner :mem_macn1_left_in_writeP
+    mem_macrn_left_in.branch(:winc).inner :mem_macrn_left_in_writeP
+    mem_macrn_right_in.branch(:winc).inner :mem_macrn_right_in_writeP
+    # Filling index
+    [8].inner :idx
+    # Filling counter
+    [3].inner :cnt
+    # Filling value
+    [8].inner :val
+
+    # Start flag
+    inner :start
+
+    # The execution process
+    par(clk.posedge) do
+        hif(rst) { cnt <= 0; val <= 0 }
+        helse do
+            # Step index processing.
+            hif(cnt == 7) do
+                hif(idx < 8) { idx <= idx + 1 }
+            end
+            # Memory filling steps.
+            hcase(idx)
+            hwhen(0) do
+                mem_scale_in_writeP.write(val) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            hwhen(1) do
+                mem_addn_left_in_writeP.write(val) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            hwhen(2) do
+                mem_addn_right_in_writeP.write(val) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            hwhen(3) do
+                mem_muln_left_in_writeP.write(val-24) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            hwhen(4) do
+                mem_muln_right_in_writeP.write(val-24) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            hwhen(5) do
+                mem_macn1_left_in_writeP.write(val-32) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            hwhen(6) do
+                mem_macrn_left_in_writeP.write(val-48) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            hwhen(7) do
+                mem_macrn_right_in_writeP.write(val-48) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            # Computation steps.
+            helse do
+                hif(start) do
+                    req <= 1
+                    start <= 0
+                end
+                helse { req <= 0 }
+            end
+        end
+    end
+
+
+    # The test bench.
+    timed do
+        req <= 0
+        ack <= 0
+        clk <= 0
+        rst <= 0
+        cnt <= 0
+        idx <= 0
+        val <= 0
+        start <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        # Reset
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        start <= 1
+        !10.ns
+        # Run
+        128.times do
+            clk <= 1
+            !10.ns
+            clk <= 0
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/rom.rb

@@ -4,8 +4,8 @@ system :rom4_8 do
     [2..0].input :addr
     [7..0].output :data0,:data1,:data2
 
-    bit[7..0][0..7].constant content0: [1,2,3,4,5,6,7]
-    bit[7..0][-8].constant content1: [1,2,3,4,5,6,7]
+    bit[7..0][0..7].constant content0: [0,1,2,3,4,5,6,7]
+    bit[7..0][-8].constant content1: [0,1,2,3,4,5,6,7]
     bit[7..0][-8].constant content2: (8).times.to_a
 
     data0 <= content0[addr]

data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb

@@ -0,0 +1,96 @@
+require 'std/memory.rb'
+require 'std/linear.rb'
+# require 'std/timing.rb'
+
+include HDLRuby::High::Std
+
+
+system :fir do |typ,iChannel,oChannel,coefs|
+    input :clk, :rst, :req
+    output :ack
+    # Declare the input port.
+    iChannel.input :iPort
+    # Declare the output port.
+    oChannel.output :oPort
+
+    # Declares the data registers.
+    datas = coefs.map.with_index do |coef,id|
+        coef.type.inner :"data_#{id}"
+    end
+
+    inner :req2
+    
+
+    # Generate the mac pipeline.
+    mac_np(typ,clk.posedge,req2,ack, 
+          datas.map{|data| channel_port(data) },
+          coefs.map{|coef| channel_port(coef) }, oPort)
+
+    # Generate the data transfer through the pipeline.
+    par(clk.posedge) do
+        req2 <= 0
+        hif(rst) { datas.each { |d| d <= 0 } }
+        hif(req) do
+            iPort.read(datas[0]) do
+                # datas.each_cons(2) { |d0,d1| d1 <= d0 }
+                datas[1..-1] <= datas[0..-2]
+            end
+            req2 <= 1
+        end
+    end
+end
+
+
+
+
+
+system :work do
+
+    inner :clk,:rst,:req,:ack
+
+    # The input memory.
+    mem_rom([8],8,clk,rst,
+            [_00000001,_00000010,_00000011,_00000100,
+             _00000101,_00000110,_00000111,_00001000]).(:iMem)
+    # The output memory.
+    mem_dual([8],8,clk,rst).(:oMem)
+    # The coefficients.
+    coefs = [_11001100,_00110011,_10101010,_01010101,
+             _11110000,_00001111,_11100011,_00011100]
+
+    # The filter
+    fir([8],iMem.branch(:rinc),oMem.branch(:winc),coefs).(:my_fir).(clk,rst,req,ack)
+
+    # iMem.branch(:rinc).inner :port
+    # [8].inner :a
+    # par(clk.posedge) do
+    #     hif(req) { port.read(a) }
+    # end
+
+    timed do
+        req <= 0
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        req <= 1
+        clk <= 0
+        64.times do
+            !10.ns
+            clk <= 1
+            !10.ns
+            clk <= 0
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_fixpoint.rb

@@ -12,8 +12,9 @@ system :fix_test do
 
     # Performs calculation between then
     timed do
-        x <= _00110011
-        y <= _01000000
+        # x <= _00110011 # 3.1875
+        x <= 3.1875.to_fix(4)
+        y <= _01000000 # 4
         !10.ns
         z <= x + y
         !10.ns

data/lib/HDLRuby/hdr_samples/with_linear.rb

@@ -0,0 +1,166 @@
+require 'std/memory.rb'
+require 'std/linear.rb'
+
+include HDLRuby::High::Std
+
+# Tries for matrix-vector product.
+
+
+
+
+
+# Testing.
+system :testmat do
+
+    inner :clk,:rst, :req
+
+    # Input memories
+    # mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memL0)
+    # The first memory is 4-bank for testing purpose.
+    mem_bank([8],4,256/4,clk,rst, rinc: :rst,winc: :rst).(:memL0)
+    # The others are standard dual-edge memories.
+    mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memL1)
+    mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memR)
+    # Access ports.
+    memL0.branch(:rinc).inner :readL0
+    memL1.branch(:rinc).inner :readL1
+    memR.branch(:rinc).inner :readR
+
+    # Prepares the left and acc arrays.
+    lefts = [readL0, readL1]
+
+    # Accumulators memory.
+    mem_file([8],2,clk,rst,rinc: :rst).(:memAcc)
+    memAcc.branch(:anum).inner :accs
+    accs_out = [accs.wrap(0), accs.wrap(1)]
+
+    # Layer 0 ack.
+    inner :ack0
+    
+    # Instantiate the matrix product.
+    mac_n1([8],clk,req,ack0,lefts,readR,accs_out)
+
+    # Translation.
+    # Translation memory.
+    mem_file([8],2,clk,rst,winc: :rst).(:memT)
+    # Tarnslation result
+    mem_file([8],2,clk,rst,rinc: :rst).(:memF)
+    # Access ports.
+    memT.branch(:anum).inner :readT
+    memF.branch(:anum).inner :writeF
+    regRs = [ readT.wrap(0), readT.wrap(1) ]
+    regLs = [ accs.wrap(0), accs.wrap(1) ]
+    regs =  [ writeF.wrap(0), writeF.wrap(1) ]
+
+    # Translater ack.
+    inner :ackT
+
+    # Instantiate the translater.
+    add_n([8],clk,ack0,ackT,regLs,regRs,regs)
+
+
+
+    # Second layer.
+    # Input memories.
+    mem_dual([8],2,clk,rst, rinc: :rst,winc: :rst).(:mem2L0)
+    # Access ports.
+    mem2L0.branch(:rinc).inner :read2L0
+    # memAcc.branch(:rinc).inner :accsR
+    memF.branch(:rinc).inner :readF
+
+    # Second layer ack.
+    inner :ack1
+
+    # Result.
+    [8].inner :res
+
+    sub do
+        # Instantiate the second matrix product.
+        # mac([8],clk,req,read2L0,accsR,res)
+        mac([8],clk,ackT,ack1,read2L0,readF,channel_port(res))
+    end
+
+
+
+    # The memory initializer.
+    memL0.branch(:winc).inner :writeL0
+    memL1.branch(:winc).inner :writeL1
+    memR.branch(:winc).inner :writeR
+    memT.branch(:winc).inner :writeT
+    mem2L0.branch(:winc).inner :write2L0
+    inner :fill, :fill2
+    [8].inner :val
+    par(clk.posedge) do
+        hif(fill) do
+            writeL0.write(val)
+            writeL1.write(val+1)
+            writeR.write(val+1)
+        end
+        hif(fill2) do
+            write2L0.write(val+2)
+            writeT.write(val+2)
+        end
+    end
+
+    timed do
+        req <= 0
+        clk <= 0
+        rst <= 0
+        fill <= 0
+        fill2 <= 0
+        val  <= 0
+        !10.ns
+        # Reset the memories.
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        # Fill the memories.
+        # First layer
+        clk <= 0
+        rst <= 0
+        fill <= 1
+        !10.ns
+        256.times do |i|
+            clk <= 1
+            !10.ns
+            clk <= 0
+            val <= val + 1
+            !10.ns
+        end
+        fill <= 0
+        clk <= 1
+        !10.ns
+        # Second layer
+        clk <= 0
+        rst <= 0
+        fill2 <= 1
+        !10.ns
+        2.times do |i|
+            clk <= 1
+            !10.ns
+            clk <= 0
+            val <= val + 1
+            !10.ns
+        end
+        fill2 <= 0
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        # Launch the computation
+        clk <= 0
+        req <= 1
+        !10.ns
+        300.times do
+            clk <= 1
+            !10.ns
+            clk <= 0
+            !10.ns
+        end
+    end
+end