HDLRuby 2.11.4 → 2.11.7

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@@ -11,6 +11,35 @@ module HDLRuby::High
11
11
  return name.to_s.gsub(/[^a-zA-Z0-9_$]/,"$")
12
12
  end
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13
 
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+ ## Converts a bit string to a vcd format.
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+ def self.vcd_bitstr(str)
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+ if str.length > 1 then
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+ return "b" + str + " "
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+ else
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+ return str
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+ end
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+ end
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+
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+ ## Converts a HDLRuby object to a VCD id string.
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+ @@rsim_object_idstr = { }
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+ @@rsim_object_idstr_count = 0
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+ def self.vcd_idstr(obj)
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+ idstr = @@rsim_object_idstr[obj]
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+ unless idstr then
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+ # Must generate a new id string.
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+ chars = []
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+ id = @@rsim_object_idstr_count
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+ @@rsim_object_idstr_count += 1
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+ loop do
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+ chars << ((id % (127-33)) + 33).chr
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+ break if ((id=id/(127-33)) == 0)
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+ end
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+ idstr = chars.join
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+ @@rsim_object_idstr[obj] = idstr
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+ end
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+ return idstr
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+ end
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+
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  ##
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  # Enhance the system type class with VCD support.
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  class SystemT
@@ -40,14 +69,24 @@ module HDLRuby::High
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  # Closes the header.
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  @vcdout << "$enddefinitions $end\n"
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  # Initializes the variables with their name.
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- @vars_with_fullname = self.get_vars_with_fullname
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+ # @vars_with_fullname = self.get_vars_with_fullname
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+ @vars_with_idstr = self.get_vars_with_idstr
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  @vcdout << "$dumpvars\n"
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- @vars_with_fullname.each_pair do |sig,fullname|
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+ # @vars_with_fullname.each_pair do |sig,fullname|
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+ # if sig.f_value then
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+ # @vcdout << " b#{sig.f_value.to_vstr} #{fullname}\n"
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+ # else
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+ # @vcdout << " b#{"x"} #{fullname}\n"
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+ # end
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+ # end
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+ @vars_with_idstr.each_pair do |sig,idstr|
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  if sig.f_value then
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- @vcdout << " b#{sig.f_value.to_vstr} #{fullname}\n"
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+ # @vcdout << " b#{sig.f_value.to_vstr} #{idstr}\n"
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+ @vcdout << HDLRuby::High.vcd_bitstr(sig.f_value.to_vstr) <<
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+ idstr << "\n"
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  else
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- # @vcdout << " b#{"x"*sig.type.width} #{fullname}\n"
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- @vcdout << " b#{"x"} #{fullname}\n"
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+ # @vcdout << " b#{"x"} #{idstr}\n"
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+ @vcdout << HDLRuby::High.vcd_bitstr("x") << idstr << "\n"
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  end
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  end
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  @vcdout << "$end\n"
@@ -63,6 +102,16 @@ module HDLRuby::High
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  return self.scope.get_vars_with_fullname(vars_with_fullname)
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  end
65
104
 
105
+ ## Gets the VCD variables with their id string.
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+ def get_vars_with_idstr(vars_with_idstr = {})
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+ # Adds the signals of the interface of the system.
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+ self.each_signal do |sig|
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+ vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
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+ end
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+ # Recurse on the scope.
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+ return self.scope.get_vars_with_idstr(vars_with_idstr)
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+ end
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+
66
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  ## Shows the hierarchy of the variables.
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  def show_hierarchy(vcdout)
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  # puts "show_hierarchy for module #{self} (#{self.name})"
@@ -72,7 +121,8 @@ module HDLRuby::High
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  self.each_signal do |sig|
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  # puts "showing signal #{HDLRuby::High.vcd_name(sig.fullname)}"
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  vcdout << "$var wire #{sig.type.width} "
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- vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
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+ # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
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+ vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
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  vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
77
127
  end
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  # Recurse on the scope.
@@ -88,8 +138,9 @@ module HDLRuby::High
88
138
 
89
139
  ## Displays the value of signal +sig+.
90
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  def show_signal(sig)
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- @vcdout << "b#{sig.f_value.to_vstr} "
92
- @vcdout << "#{@vars_with_fullname[sig]}\n"
141
+ # @vcdout << "b#{sig.f_value.to_vstr} "
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+ @vcdout << HDLRuby::High.vcd_bitstr(sig.f_value.to_vstr)
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+ @vcdout << "#{@vars_with_idstr[sig]}\n"
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  end
94
145
 
95
146
  ## Displays value +val+.
@@ -121,7 +172,8 @@ module HDLRuby::High
121
172
  self.each_inner do |sig|
122
173
  # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
123
174
  vcdout << "$var wire #{sig.type.width} "
124
- vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
175
+ # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
176
+ vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
125
177
  vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
126
178
  end
127
179
  # Recurse on the behaviors' blocks
@@ -162,6 +214,27 @@ module HDLRuby::High
162
214
  end
163
215
  return vars_with_fullname
164
216
  end
217
+
218
+ ## Gets the VCD variables with their id string.
219
+ def get_vars_with_idstr(vars_with_idstr = {})
220
+ # Adds the inner signals.
221
+ self.each_inner do |sig|
222
+ vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
223
+ end
224
+ # Recurse on the behaviors' blocks
225
+ self.each_behavior do |beh|
226
+ beh.block.get_vars_with_idstr(vars_with_idstr)
227
+ end
228
+ # Recurse on the systemI's Eigen system.
229
+ self.each_systemI do |sys|
230
+ sys.systemT.get_vars_with_idstr(vars_with_idstr)
231
+ end
232
+ # Recurse on the subscopes.
233
+ self.each_scope do |scope|
234
+ scope.get_vars_with_idstr(vars_with_idstr)
235
+ end
236
+ return vars_with_idstr
237
+ end
165
238
  end
166
239
 
167
240
 
@@ -177,6 +250,11 @@ module HDLRuby::High
177
250
  def get_vars_with_fullname(vars_with_fullname = {})
178
251
  # By default: nothing to do
179
252
  end
253
+
254
+ ## Gets the VCD variables with their id string.
255
+ def get_vars_with_idstr(vars_with_idstr = {})
256
+ # By default: nothing to do
257
+ end
180
258
  end
181
259
 
182
260
  ##
@@ -192,6 +270,11 @@ module HDLRuby::High
192
270
  def get_vars_with_fullname(vars_with_fullname = {})
193
271
  # By default: nothing to do
194
272
  end
273
+
274
+ ## Gets the VCD variables with their idstr.
275
+ def get_vars_with_idstr(vars_with_idstr = {})
276
+ # By default: nothing to do
277
+ end
195
278
  end
196
279
 
197
280
  ##
@@ -206,6 +289,11 @@ module HDLRuby::High
206
289
  def get_vars_with_fullname(vars_with_fullname = {})
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290
  # By default: nothing to do
208
291
  end
292
+
293
+ ## Gets the VCD variables with their id string.
294
+ def get_vars_with_idstr(vars_with_idstr = {})
295
+ # By default: nothing to do
296
+ end
209
297
  end
210
298
 
211
299
  ##
@@ -220,6 +308,11 @@ module HDLRuby::High
220
308
  def get_vars_with_fullname(vars_with_fullname = {})
221
309
  # By default: nothing to do
222
310
  end
311
+
312
+ ## Gets the VCD variables with their id string.
313
+ def get_vars_with_idstr(vars_with_idstr = {})
314
+ # By default: nothing to do
315
+ end
223
316
  end
224
317
 
225
318
 
@@ -238,7 +331,8 @@ module HDLRuby::High
238
331
  self.each_inner do |sig|
239
332
  # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
240
333
  vcdout << "$var wire #{sig.type.width} "
241
- vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
334
+ # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
335
+ vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
242
336
  vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
243
337
  end
244
338
  # Recurse on the statements
@@ -263,6 +357,19 @@ module HDLRuby::High
263
357
  end
264
358
  return vars_with_fullname
265
359
  end
360
+
361
+ ## Gets the VCD variables with their id string.
362
+ def get_vars_with_idstr(vars_with_idstr = {})
363
+ # Adds the inner signals.
364
+ self.each_inner do |sig|
365
+ vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
366
+ end
367
+ # Recurse on the statements.
368
+ self.each_statement do |stmnt|
369
+ stmnt.get_vars_with_idstr(vars_with_idstr)
370
+ end
371
+ return vars_with_idstr
372
+ end
266
373
  end
267
374
 
268
375
 
@@ -307,6 +414,19 @@ module HDLRuby::High
307
414
  self.no.get_vars_with_fullname(vars_with_fullname) if self.no
308
415
  return vars_with_fullname
309
416
  end
417
+
418
+ ## Gets the VCD variables with their id string.
419
+ def get_vars_with_idstr(vars_with_idstr = {})
420
+ # Recurse on the yes.
421
+ self.yes.get_vars_with_idstr(vars_with_idstr)
422
+ # Recurse on the noifs.
423
+ self.each_noif do |cond,stmnt|
424
+ stmnt.get_vars_with_idstr(vars_with_idstr)
425
+ end
426
+ # Recure on the no if any.
427
+ self.no.get_vars_with_idstr(vars_with_idstr) if self.no
428
+ return vars_with_idstr
429
+ end
310
430
  end
311
431
 
312
432
 
@@ -320,7 +440,7 @@ module HDLRuby::High
320
440
  w.statement.show_hierarchy(vcdout)
321
441
  end
322
442
  # Recurse on the default if any.
323
- self.default.show_hierarchy(vcdout)
443
+ self.default.show_hierarchy(vcdout) if self.default
324
444
  end
325
445
 
326
446
  ## Gets the VCD variables with their long name.
@@ -330,8 +450,44 @@ module HDLRuby::High
330
450
  w.statement.get_vars_with_fullname(vars_with_fullname)
331
451
  end
332
452
  # Recurse on the default if any.
333
- self.default.get_vars_with_fullname(vars_with_fullname)
453
+ self.default.get_vars_with_fullname(vars_with_fullname) if self.default
454
+ return vars_with_fullname
455
+ end
456
+
457
+ ## Gets the VCD variables with their id string.
458
+ def get_vars_with_idstr(vars_with_idstr = {})
459
+ # Recurse on each when.
460
+ self.each_when do |w|
461
+ w.statement.get_vars_with_idstr(vars_with_idstr)
462
+ end
463
+ # Recurse on the default if any.
464
+ self.default.get_vars_with_idstr(vars_with_idstr) if self.default
465
+ return vars_with_idstr
466
+ end
467
+ end
468
+
469
+ ##
470
+ # Enhance the TimeRepeat class with VCD support.
471
+ class TimeRepeat
472
+ ## Shows the hierarchy of the variables.
473
+ def show_hierarchy(vcdout)
474
+ # Recurse on the statement.
475
+ self.statement.show_hierarchy(vcdout)
476
+ end
477
+
478
+ ## Gets the VCD variables with their long name.
479
+ def get_vars_with_fullname(vars_with_fullname = {})
480
+ # Recurse on the statement.
481
+ self.statement.get_vars_with_fullname(vars_with_fullname)
334
482
  return vars_with_fullname
335
483
  end
484
+
485
+ ## Gets the VCD variables with their id string.
486
+ def get_vars_with_idstr(vars_with_idstr = {})
487
+ # Recurse on the statement.
488
+ self.statement.get_vars_with_idstr(vars_with_idstr)
489
+ return vars_with_idstr
490
+ end
336
491
  end
492
+
337
493
  end
@@ -34,7 +34,6 @@ module HDLRuby
34
34
  :==, :!=, :<, :>, :<=, :>=, :<=> ].
35
35
  each do |op|
36
36
  define_method(op) do |val|
37
- # puts "op=#{op} value=#{value}"
38
37
  # Ensures val is computable.
39
38
  unless val.to_value? then
40
39
  # Not computable, use the former method that generates
@@ -45,6 +44,7 @@ module HDLRuby
45
44
  if self.content.is_a?(Numeric) && val.content.is_a?(BitString)
46
45
  if val.content.specified? then
47
46
  res_content = self.content.send(op,val.content.to_i)
47
+ # puts "op=#{op} self.content=#{self.content} val.content=#{val.content.to_i} res_content=#{res_content}"
48
48
  else
49
49
  res_content =
50
50
  BitString.new(self.content).send(op,val.content)
@@ -52,7 +52,7 @@ module HDLRuby
52
52
  else
53
53
  # Generate the resulting content.
54
54
  res_content = self.content.send(op,val.content)
55
- # puts "op=#{op} self.content=#{self.content} (#{self.content.class}) val.content=#{val.content} (#{val.content.class}) res_content=#{res_content} (#{res_content.class})"
55
+ # puts "op=#{op} self.content=#{self.content} (#{self.content.to_i}) val.content=#{val.content} (#{val.content.to_i}) res_content=#{res_content} (#{res_content.class})" if op == :^
56
56
  end
57
57
  res_type = self.type.resolve(val.type)
58
58
  # # Adjust the result content size.
@@ -374,6 +374,23 @@ module HDLRuby
374
374
  return other,self.content
375
375
  end
376
376
 
377
+ # Hash-map comparison of values.
378
+ # Also use in simulation engines to know if a signal changed.
379
+ def eql?(val)
380
+ if self.content.is_a?(Numeric) then
381
+ return self.content == val if val.is_a?(Numeric)
382
+ return self.content == val.content if val.content.is_a?(Numeric)
383
+ return false unless val.content.specified?
384
+ return self.content == val.content.to_i
385
+ else
386
+ return self.content.to_i == val if val.is_a?(Numeric)
387
+ return self.content.eql?(val.content) unless val.content.is_a?(Numeric)
388
+ return false if self.content.specified?
389
+ return self.content.to_i == val.content
390
+ end
391
+ end
392
+
393
+
377
394
  # Tell if the value is zero.
378
395
  def zero?
379
396
  return false unless @content
@@ -1524,7 +1524,14 @@ module HDLRuby::Low
1524
1524
  # Converts the system to Verilog code.
1525
1525
  def to_verilog
1526
1526
  # Outputs the first and second choices (choice (0) and choice (1)).
1527
- return "#{self.select.to_verilog} == 1 #{self.operator} #{self.get_choice(0).to_verilog} : #{self.get_choice(1).to_verilog}"
1527
+ # return "#{self.select.to_verilog} == 1 #{self.operator} #{self.get_choice(0).to_verilog} : #{self.get_choice(1).to_verilog}"
1528
+ res = ""
1529
+ sels = self.select.to_verilog
1530
+ @choices[0..-2].each_with_index do |choice,i|
1531
+ res << "#{sels} == #{i} ? #{choice.to_verilog} : "
1532
+ end
1533
+ res << @choices[-1].to_verilog
1534
+ return res
1528
1535
  end
1529
1536
  end
1530
1537
 
@@ -1534,18 +1541,36 @@ module HDLRuby::Low
1534
1541
  # Converts the system to Verilog code.
1535
1542
  # If it is bit, it is b, and if it is int, it is represented by d. (Example: 4'b0000, 32'd1)
1536
1543
  def to_verilog(unknown = nil)
1537
- if self.type.base.name.to_s == "bit"
1538
- return "#{self.type.range.first + 1}'b#{self.content.to_verilog}"
1539
- elsif self.type.name.to_s == "integer"
1540
- str = self.content.to_verilog
1541
- if str[0] == "-" then
1542
- # Negative value.
1543
- return "-#{self.type.range.first + 1}'d#{str[1..-1]}"
1544
+ # if self.type.base.name.to_s == "bit"
1545
+ # if self.type.unsigned? then
1546
+ # # return "#{self.type.range.first + 1}'b#{self.content.to_verilog}"
1547
+ # return "#{self.type.width}'b#{self.content.to_verilog}"
1548
+ # elsif self.type.name.to_s == "integer"
1549
+ # str = self.content.to_verilog
1550
+ # if str[0] == "-" then
1551
+ # # Negative value.
1552
+ # return "-#{self.type.range.first + 1}'d#{str[1..-1]}"
1553
+ # else
1554
+ # return "#{self.type.range.first + 1}'d#{str}"
1555
+ # end
1556
+ # end
1557
+ # return "#{self.type.range.first + 1}'b#{self.content.to_verilog}"
1558
+ if self.content.is_a?(Numeric) then
1559
+ if self.content < 0 then
1560
+ # str = (2**self.type.width + self.content).to_s(2)
1561
+ str = self.content.to_s(2)
1562
+ str = "0" * (self.type.width-str.length+1) + str[1..-1]
1563
+ return "-#{self.type.width}'b#{str}"
1544
1564
  else
1545
- return "#{self.type.range.first + 1}'d#{str}"
1565
+ str = self.content.to_s(2)
1566
+ str = "0" * (self.type.width-str.length) + str
1567
+ return "#{self.type.width}'b#{str}"
1546
1568
  end
1569
+ # return "#{self.type.width}'b#{str}"
1570
+ else
1571
+ str = self.content.to_verilog
1572
+ return "#{str.length}'b#{str}"
1547
1573
  end
1548
- return "#{self.type.range.first + 1}'b#{self.content.to_verilog}"
1549
1574
  end
1550
1575
  # How to use when simply obtaining the width
1551
1576
  def to_getrange
@@ -1602,7 +1627,6 @@ module HDLRuby::Low
1602
1627
 
1603
1628
  result = " " * spc # Indented based on space_count.
1604
1629
 
1605
- result = ""
1606
1630
  result << "case(#{self.value.to_verilog})\n"
1607
1631
 
1608
1632
  # n the case statement, each branch is partitioned by when. Process each time when.
@@ -1611,18 +1635,19 @@ module HDLRuby::Low
1611
1635
  result << " " * (spc+3) + "#{whens.match.to_verilog}: "
1612
1636
 
1613
1637
  if whens.statement.each_statement.count >= 1 then
1614
- result << whens.statement.to_verilog(spc+3)
1638
+ result << whens.statement.to_verilog(spc+3) << "\n"
1615
1639
  else
1616
- result << "\n"
1640
+ result << ";\n"
1617
1641
  end
1618
1642
  end
1619
1643
  if self.default then
1644
+ result << " " * (spc+3) + "default: "
1620
1645
  if self.default.each_statement.count >= 1 then
1621
1646
  result << self.default.each_statement.map do |stmnt|
1622
1647
  stmnt.to_verilog(spc+3)
1623
- end.join("\n")
1648
+ end.join("\n") << "\n"
1624
1649
  else
1625
- result << "\n"
1650
+ result << ";\n"
1626
1651
  end
1627
1652
  end
1628
1653
  result << " " * spc + "endcase\n" # Conclusion.
@@ -2032,6 +2057,9 @@ module HDLRuby::Low
2032
2057
  # Generate content code.
2033
2058
  codeC = ""
2034
2059
 
2060
+ # Arrays to initialize.
2061
+ arrays_to_init = []
2062
+
2035
2063
  # Declare "inner".
2036
2064
  self.each_inner do |inner|
2037
2065
  if HDLRuby::Low::VERILOG_REGS.include?(inner.to_verilog) then
@@ -2050,8 +2078,14 @@ module HDLRuby::Low
2050
2078
  codeC << " #{inner.type.to_verilog}#{inner.to_verilog}"
2051
2079
  end
2052
2080
  if inner.value then
2053
- # There is an initial value.
2054
- codeC << " = #{inner.value.to_verilog}"
2081
+ val = inner.value
2082
+ val = val.child while val.is_a?(Cast)
2083
+ if val.is_a?(Concat) then
2084
+ arrays_to_init << [inner,val]
2085
+ else
2086
+ # There is an initial value.
2087
+ codeC << " = #{inner.value.to_verilog}"
2088
+ end
2055
2089
  end
2056
2090
  codeC << ";\n"
2057
2091
  end
@@ -2192,6 +2226,22 @@ module HDLRuby::Low
2192
2226
 
2193
2227
  end
2194
2228
 
2229
+ # Generate the code for the initialization of the arrays.
2230
+ if arrays_to_init.any? then
2231
+ codeC << " initial begin\n"
2232
+ arrays_to_init.each do |(sig,val)|
2233
+ val.each_expression.with_index do |expr,i|
2234
+ # Initialization, therefore maybe no cast required...
2235
+ # if sig.value.is_a?(Cast) then
2236
+ # expr = Cast.new(sig.value.type,expr.clone)
2237
+ # end
2238
+ codeC << " ";
2239
+ codeC << "#{sig.to_verilog}[#{i}]=#{expr.to_verilog};\n"
2240
+ end
2241
+ end
2242
+ codeC << " end\n"
2243
+ end
2244
+
2195
2245
  # Conclusion.
2196
2246
  codeC << "\nendmodule"
2197
2247
 
@@ -120,10 +120,10 @@ module HDLRuby::High::Std
120
120
 
121
121
  # Enters the current system
122
122
  HDLRuby::High.cur_system.open do
123
- sub do
123
+ # sub do
124
124
  HDLRuby::High.space_push(namespace)
125
125
  # Execute the instantiation block
126
- return_value =HDLRuby::High.top_user.instance_exec(&ruby_block)
126
+ return_value = HDLRuby::High.top_user.instance_exec(&ruby_block)
127
127
 
128
128
  # Expands the extra state processing so that al all the
129
129
  # parts of the state machine are in par (clear synthesis).
@@ -311,7 +311,7 @@ module HDLRuby::High::Std
311
311
  end
312
312
 
313
313
  HDLRuby::High.space_pop
314
- end
314
+ # end
315
315
  end
316
316
 
317
317
  return return_value
@@ -1,3 +1,3 @@
1
1
  module HDLRuby
2
- VERSION = "2.11.4"
2
+ VERSION = "2.11.7"
3
3
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: HDLRuby
3
3
  version: !ruby/object:Gem::Version
4
- version: 2.11.4
4
+ version: 2.11.7
5
5
  platform: ruby
6
6
  authors:
7
7
  - Lovic Gauthier
8
8
  autorequire:
9
9
  bindir: exe
10
10
  cert_chain: []
11
- date: 2022-10-11 00:00:00.000000000 Z
11
+ date: 2022-11-10 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: bundler
@@ -70,6 +70,7 @@ files:
70
70
  - ext/hruby_sim/hruby_sim_calc.c
71
71
  - ext/hruby_sim/hruby_sim_core.c
72
72
  - ext/hruby_sim/hruby_sim_list.c
73
+ - ext/hruby_sim/hruby_sim_mute.c
73
74
  - ext/hruby_sim/hruby_sim_stack_calc.c
74
75
  - ext/hruby_sim/hruby_sim_stack_calc.c.sav
75
76
  - ext/hruby_sim/hruby_sim_tree_calc.c
@@ -96,11 +97,13 @@ files:
96
97
  - lib/HDLRuby/hdr_samples/addsub.rb
97
98
  - lib/HDLRuby/hdr_samples/addsubz.rb
98
99
  - lib/HDLRuby/hdr_samples/alu.rb
100
+ - lib/HDLRuby/hdr_samples/arith_bench.rb
99
101
  - lib/HDLRuby/hdr_samples/bstr_bench.rb
100
102
  - lib/HDLRuby/hdr_samples/calculator.rb
101
103
  - lib/HDLRuby/hdr_samples/case_bench.rb
102
104
  - lib/HDLRuby/hdr_samples/comparison_bench.rb
103
105
  - lib/HDLRuby/hdr_samples/constant_in_function.rb
106
+ - lib/HDLRuby/hdr_samples/constant_prop_bench.rb
104
107
  - lib/HDLRuby/hdr_samples/counter_bench.rb
105
108
  - lib/HDLRuby/hdr_samples/counter_dff_bench.rb
106
109
  - lib/HDLRuby/hdr_samples/dff.rb
@@ -286,6 +289,7 @@ files:
286
289
  - lib/HDLRuby/hruby_low_without_select.rb
287
290
  - lib/HDLRuby/hruby_rcsim.rb
288
291
  - lib/HDLRuby/hruby_rsim.rb
292
+ - lib/HDLRuby/hruby_rsim_mute.rb
289
293
  - lib/HDLRuby/hruby_rsim_vcd.rb
290
294
  - lib/HDLRuby/hruby_serializer.rb
291
295
  - lib/HDLRuby/hruby_tools.rb