HDLRuby 2.11.4 → 2.11.7

data/lib/HDLRuby/hruby_low_without_connection.rb

@@ -29,7 +29,9 @@ module HDLRuby::Low
                 if scope.each_connection.to_a.any? then
                     inputs_blk = Block.new(:par)
                     outputs_blk = Block.new(:par)
-                    timed_blk = TimeBlock.new(:seq)
+                    # Timed block is not necessary anymore for initialization.
+                    # timed_blk = TimeBlock.new(:seq)
+                    timed_blk = Block.new(:seq)
                     scope.each_connection do |connection|
                         # puts "For connection: #{connection}"
                         # Check the left and right of the connection
@@ -134,7 +136,9 @@ module HDLRuby::Low
                         scope.add_behavior(Behavior.new(outputs_blk))
                     end
                     if timed_blk.each_statement.any? then
-                        scope.add_behavior(TimeBehavior.new(timed_blk))
+                        # No more required to be timed.
+                        # scope.add_behavior(TimeBehavior.new(timed_blk))
+                        scope.add_behavior(Behavior.new(timed_blk))
                     end
                 end
             end

data/lib/HDLRuby/hruby_rcsim.rb

@@ -78,11 +78,13 @@ module HDLRuby::High
 
     
     ## Starts the simulation for top system +top+.
-    #  NOTE: +name+ is the name of the simulation and +vcd+ tells if
-    #        the vcd generation is used and +outpath+ is the path where
-    #        the faile is to save.
-    def self.rcsim(top,name,outpath,vcd)
-        RCSim.rcsim_main(top.rcsystemT,outpath +"/" + name,vcd)
+    #  NOTE: +name+ is the name of the simulation, +outpath+ is the path where
+    #        the output is to save, and +outmode+ is the output mode as follows:
+    #        0: standard
+    #        1: mute
+    #        2: vcd
+    def self.rcsim(top,name,outpath,outmode)
+        RCSim.rcsim_main(top.rcsystemT,outpath +"/" + name,outmode)
     end
 
 
@@ -741,7 +743,7 @@ module HDLRuby::High
             # Create and add the events.
             rcevs = []
             self.right.each_node_deep do |node|
-                if node.is_a?(RefObject) then
+                if node.is_a?(RefObject) && !node.parent.is_a?(RefObject) then
                     ev = RCSim.rcsim_make_event(:anyedge,node.to_rcsim)
                     RCSim.rcsim_set_owner(ev,@rcbehavior)
                     rcevs << ev
@@ -786,16 +788,24 @@ module HDLRuby::High
         def to_rcsim
             # Create the value C object.
             if self.content.is_a?(::Integer) then
-                if self.content.bit_length <= 63 then
-                    return RCSim.rcsim_make_value_numeric(self.type.to_rcsim,
-                                                    self.content)
+                # puts "self.type.width=#{self.type.width} and content=#{self.content}" ; $stdout.flush
+                if self.type.width <= 64 then
+                    if self.content.bit_length <= 63 then
+                        return RCSim.rcsim_make_value_numeric(self.type.to_rcsim,
+                                                              self.content)
+                    else
+                        return RCSim.rcsim_make_value_numeric(self.type.to_rcsim,
+                                                              self.content & 0xFFFFFFFFFFFF)
+                    end
                 else
-                    str = self.content.to_s(2)
-                    if str[-1] == "-" then
-                        str[-1] = "1"
-                    elsif str[-1] == "1" then
-                        str = "0" + str
+                    if self.content < 0 then
+                        str = (2**self.type.width + self.content).to_s(2)
+                        str = "1" * (self.type.width-str.length) + str
+                    else
+                        str = self.content.to_s(2)
+                        str = "0" * (self.type.width-str.length) + str
                     end
+                    # puts "now str=#{str} (#{str.length})" ; $stdout.flush
                     return RCSim.rcsim_make_value_bitstring(self.type.to_rcsim,
                                                             str.reverse)
                 end
@@ -945,7 +955,7 @@ module HDLRuby::High
             #     RCSim.rcsim_add_refConcat_ref(rcref,ref.to_rcsim)
             # end
             if self.each_ref.any? then
-                RCSim.rcsim_add_refConcat_refs(rcref,self.each_ref(&:to_rcsim))
+                RCSim.rcsim_add_refConcat_refs(rcref,self.each_ref.map(&:to_rcsim))
             end
             
             return rcref

data/lib/HDLRuby/hruby_rsim.rb

@@ -16,6 +16,14 @@ module HDLRuby::High
     # Enhance a system type with Ruby simulation.
     class SystemT
 
+        # Tell if the simulation is in multithread mode or not.
+        attr_reader :multithread
+
+        ## Add untimed objet +obj+
+        def add_untimed(obj)
+            @untimeds << obj
+        end
+
         ## Add timed behavior +beh+.
         #  Returns the id of the timed behavior.
         def add_timed_behavior(beh)
@@ -36,6 +44,63 @@ module HDLRuby::High
             @sig_active << sig
         end
 
+        ## Advance the global simulator.
+        def advance
+            # # Display the time
+            # self.show_time
+            shown_values = {}
+            # Get the behaviors waiting on activated signals.
+            until @sig_active.empty? do
+                # puts "sig_active.size=#{@sig_active.size}"
+                # puts "sig_active=#{@sig_active.map {|sig| sig.fullname}}"
+                # Look for the behavior sensitive to the signals.
+                # @sig_active.each do |sig|
+                #     sig.each_anyedge { |beh| @sig_exec << beh }
+                #     if (sig.c_value.zero? && !sig.f_value.zero?) then
+                #         # puts "sig.c_value=#{sig.c_value.content}"
+                #         sig.each_posedge { |beh| @sig_exec << beh }
+                #     elsif (!sig.c_value.zero? && sig.f_value.zero?) then
+                #         sig.each_negedge { |beh| @sig_exec << beh }
+                #     end
+                # end
+                @sig_active.each do |sig|
+                    next if (sig.c_value.eql?(sig.f_value))
+                    # next if (sig.c_value.to_vstr == sig.f_value.to_vstr)
+                    # puts "sig.c_value: #{sig.c_value.to_vstr}, sig.f_value=#{sig.f_value.to_vstr}"
+                    sig.each_anyedge { |beh| @sig_exec << beh }
+                    if (sig.c_value.zero?) then
+                        # puts "sig.c_value=#{sig.c_value.content}"
+                        sig.each_posedge { |beh| @sig_exec << beh }
+                    elsif (!sig.c_value.zero?) then
+                        sig.each_negedge { |beh| @sig_exec << beh }
+                    end
+                end
+                # Update the signals.
+                @sig_active.each { |sig| sig.c_value = sig.f_value }
+                # puts "first @sig_exec.size=#{@sig_exec.size}"
+                @sig_exec.uniq! {|beh| beh.object_id }
+                # Display the activated signals.
+                @sig_active.each do |sig|
+                    if !shown_values[sig].eql?(sig.f_value) then
+                        self.show_signal(sig) 
+                        shown_values[sig] = sig.f_value
+                    end
+                end
+                # Clear the list of active signals.
+                @sig_active.clear
+                # puts "sig_exec.size=#{@sig_exec.size}"
+                # Execute the relevant behaviors and connections.
+                @sig_exec.each { |obj| obj.execute(:par) }
+                @sig_exec.clear
+                @sig_active.uniq! {|sig| sig.object_id }
+                # puts "@sig_active.size=#{@sig_active.size}"
+                # Advance time.
+                @time = (@timed_behaviors.min {|b0,b1|  b0.time <=> b1.time }).time
+            end
+            # Display the time
+            self.show_time
+        end
+
         ## Run the simulation from the current systemT and outputs the resuts
         #  on simout.
         def sim(simout)
@@ -43,20 +108,13 @@ module HDLRuby::High
             HDLRuby.show "#{Time.now}#{show_mem}"
             # Merge the included.
             self.merge_included!
-            # Initializes the run mutex and the conditions.
-            @mutex = Mutex.new
-            @master = ConditionVariable.new
-            @master_flag = 0
-            @slave = ConditionVariable.new
-            @slave_flags_not = 0
-            @num_done = 0
-            # @lock = 0
-            # @runs = 0
             # Initializes the time.
             @time = 0
             # Initializes the time and signals execution buffers.
             @tim_exec = []
             @sig_exec = []
+            # Initilize the list of untimed objects.
+            @untimeds = []
             # Initialize the list of currently exisiting timed behavior.
             @timed_behaviors = []
             # Initialize the list of activated signals.
@@ -68,72 +126,97 @@ module HDLRuby::High
             self.init_sim(self)
             # Initialize the displayer.
             self.show_init(simout)
-            # exit
-            # First all the timed behaviors are to be executed.
-            @timed_behaviors.each {|beh| @tim_exec << beh }
-            # But starts locked.
-            @slave_flags_not = 2**@timed_behaviors.size - 1
-            # Starts the threads.
-            @timed_behaviors.each {|beh| beh.make_thread }
-
-            HDLRuby.show "Starting Ruby-level simulator..."
-            HDLRuby.show "#{Time.now}#{show_mem}"
-            # Run the simulation.
-            self.run_init do
-                # # Wake the behaviors.
-                # @timed_behaviors.each {|beh| beh.run }
-                until @tim_exec.empty? do
-                    # Display the time
-                    self.show_time
-                    # Execute the time behaviors that are ready.
-                    self.run_ack
-                    self.run_wait
-                    shown_values = {}
-                    # Get the behaviors waiting on activated signals.
-                    until @sig_active.empty? do
-                        # # Update the signals.
-                        # @sig_active.each { |sig| sig.c_value = sig.f_value }
-                        # puts "sig_active.size=#{@sig_active.size}"
-                        # Look for the behavior sensitive to the signals.
-                        @sig_active.each do |sig|
-                            sig.each_anyedge { |beh| @sig_exec << beh }
-                            if (sig.c_value.zero? && !sig.f_value.zero?) then
-                                # puts "sig.c_value=#{sig.c_value.content}"
-                                sig.each_posedge { |beh| @sig_exec << beh }
-                            elsif (!sig.c_value.zero? && sig.f_value.zero?) then
-                                sig.each_negedge { |beh| @sig_exec << beh }
-                            end
-                        end
-                        # Update the signals.
-                        @sig_active.each { |sig| sig.c_value = sig.f_value }
-                        # puts "first @sig_exec.size=#{@sig_exec.size}"
-                        @sig_exec.uniq! {|beh| beh.object_id }
-                        # Display the activated signals.
-                        @sig_active.each do |sig|
-                            if !shown_values[sig].eql?(sig.f_value) then
-                                self.show_signal(sig) 
-                                shown_values[sig] = sig.f_value
-                            end
+
+            # Initialize the untimed objects.
+            self.init_untimeds
+            # puts "End of init_untimed."
+
+            # Is there more than one timed behavior.
+            if @total_timed_behaviors <= 1 then
+                # No, no need of multithreading.
+                @multithread = false
+                # Simple execute the block of the behavior.
+                @timed_behaviors[0].block.execute(:seq)
+            else
+                # Yes, need of multithreading.
+                @multithread = true
+                # Initializes the run mutex and the conditions.
+                @mutex = Mutex.new
+                @master = ConditionVariable.new
+                @master_flag = 0
+                @slave = ConditionVariable.new
+                @slave_flags_not = 0
+                @num_done = 0
+
+                # First all the timed behaviors are to be executed.
+                @timed_behaviors.each {|beh| @tim_exec << beh }
+                # But starts locked.
+                @slave_flags_not = 2**@timed_behaviors.size - 1
+                # Starts the threads.
+                @timed_behaviors.each {|beh| beh.make_thread }
+
+                HDLRuby.show "Starting Ruby-level simulator..."
+                HDLRuby.show "#{Time.now}#{show_mem}"
+                # Run the simulation.
+                self.run_init do
+                    # # Wake the behaviors.
+                    # @timed_behaviors.each {|beh| beh.run }
+                    until @tim_exec.empty? do
+                        # Execute the time behaviors that are ready.
+                        self.run_ack
+                        self.run_wait
+                        # Advance the global simulator.
+                        self.advance
+                        # # Display the time
+                        # self.show_time
+                        # shown_values = {}
+                        # # Get the behaviors waiting on activated signals.
+                        # until @sig_active.empty? do
+                        #     # # Update the signals.
+                        #     # @sig_active.each { |sig| sig.c_value = sig.f_value }
+                        #     # puts "sig_active.size=#{@sig_active.size}"
+                        #     # Look for the behavior sensitive to the signals.
+                        #     @sig_active.each do |sig|
+                        #         sig.each_anyedge { |beh| @sig_exec << beh }
+                        #         if (sig.c_value.zero? && !sig.f_value.zero?) then
+                        #             # puts "sig.c_value=#{sig.c_value.content}"
+                        #             sig.each_posedge { |beh| @sig_exec << beh }
+                        #         elsif (!sig.c_value.zero? && sig.f_value.zero?) then
+                        #             sig.each_negedge { |beh| @sig_exec << beh }
+                        #         end
+                        #     end
+                        #     # Update the signals.
+                        #     @sig_active.each { |sig| sig.c_value = sig.f_value }
+                        #     # puts "first @sig_exec.size=#{@sig_exec.size}"
+                        #     @sig_exec.uniq! {|beh| beh.object_id }
+                        #     # Display the activated signals.
+                        #     @sig_active.each do |sig|
+                        #         if !shown_values[sig].eql?(sig.f_value) then
+                        #             self.show_signal(sig) 
+                        #             shown_values[sig] = sig.f_value
+                        #         end
+                        #     end
+                        #     # Clear the list of active signals.
+                        #     @sig_active.clear
+                        #     # puts "sig_exec.size=#{@sig_exec.size}"
+                        #     # Execute the relevant behaviors and connections.
+                        #     @sig_exec.each { |obj| obj.execute(:par) }
+                        #     @sig_exec.clear
+                        #     @sig_active.uniq! {|sig| sig.object_id }
+                        #     # puts "@sig_active.size=#{@sig_active.size}"
+                        # end
+
+                        # # Advance time.
+                        # @time = (@timed_behaviors.min {|b0,b1|  b0.time <=> b1.time }).time
+                        break if @timed_behaviors.empty?
+                        # Schedule the next timed behavior to execute.
+                        @tim_exec = []
+                        @timed_behaviors.each do |beh|
+                            @tim_exec << beh if beh.time == @time
                         end
-                        # Clear the list of active signals.
-                        @sig_active.clear
-                        # puts "sig_exec.size=#{@sig_exec.size}"
-                        # Execute the relevant behaviors and connections.
-                        @sig_exec.each { |obj| obj.execute(:par) }
-                        @sig_exec.clear
-                        @sig_active.uniq! {|sig| sig.object_id }
-                        # puts "@sig_active.size=#{@sig_active.size}"
+                        # puts "@tim_exec.size=#{@tim_exec.size}"
+                        # puts "@timed_bevaviors.size=#{@timed_behaviors.size}"
                     end
-                    break if @timed_behaviors.empty?
-                    # Advance time.
-                    @time = (@timed_behaviors.min {|b0,b1|  b0.time <=> b1.time }).time
-                    # Schedule the next timed behavior to execute.
-                    @tim_exec = []
-                    @timed_behaviors.each do |beh|
-                        @tim_exec << beh if beh.time == @time
-                    end
-                    # puts "@tim_exec.size=#{@tim_exec.size}"
-                    # puts "@timed_bevaviors.size=#{@timed_behaviors.size}"
                 end
             end
         end
@@ -146,6 +229,17 @@ module HDLRuby::High
             # Recure on the scope.
             self.scope.init_sim(systemT)
         end
+
+        ## Initialize the untimed objects.
+        def init_untimeds
+            @untimeds.each do |obj|
+                if obj.is_a?(Behavior) then
+                    obj.block.execute(:seq)
+                else
+                    obj.execute(:seq)
+                end
+            end
+        end
         
         ## Initialize run for executing +ruby_block+
         def run_init(&ruby_block)
@@ -278,6 +372,8 @@ module HDLRuby::High
 
         ## Initialize the simulation for system +systemT+.
         def init_sim(systemT)
+            # Add the behavior to the list of untimed objects.
+            systemT.add_untimed(self)
             # Process the sensitivity list.
             # Is it a clocked behavior?
             events = self.each_event.to_a
@@ -292,6 +388,7 @@ module HDLRuby::High
                 end.to_a
                 # Keep only one ref per signal.
                 refs.uniq! { |node| node.fullname }
+                # puts "refs=#{refs.map {|node| node.fullname}}"
                 # Remove the inner signals from the list.
                 self.block.each_inner do |inner|
                     refs.delete_if {|r| r.name == inner.name }
@@ -358,7 +455,8 @@ module HDLRuby::High
                     begin
                         # puts "Starting thread"
                         systemT.run_req(@id)
-                        self.block.execute(:par)
+                        # self.block.execute(:par)
+                        self.block.execute(:seq)
                         # puts "Ending thread"
                     rescue => e
                         puts "Got exception: #{e.full_message}"
@@ -456,8 +554,8 @@ module HDLRuby::High
             @f_value = value
             # Set the mode.
             @mode = mode
-            # puts "assign #{value.content} (#{value.content.class}) with self.type.width=#{self.type.width} while value.type.width=#{value.type.width}" if self.name.to_s.include?("idx")
-            # @f_value = value.cast(self.type) # Cast inserted by HDLRuby normally
+            # puts "assign #{value.content} (#{value.content.class}) with self.type.width=#{self.type.width} while value.type.width=#{value.type.width}" if self.name.to_s.include?("xnor")
+            @f_value = value.cast(self.type) # Cast not always inserted by HDLRuby normally
         end
 
         ## Assigns +value+ at +index+ (integer or range).
@@ -607,7 +705,7 @@ module HDLRuby::High
         ## Initialize the simulation for system +systemT+.
         def init_sim(systemT)
             self.each_when { |wh| wh.init_sim(systemT) }
-            self.default.init_sim(systemT)
+            self.default.init_sim(systemT) if self.default
         end
 
         ## Executes the statement.
@@ -618,7 +716,7 @@ module HDLRuby::High
                     return
                 end
             end
-                self.default.execute(mode)
+            self.default.execute(mode) if self.default
             end
         end
     end
@@ -690,10 +788,16 @@ module HDLRuby::High
         def execute(mode)
             @behavior ||= self.behavior
             @behavior.time += self.delay.time_ps
-            # puts "Stopping #{@behavior.object_id} (@behavior.time=#{@behavior.time})..."
-            @sim.run_done(@behavior.id)
-            # puts "Rerunning #{@behavior.object_id} (@behavior.time=#{@behavior.time})..."
-            @sim.run_req(@behavior.id)
+            if @sim.multithread then
+                # Multi thread mode: synchronize.
+                # puts "Stopping #{@behavior.object_id} (@behavior.time=#{@behavior.time})..."
+                @sim.run_done(@behavior.id)
+                # puts "Rerunning #{@behavior.object_id} (@behavior.time=#{@behavior.time})..."
+                @sim.run_req(@behavior.id)
+            else
+                # No thread mode, need to advance the global simulator.
+                @sim.advance
+            end
         end
     end
 
@@ -783,6 +887,8 @@ module HDLRuby::High
 
         ## Initialize the simulation for system +systemT+.
         def init_sim(systemT)
+            # Add the connection to the list of untimed objets.
+            systemT.add_untimed(self)
             # Recurse on the left.
             self.left.init_sim(systemT)
             # Process the sensitivity list.
@@ -795,6 +901,8 @@ module HDLRuby::High
             end.to_a
             # Keep only one ref per signal.
             refs.uniq! { |node| node.fullname }
+            # puts "connection input: #{self.left.fullname}"
+            # puts "connection refs=#{refs.map {|node| node.fullname}}"
             # # Generate the event.
             # events = refs.map {|ref| Event.new(:anyedge,ref) }
             # # Add them to the behavior for further processing.
@@ -806,7 +914,7 @@ module HDLRuby::High
 
         ## Executes the statement.
         def execute(mode)
-            # puts "connection = #{self}"
+            # puts "connection = #{self}" if self.left.is_a?(RefObject) && self.left.object.name.to_s.include?("xnor")
             self.left.assign(mode,self.right.execute(mode))
         end
     end
@@ -906,10 +1014,18 @@ module HDLRuby::High
     class Select
         ## Execute the expression.
         def execute(mode)
+            unless @mask then
+                # Need to initialize the execution of the select.
+                width = (@choices.size-1).width
+                width = 1 if width == 0
+                @mask = 2**width - 1
+                @choices.concat([@choices[-1]] * (2**width-@choices.size))
+            end
             # Recurse on the select.
-            tmps = self.select.execute(mode)
+            tmps = self.select.execute(mode).to_i & @mask
+            # puts "select tmps=#{tmps}, @choices.size=#{@choices.size}"
             # Recurse on the selection result.
-            return @choices[tmps.to_i].execute(mode)
+            return @choices[tmps].execute(mode)
         end
     end
 

data/lib/HDLRuby/hruby_rsim_mute.rb

@@ -0,0 +1,35 @@
+require "HDLRuby/hruby_rsim"
+
+##
+# Library for enhancing the Ruby simulator with VCD support
+#
+########################################################################
+module HDLRuby::High
+
+    ##
+    # Enhance the system type class with VCD support.
+    class SystemT
+
+        ## Initializes the displayer for generating a vcd on +vcdout+
+        def show_init(vcdout)
+        end
+
+        ## Displays the time.
+        def show_time
+        end
+
+        ## Displays the value of signal +sig+.
+        def show_signal(sig)
+        end
+
+        ## Displays value +val+.
+        #  NOTE: for now displays on the standard output and NOT the vcd.
+        def show_value(val)
+        end
+
+        ## Displays string +str+.
+        def show_string(str)
+        end
+    end
+
+end