HDLRuby 2.10.3 → 2.11.0
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- checksums.yaml +4 -4
- data/HDLRuby.gemspec +1 -0
- data/README.md +8 -4
- data/Rakefile +8 -0
- data/{lib/HDLRuby/sim/Makefile → ext/hruby_sim/Makefile_csim} +0 -0
- data/ext/hruby_sim/extconf.rb +13 -0
- data/ext/hruby_sim/hruby_rcsim_build.c +1188 -0
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim.h +255 -16
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_calc.c +310 -181
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_core.c +34 -17
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_list.c +0 -0
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_stack_calc.c +4 -1
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_stack_calc.c.sav +0 -0
- data/ext/hruby_sim/hruby_sim_tree_calc.c +375 -0
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_vcd.c +5 -5
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_vizualize.c +2 -2
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_value_pool.c +4 -1
- data/lib/HDLRuby/hdr_samples/bstr_bench.rb +2 -0
- data/lib/HDLRuby/hdr_samples/case_bench.rb +2 -2
- data/lib/HDLRuby/hdr_samples/counter_bench.rb +0 -1
- data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb +46 -0
- data/lib/HDLRuby/hdr_samples/dff_bench.rb +4 -1
- data/lib/HDLRuby/hdr_samples/dff_override.rb +76 -0
- data/lib/HDLRuby/hdr_samples/print_bench.rb +62 -0
- data/lib/HDLRuby/hdr_samples/rom.rb +5 -3
- data/lib/HDLRuby/hdr_samples/simple_counter_bench.rb +43 -0
- data/lib/HDLRuby/hdr_samples/with_values.rb +14 -0
- data/lib/HDLRuby/hdrcc.rb +84 -21
- data/lib/HDLRuby/hruby_bstr.rb +1175 -917
- data/lib/HDLRuby/hruby_high.rb +267 -97
- data/lib/HDLRuby/hruby_high_fullname.rb +82 -0
- data/lib/HDLRuby/hruby_low.rb +110 -71
- data/lib/HDLRuby/hruby_low2c.rb +7 -0
- data/lib/HDLRuby/hruby_low_mutable.rb +1 -1
- data/lib/HDLRuby/hruby_low_without_namespace.rb +2 -1
- data/lib/HDLRuby/hruby_rcsim.rb +978 -0
- data/lib/HDLRuby/hruby_rsim.rb +1134 -0
- data/lib/HDLRuby/hruby_rsim_vcd.rb +322 -0
- data/lib/HDLRuby/hruby_values.rb +362 -18
- data/lib/HDLRuby/hruby_verilog.rb +21 -3
- data/lib/HDLRuby/std/handshakes.rb +1 -1
- data/lib/HDLRuby/version.rb +1 -1
- metadata +25 -13
@@ -44,7 +44,9 @@ Value get_value() {
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44
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}
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45
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}
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46
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/* Readjust the position in the pool and return the value. */
|
47
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-
return pool_values[pool_pos++];
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+
// return pool_values[pool_pos++];
|
48
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+
Value res = pool_values[pool_pos++];
|
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+
return res;
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50
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}
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/** Get the current top value. */
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@@ -59,6 +61,7 @@ Value get_top_value() {
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/** Frees the last value of the pool. */
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void free_value() {
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+
if (pool_pos <= 0) { printf("Pool error!\n");exit(1);}
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if (pool_pos > 0) pool_pos--;
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}
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@@ -0,0 +1,46 @@
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1
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# A simple D-FF
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system :dff do
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input :clk, :d
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output q: 0
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(q <= d).at(clk.posedge)
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end
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# A benchmark for the dff.
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system :dff_bench do
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inner :clk
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inner :d0, :q0, :d1, :q1
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+
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dff(:my_dff0).(clk,d0,q0)
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dff(:my_dff1).(d0,d1,q1)
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d0 <= ~q0
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d1 <= ~q1
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timed do
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clk <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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!10.ns
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clk <= 1
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!10.ns
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end
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end
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@@ -0,0 +1,76 @@
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# A simple D-FF with overridable part.
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system :dff do
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input :d, :clk, :rst
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output :q
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sub(:process) do
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(q <= d & ~rst).at(clk.posedge)
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end
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end
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# A new dff overriding process.
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system :dff_neg, dff do
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sub(:process) do
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(q <= d & ~rst).at(clk.negedge)
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end
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end
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# A benchmark for the dff.
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system :dff_bench do
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inner :d, :clk, :rst
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inner :q
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dff_neg(:my_dff).(d,clk,rst,q)
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# dff(:my_dff).(d,clk,rst,q)
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timed do
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clk <= 1
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rst <= 0
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d <= _z
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!10.ns
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clk <= 0
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rst <= 0
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d <= _z
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!10.ns
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clk <= 1
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rst <= 1
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d <= _z
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!10.ns
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clk <= 0
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rst <= 1
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d <= _z
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!10.ns
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clk <= 1
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rst <= 0
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d <= 1
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!10.ns
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clk <= 0
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rst <= 0
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d <= 1
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!10.ns
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clk <= 1
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rst <= 0
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d <= 1
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!10.ns
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clk <= 0
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rst <= 0
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d <= 1
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!10.ns
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clk <= 1
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rst <= 0
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d <= 0
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!10.ns
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clk <= 0
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rst <= 0
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d <= 0
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!10.ns
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clk <= 1
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rst <= 0
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d <= 0
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!10.ns
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clk <= 0
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rst <= 0
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d <= 0
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!10.ns
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end
|
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end
|
@@ -0,0 +1,62 @@
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1
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##
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# A simple system for testing hw print and strings.
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######################################################
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|
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system :with_print do
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input :clk, :rst
|
7
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[4].output :counter
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8
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+
|
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seq(clk.posedge) do
|
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hif(rst) do
|
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counter <= 0
|
12
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+
end
|
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helse do
|
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counter <= counter + 1
|
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hprint("In '#{__FILE__}' line #{__LINE__}: ")
|
16
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+
hprint("Counter=", counter, "\n")
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+
end
|
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end
|
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+
end
|
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|
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# A benchmark for the dff.
|
22
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system :with_print_bench do
|
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+
inner :clk, :rst
|
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[4].inner :counter
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+
|
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with_print(:my_print).(clk,rst,counter)
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27
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+
|
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timed do
|
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clk <= 0
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rst <= 0
|
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+
!10.ns
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clk <= 1
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rst <= 0
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!10.ns
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clk <= 0
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rst <= 1
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!10.ns
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clk <= 1
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rst <= 1
|
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!10.ns
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clk <= 0
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rst <= 0
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!10.ns
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clk <= 1
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!10.ns
|
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clk <= 0
|
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!10.ns
|
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clk <= 1
|
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!10.ns
|
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clk <= 0
|
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!10.ns
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clk <= 1
|
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!10.ns
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clk <= 0
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!10.ns
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clk <= 1
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!10.ns
|
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end
|
59
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+
|
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# cur_system.properties[:pre_driver] = "drivers/hw_print.rb", :hw_print_generator
|
62
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+
end
|
@@ -6,9 +6,11 @@ system :rom4_8 do
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6
6
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[2..0].input :addr
|
7
7
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[7..0].output :data0,:data1,:data2
|
8
8
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9
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-
bit[7..0][0..7].constant content0: [
|
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-
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-
|
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bit[7..0][0..7].constant content0: [_00000000,_00000001,_00000010,_00000011,
|
10
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+
_00000100,_00000101,_00000110,_00000111]
|
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signed[7..0][-8].constant content1: [_sh00,_sh01,_sh02,_sh03,
|
12
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_sh04,_sh05,_sh06,_sh07]
|
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typ[-8].constant content2: (8).times.map {|i| i.to_expr.as(typ) }.reverse
|
12
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data0 <= content0[addr]
|
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data1 <= content1[addr]
|
@@ -0,0 +1,43 @@
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# A benchmark for very simple counters.
|
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# Also test the use of ~ on the clock.
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system :counter_bench do
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4
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inner :clk, :rst
|
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[3].inner :counter
|
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[4].inner :counter2
|
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|
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par(clk.posedge) do
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hif(rst) { counter <= 0 }
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helse { counter <= counter + 1 }
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end
|
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|
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par(clk.posedge) do
|
14
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hif(rst) { counter2 <= 0 }
|
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helse { counter2 <= counter2 + 1 }
|
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end
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timed do
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clk <= 0
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rst <= 0
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!10.ns
|
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clk <= 1
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rst <= 0
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!10.ns
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clk <= ~clk
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rst <= 1
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!10.ns
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clk <= ~clk
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!10.ns
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clk <= ~clk
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rst <= 0
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!10.ns
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clk <= ~clk
|
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!10.ns
|
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10.times do
|
37
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clk <= ~clk
|
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!10.ns
|
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clk <= ~clk
|
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!10.ns
|
41
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end
|
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end
|
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end
|
@@ -37,6 +37,20 @@ system :with_values do
|
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37
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v64 <= 128
|
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38
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v96 <= 128
|
39
39
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!10.ns
|
40
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v8 <= -1
|
41
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v16 <= -1
|
42
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v32 <= -1
|
43
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v56 <= -1
|
44
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v64 <= -1
|
45
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v96 <= -1
|
46
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+
!10.ns
|
47
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+
v8 <= -2
|
48
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+
v16 <= -2
|
49
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v32 <= -2
|
50
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v56 <= -2
|
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v64 <= -2
|
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v96 <= -2
|
53
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!10.ns
|
40
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|
v16 <= 0x1000
|
41
55
|
v32 <= 0x1000
|
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|
v56 <= 0x1000
|
data/lib/HDLRuby/hdrcc.rb
CHANGED
@@ -36,6 +36,22 @@ if ARGV.include?("-I") || ARGV.include?("--interactive") then
|
|
36
36
|
abort
|
37
37
|
end
|
38
38
|
|
39
|
+
|
40
|
+
begin
|
41
|
+
# We can check the memory.
|
42
|
+
require 'get_process_mem'
|
43
|
+
$memory_check = GetProcessMem.new
|
44
|
+
def show_mem
|
45
|
+
" | "+$memory_check.bytes.to_s+"B"
|
46
|
+
end
|
47
|
+
rescue LoadError
|
48
|
+
# We cannot check the memory.
|
49
|
+
def show_mem
|
50
|
+
""
|
51
|
+
end
|
52
|
+
end
|
53
|
+
|
54
|
+
|
39
55
|
require 'fileutils'
|
40
56
|
require 'tempfile'
|
41
57
|
require 'HDLRuby'
|
@@ -67,6 +83,7 @@ require 'HDLRuby/backend/hruby_c_allocator'
|
|
67
83
|
|
68
84
|
require 'HDLRuby/version.rb'
|
69
85
|
|
86
|
+
|
70
87
|
##
|
71
88
|
# HDLRuby compiler interface program
|
72
89
|
#####################################
|
@@ -346,10 +363,22 @@ $optparse = OptionParser.new do |opts|
|
|
346
363
|
opts.on("--allocate=LOW,HIGH,WORD","Allocate signals to addresses") do |v|
|
347
364
|
$options[:allocate] = v
|
348
365
|
end
|
349
|
-
opts.on("-S",
|
366
|
+
opts.on("-S","--sim","Default simulator (hybrid C-Ruby)") do |v|
|
367
|
+
$options[:rcsim] = v
|
368
|
+
$options[:multiple] = v
|
369
|
+
end
|
370
|
+
opts.on("--csim","Standalone C-based simulator") do |v|
|
350
371
|
$options[:clang] = v
|
351
372
|
$options[:multiple] = v
|
352
|
-
$options[:
|
373
|
+
$options[:csim] = v
|
374
|
+
end
|
375
|
+
opts.on("--rsim","Ruby-based simulator") do |v|
|
376
|
+
$options[:rsim] = v
|
377
|
+
$options[:multiple] = v
|
378
|
+
end
|
379
|
+
opts.on("--rcsim","Hybrid C-Ruby-based simulator") do |v|
|
380
|
+
$options[:rcsim] = v
|
381
|
+
$options[:multiple] = v
|
353
382
|
end
|
354
383
|
opts.on("--vcd", "The simulator will generate a vcd file") do |v|
|
355
384
|
$options[:vcd] = v
|
@@ -525,7 +554,7 @@ if $options[:syntax] then
|
|
525
554
|
$output << $loader.show_all
|
526
555
|
exit
|
527
556
|
end
|
528
|
-
HDLRuby.show Time.now
|
557
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
529
558
|
HDLRuby.show "##### Starting parser #####"
|
530
559
|
|
531
560
|
if $options[:debug] then
|
@@ -538,12 +567,12 @@ end
|
|
538
567
|
|
539
568
|
# Generate the result.
|
540
569
|
# Get the top systemT.
|
541
|
-
HDLRuby.show Time.now
|
542
|
-
|
570
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
571
|
+
# Ruby simulation uses the HDLRuby::High tree, other the HDLRuby::Lowais used
|
572
|
+
$top_system = ($options[:rsim] || $options[:rcsim]) ? $top_instance.systemT : $top_instance.to_low.systemT
|
543
573
|
$top_intance = nil # Free as much memory as possible.
|
544
574
|
HDLRuby.show "##### Top system built #####"
|
545
|
-
HDLRuby.show Time.now
|
546
|
-
|
575
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
547
576
|
|
548
577
|
# # Apply the pre drivers if any.
|
549
578
|
# Hdecorator.each_with_property(:pre_driver) do |obj, value|
|
@@ -613,19 +642,19 @@ elsif $options[:clang] then
|
|
613
642
|
# Coverts the par blocks in seq blocks to seq blocks to match
|
614
643
|
# the simulation engine.
|
615
644
|
systemT.par_in_seq2seq!
|
616
|
-
HDLRuby.show Time.now
|
645
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
617
646
|
HDLRuby.show "connections_to_behaviors step..."
|
618
647
|
# Converts the connections to behaviors.
|
619
648
|
systemT.connections_to_behaviors!
|
620
|
-
HDLRuby.show Time.now
|
649
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
621
650
|
# Break the RefConcat.
|
622
651
|
HDLRuby.show "concat_assigns step..."
|
623
652
|
systemT.break_concat_assigns!
|
624
|
-
HDLRuby.show Time.now
|
653
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
625
654
|
# Explicits the types.
|
626
655
|
HDLRuby.show "explicit_types step..."
|
627
656
|
systemT.explicit_types!
|
628
|
-
HDLRuby.show Time.now
|
657
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
629
658
|
end
|
630
659
|
# Generate the C.
|
631
660
|
if $options[:multiple] then
|
@@ -729,11 +758,12 @@ elsif $options[:clang] then
|
|
729
758
|
$output << HDLRuby::Low::Low2C.main(top_system,
|
730
759
|
*top_system.each_systemT_deep.to_a)
|
731
760
|
end
|
732
|
-
if $options[:
|
761
|
+
if $options[:csim] then
|
733
762
|
# Simulation mode, compile and exectute.
|
734
763
|
# Path of the simulator core files.
|
735
|
-
# simdir =
|
736
|
-
|
764
|
+
# $simdir = $hdr_dir + "sim/"
|
765
|
+
# puts "$hdr_dir=#{$hdr_dir}"
|
766
|
+
$simdir = $hdr_dir + "/../../ext/hruby_sim/"
|
737
767
|
# Generate and execute the simulation commands.
|
738
768
|
# Kernel.system("cp -n #{simdir}* #{$output}/; cd #{$output}/ ; make -s ; ./hruby_simulator")
|
739
769
|
Dir.entries($simdir).each do |filename|
|
@@ -768,23 +798,23 @@ elsif $options[:verilog] then
|
|
768
798
|
# HDLRuby.show Time.now
|
769
799
|
HDLRuby.show "to_upper_space! step..."
|
770
800
|
systemT.to_upper_space!
|
771
|
-
HDLRuby.show Time.now
|
801
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
772
802
|
end
|
773
803
|
HDLRuby.show "to_global_space! step (global)..."
|
774
804
|
$top_system.to_global_systemTs!
|
775
|
-
HDLRuby.show Time.now
|
805
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
776
806
|
$top_system.each_systemT_deep do |systemT|
|
777
807
|
## systemT.break_types!
|
778
808
|
## systemT.expand_types!
|
779
809
|
HDLRuby.show "par_in_seq2seq! step..."
|
780
810
|
systemT.par_in_seq2seq!
|
781
|
-
HDLRuby.show Time.now
|
811
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
782
812
|
HDLRuby.show "initial_concat_to_timed! step..."
|
783
813
|
systemT.initial_concat_to_timed!
|
784
|
-
HDLRuby.show Time.now
|
814
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
785
815
|
HDLRuby.show "with_port! step..."
|
786
816
|
systemT.with_port!
|
787
|
-
HDLRuby.show Time.now
|
817
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
788
818
|
end
|
789
819
|
# # Verilog generation
|
790
820
|
# $output << top_system.to_verilog
|
@@ -809,7 +839,8 @@ elsif $options[:verilog] then
|
|
809
839
|
# Open the file for current systemT
|
810
840
|
outfile = File.open($name,"w")
|
811
841
|
# Generate the Verilog code in to.
|
812
|
-
outfile << systemT.to_verilog
|
842
|
+
# outfile << systemT.to_verilog
|
843
|
+
outfile << systemT.to_verilog($options[:vcd])
|
813
844
|
# Close the file.
|
814
845
|
outfile.close
|
815
846
|
# Clears the name.
|
@@ -821,6 +852,38 @@ elsif $options[:verilog] then
|
|
821
852
|
$output << systemT.to_verilog
|
822
853
|
end
|
823
854
|
end
|
855
|
+
elsif $options[:rsim] then
|
856
|
+
HDLRuby.show "Loading Ruby-level simulator..."
|
857
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
858
|
+
# Ruby-level simulation.
|
859
|
+
require 'HDLRuby/hruby_rsim.rb'
|
860
|
+
# Is VCD output is required.
|
861
|
+
if $options[:vcd] then
|
862
|
+
# Yes
|
863
|
+
require "HDLRuby/hruby_rsim_vcd.rb"
|
864
|
+
vcdout = File.open($output+"/hruby_simulator.vcd","w")
|
865
|
+
$top_system.sim(vcdout)
|
866
|
+
vcdout.close
|
867
|
+
else
|
868
|
+
# No
|
869
|
+
$top_system.sim($stdout)
|
870
|
+
end
|
871
|
+
HDLRuby.show "End of Ruby-level simulation..."
|
872
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
873
|
+
elsif $options[:rcsim] then
|
874
|
+
HDLRuby.show "Building the hybrid C-Ruby-level simulator..."
|
875
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
876
|
+
# C-Ruby-level simulation.
|
877
|
+
require 'HDLRuby/hruby_rcsim.rb'
|
878
|
+
# Merge the included from the top system.
|
879
|
+
$top_system.merge_included!
|
880
|
+
# Generate the C data structures.
|
881
|
+
$top_system.to_rcsim
|
882
|
+
HDLRuby.show "Executing the hybrid C-Ruby-level simulator..."
|
883
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
884
|
+
HDLRuby::High.rcsim($top_system,"hruby_simulator",$output,$options[:vcd] && true)
|
885
|
+
HDLRuby.show "End of hybrid C-Ruby-level simulation..."
|
886
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
824
887
|
elsif $options[:vhdl] then
|
825
888
|
# top_system = $top_instance.to_low.systemT
|
826
889
|
# top_system = $top_system
|
@@ -875,7 +938,7 @@ elsif $options[:vhdl] then
|
|
875
938
|
end
|
876
939
|
|
877
940
|
HDLRuby.show "##### Code generated #####"
|
878
|
-
HDLRuby.show Time.now
|
941
|
+
HDLRuby.show "#{Time.now}#{show_mem}"
|
879
942
|
|
880
943
|
# # Apply the post drivers if any.
|
881
944
|
# Hdecorator.each_with_property(:post_driver) do |obj, value|
|