HDLRuby 2.10.3 → 2.11.0
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/HDLRuby.gemspec +1 -0
- data/README.md +8 -4
- data/Rakefile +8 -0
- data/{lib/HDLRuby/sim/Makefile → ext/hruby_sim/Makefile_csim} +0 -0
- data/ext/hruby_sim/extconf.rb +13 -0
- data/ext/hruby_sim/hruby_rcsim_build.c +1188 -0
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim.h +255 -16
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_calc.c +310 -181
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_core.c +34 -17
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_list.c +0 -0
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_stack_calc.c +4 -1
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_stack_calc.c.sav +0 -0
- data/ext/hruby_sim/hruby_sim_tree_calc.c +375 -0
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_vcd.c +5 -5
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_vizualize.c +2 -2
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_value_pool.c +4 -1
- data/lib/HDLRuby/hdr_samples/bstr_bench.rb +2 -0
- data/lib/HDLRuby/hdr_samples/case_bench.rb +2 -2
- data/lib/HDLRuby/hdr_samples/counter_bench.rb +0 -1
- data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb +46 -0
- data/lib/HDLRuby/hdr_samples/dff_bench.rb +4 -1
- data/lib/HDLRuby/hdr_samples/dff_override.rb +76 -0
- data/lib/HDLRuby/hdr_samples/print_bench.rb +62 -0
- data/lib/HDLRuby/hdr_samples/rom.rb +5 -3
- data/lib/HDLRuby/hdr_samples/simple_counter_bench.rb +43 -0
- data/lib/HDLRuby/hdr_samples/with_values.rb +14 -0
- data/lib/HDLRuby/hdrcc.rb +84 -21
- data/lib/HDLRuby/hruby_bstr.rb +1175 -917
- data/lib/HDLRuby/hruby_high.rb +267 -97
- data/lib/HDLRuby/hruby_high_fullname.rb +82 -0
- data/lib/HDLRuby/hruby_low.rb +110 -71
- data/lib/HDLRuby/hruby_low2c.rb +7 -0
- data/lib/HDLRuby/hruby_low_mutable.rb +1 -1
- data/lib/HDLRuby/hruby_low_without_namespace.rb +2 -1
- data/lib/HDLRuby/hruby_rcsim.rb +978 -0
- data/lib/HDLRuby/hruby_rsim.rb +1134 -0
- data/lib/HDLRuby/hruby_rsim_vcd.rb +322 -0
- data/lib/HDLRuby/hruby_values.rb +362 -18
- data/lib/HDLRuby/hruby_verilog.rb +21 -3
- data/lib/HDLRuby/std/handshakes.rb +1 -1
- data/lib/HDLRuby/version.rb +1 -1
- metadata +25 -13
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
|
---
|
2
2
|
SHA256:
|
3
|
-
metadata.gz:
|
4
|
-
data.tar.gz:
|
3
|
+
metadata.gz: a9fc5a3510b44232e5c7f34b3cf519692690fdac2cf4c0ae1078d8493eaf78d0
|
4
|
+
data.tar.gz: 0bbb47f453e246c0bb90e9714b59b07240bc92273f975ac3074b21cbb8e85099
|
5
5
|
SHA512:
|
6
|
-
metadata.gz:
|
7
|
-
data.tar.gz:
|
6
|
+
metadata.gz: 601d7638bb702da17e6dd85ea969ae3015fbd18775b94fcb77e69315bb1ccd4684e41dd5791538ddda5918d13b36d5550e167a7021dcc0ed5155427a2ffe23f1
|
7
|
+
data.tar.gz: 7a7a657dbc3b675dec95a3073b9f71026645d38fde2ff8e84dce0a2a69d3f3c6eff9fd28c0b581249a2033010d5a4fd420f5979511e07170af02b7ec88a68b5b
|
data/HDLRuby.gemspec
CHANGED
@@ -26,6 +26,7 @@ Gem::Specification.new do |spec|
|
|
26
26
|
spec.executables = spec.files.grep(%r{^exe/}) { |f| File.basename(f) }
|
27
27
|
# spec.require_paths = ["lib"]
|
28
28
|
spec.require_paths = ["lib","lib/HDLRuby"]
|
29
|
+
spec.extensions = %w[ext/hruby_sim/extconf.rb]
|
29
30
|
|
30
31
|
spec.required_ruby_version = '>= 2.0'
|
31
32
|
# spec.add_development_dependency "bundler", "~> 2.0.1"
|
data/README.md
CHANGED
@@ -49,8 +49,11 @@ Where:
|
|
49
49
|
| `-v, --verilog` | Output in Verilog HDL format |
|
50
50
|
| `-V, --vhdl` | Output in VHDL format |
|
51
51
|
| `-s, --syntax` | Output the Ruby syntax tree |
|
52
|
-
| `-C, --clang` | Output the C code of the simulator
|
53
|
-
| `-S, --sim` |
|
52
|
+
| `-C, --clang` | Output the C code of the standalone simulator. |
|
53
|
+
| `-S, --sim` | Perform the simulation with the default engine. |
|
54
|
+
| `--csim` | Perform the simulation with the standalone engine. |
|
55
|
+
| `--rsim` | Perform the simulation with the Ruby engine. |
|
56
|
+
| `--rcsim` | Perform the simulation with the Hybris engine. |
|
54
57
|
| `--vcd` | Make the simulator generate a VCD file |
|
55
58
|
| `-d, --directory` | Specify the base directory for loading the HDLRuby files |
|
56
59
|
| `-D, --debug` | Set the HDLRuby debug mode |
|
@@ -91,13 +94,14 @@ hdrcc -V -t adder --param 16 adder_gen.rb adder
|
|
91
94
|
hdrcc -y -t multer -p 16,16,32 multer_gen.rb multer
|
92
95
|
```
|
93
96
|
|
94
|
-
* Simulate the circuit described in file `counter_bench.rb` using directory `counter
|
95
|
-
storing the simulator's files:
|
97
|
+
* Simulate the circuit described in file `counter_bench.rb` using the default simluation engine and putting the simulator's files in directory `counter`:
|
96
98
|
|
97
99
|
```
|
98
100
|
hdrcc -S counter_bench.rb counter
|
99
101
|
```
|
100
102
|
|
103
|
+
As a policy, the default simulation enigne is set to the fastest one (cuttently it is the hybrid engine).
|
104
|
+
|
101
105
|
* Run in interactive mode.
|
102
106
|
|
103
107
|
```
|
data/Rakefile
CHANGED
@@ -1,5 +1,11 @@
|
|
1
1
|
require "bundler/gem_tasks"
|
2
2
|
require "rake/testtask"
|
3
|
+
require "rake/extensiontask"
|
4
|
+
|
5
|
+
Rake::ExtensionTask.new "hruby_sim" do |ext|
|
6
|
+
ext.lib_dir = "lib/hruby_sim"
|
7
|
+
end
|
8
|
+
|
3
9
|
|
4
10
|
Rake::TestTask.new(:test) do |t|
|
5
11
|
t.libs << "test"
|
@@ -7,4 +13,6 @@ Rake::TestTask.new(:test) do |t|
|
|
7
13
|
t.test_files = FileList['test/**/*_test.rb']
|
8
14
|
end
|
9
15
|
|
16
|
+
|
17
|
+
|
10
18
|
task :default => :test
|
File without changes
|
@@ -0,0 +1,13 @@
|
|
1
|
+
require 'mkmf'
|
2
|
+
|
3
|
+
append_cppflags(["-DRCSIM"])
|
4
|
+
# For debugging RCSIM
|
5
|
+
append_cflags(["-g"])
|
6
|
+
# append_cflags(["-fsanitize=address"])
|
7
|
+
# append_ldflags(["-fsanitize=address"])
|
8
|
+
|
9
|
+
abort "missing malloc()" unless have_func "malloc"
|
10
|
+
abort "missing free()" unless have_func "free"
|
11
|
+
|
12
|
+
create_header
|
13
|
+
create_makefile 'hruby_sim/hruby_sim'
|