GBRb 0.1.0

data/spec/gbrb/cpu/register_ensemble_spec.rb

@@ -0,0 +1,84 @@
+require_relative '../../spec_helper.rb'
+require_relative '../../../lib/gbrb/cpu/register_ensemble'
+
+module GBRb::CPU
+  describe RegisterEnsemble do
+    def register_bit_count label
+      @re.public_send(label.to_sym).instance_eval("@bits")
+    end
+
+    before {@re = RegisterEnsemble.new }
+    it "has an a register" do
+      register_bit_count(:a).should eq 8
+    end
+
+    it "has an 8-bit b register" do
+      register_bit_count(:b).should eq 8
+    end
+
+    it "has an 8-bit c register" do
+      register_bit_count(:c).should eq 8
+    end
+
+    it "has an 8-bit d register" do
+      register_bit_count(:d).should eq 8
+    end
+
+    it "has an 8-bit e register" do
+      register_bit_count(:e).should eq 8
+    end
+
+    it "has an 8-bit h register" do
+      register_bit_count(:h).should eq 8
+    end
+
+    it "has an 8-bit l register" do
+      register_bit_count(:l).should eq 8
+    end
+
+    it "has an 8-bit f register" do
+      register_bit_count(:f).should eq 8
+    end
+
+    it "has a 16-bit pc register" do
+      register_bit_count(:pc).should eq 16
+    end
+
+    it "has a 16-bit sp register" do
+      register_bit_count(:sp).should eq 16
+    end
+
+    it "has an 8-bit m register" do
+      register_bit_count(:m).should eq 8
+    end
+
+    it "has an 8-bit t register" do
+      register_bit_count(:t).should eq 8
+    end
+
+    it "provides access to bc as one 16-bit register" do
+      register_bit_count(:bc).should eq 16
+    end
+
+    it "provides access to de as one 16-bit register" do
+      register_bit_count(:de).should eq 16
+    end
+
+    it "provides access to hl as one 16-bit register" do
+      register_bit_count(:hl).should eq 16
+    end
+
+    context "#==" do
+      it "is true if all registers are equal" do
+        se = RegisterEnsemble.new
+        @re.should eq se
+      end
+
+      it "is false if a register is different" do
+        se = RegisterEnsemble.new
+        se.d.store(0xAA)
+        @re.should_not eq se
+      end
+    end
+  end
+end

data/spec/gbrb/cpu/register_spec.rb

@@ -0,0 +1,86 @@
+require_relative '../../spec_helper.rb'
+require_relative '../../../lib/gbrb/cpu/register.rb'
+
+module GBRb::CPU
+  describe Register do
+    context "8bit" do
+      let(:r) { Register.new }
+
+      it "returns a value" do
+        r.read.should eq 0x0
+      end
+
+      it "stores a value" do
+        r.store 0xFF
+        r.read.should eq 0xFF
+      end
+
+      it "only stores one byte" do
+        r.store 0x1FD
+        r.read.should eq 0xFD
+      end
+
+      it "has the correct mask value" do
+        r.mask.should eq 0x100
+      end
+
+      it "has the correct half mask value" do
+        r.half_mask.should eq 0x10
+      end
+    end
+
+    context "16bit" do
+      let(:r) { Register.new 0x0, 16 }
+
+      it "stores two bytes" do
+        r.store 0xD
+        r.read.should eq 0xD
+      end
+
+      it "has the correct mask value" do
+        r.mask.should eq 0x10000
+      end
+
+      it "has the correct half mask value" do
+        r.half_mask.should eq 0x100
+      end
+    end
+
+    it "raises an error if invalid bits are specified" do
+      expect {Register.new 0x0, 5}.to raise_error ArgumentError
+    end
+
+    it "clears the bits" do
+      r = Register.new 0x3
+      r.clear
+      r.read.should eq 0x0
+    end
+
+    it "knows if it is zero" do
+      r = Register.new
+      r.zero?.should be_true
+      r.store 0x1
+      r.zero?.should be_false
+    end
+
+    context "#==" do
+      it "is true if both registers have the same value and the same bit count" do
+        r = Register.new
+        s = Register.new
+        r.should eq s
+      end
+
+      it "is false if registers have different values" do
+        r = Register.new 0x05
+        s = Register.new 0xF0
+        r.should_not eq s
+      end
+
+      it "is false if registers have different bit counts" do
+        r = Register.new 0, 8
+        s = Register.new 0, 16
+        r.should_not eq s
+      end
+    end
+  end
+end

data/spec/gbrb/cpu/z80_spec.rb

@@ -0,0 +1,2534 @@
+require_relative '../../spec_helper'
+require_relative '../../../lib/gbrb/cpu/z80'
+
+module GBRb
+  module CPU
+    describe Z80 do
+      context "#clock" do
+        let(:z) { Z80.new }
+        it "has two clock values" do
+          z.clock.keys.should eq %i[m t]
+        end
+      end
+
+      context "#dispatch" do
+        let(:z) { Z80.new }
+        it "updates the accumulated clock" do
+          initial_clock = z.clock.dup
+          z.dispatch z.decode 0x00
+          z.clock.should_not eq initial_clock
+        end
+      end
+
+      context "#instructions" do
+        before(:all) { @z = Z80.new }
+        before(:each) { @z.reset }
+
+        def run op
+          @z.dispatch @z.decode op.to_i
+        end
+
+        it "nop" do
+          initial_registers = Marshal.load Marshal.dump @z.registers
+          run 0x00
+          @z.registers.should eq initial_registers
+        end
+
+        it "rla" do
+          @z.r.a.store 0b10100101
+          run 0x17
+          @z.r.a.read.should eq 0b01001010
+          @z.r.carry_flag?.should be_true
+        end
+
+        it "rlca" do
+          @z.r.a.store 0b10100101
+          @z.r.set_carry_flag
+          run 0x07
+          @z.r.a.read.should eq 0b01001011
+          @z.r.carry_flag?.should be_true
+        end
+
+        it "scf" do
+          @z.r.should_receive(:clear_half_carry_flag)
+          @z.r.should_receive(:clear_add_sub_flag)
+          @z.r.should_receive(:set_carry_flag)
+          run 0x37
+        end
+
+        it "cpl" do
+          @z.r.should_receive(:set_half_carry_flag)
+          @z.r.should_receive(:set_add_sub_flag)
+          run 0x2f
+          @z.r.a.read.should eq 0xFF
+        end
+
+        it "ccf" do
+          @z.r.carry_flag?.should be_false
+          run 0x3f
+          @z.r.carry_flag?.should be_true
+          run 0x3f
+          @z.r.carry_flag?.should be_false
+        end
+
+        context "push and pop (round-trip)" do
+          def common register, push_opcode, pop_opcode
+            value = 0x835b
+            reg = @z.r.public_send(register.to_sym)
+            reg.store value
+            run push_opcode
+            reg.clear
+            reg.read.should eq 0x00
+            run pop_opcode
+            reg.read.should eq value
+          end
+
+          it "push/pop bc" do
+            common :bc, 0xc5, 0xc1
+          end
+
+          it "push/pop de" do
+            common :de, 0xd5, 0xd1
+          end
+
+          it "push/pop hl" do
+            common :hl, 0xe5, 0xe1
+          end
+
+          it "push/pop af" do
+            common :af, 0xf5, 0xf1
+          end
+
+        end
+
+        context "inc" do
+          it "inc_a" do
+            a = @z.r.a.read
+            run 0x3c
+            @z.registers.a.read.should eq a + 1
+          end
+
+          it "inc_b" do
+            b = @z.r.b.read
+            run 0x04
+            @z.registers.b.read.should eq b + 1
+          end
+
+          it "inc_c" do
+            c = @z.r.c.read
+            run 0x0c
+            @z.registers.c.read.should eq c + 1
+          end
+
+          it "inc_d" do
+            d = @z.r.d.read
+            run 0x14
+            @z.registers.d.read.should eq d + 1
+          end
+
+          it "inc_e" do
+            e = @z.r.e.read
+            run 0x1c
+            @z.registers.e.read.should eq e + 1
+          end
+
+          it "inc_h" do
+            h = @z.r.h.read
+            run 0x24
+            @z.registers.h.read.should eq h + 1
+          end
+
+          it "inc_l" do
+            l = @z.r.l.read
+            run 0x2c
+            @z.registers.l.read.should eq l + 1
+          end
+
+          it "inc_bc" do
+            bc = @z.r.bc.read
+            run 0x03
+            @z.registers.bc.read.should eq bc + 1
+          end
+
+          it "inc_de" do
+            de = @z.r.de.read
+            run 0x13
+            @z.registers.de.read.should eq de + 1
+          end
+
+          it "inc_hl" do
+            hl = @z.r.hl.read
+            run 0x23
+            @z.registers.hl.read.should eq hl + 1
+          end
+
+          it "inc_sp" do
+            sp = @z.r.sp.read
+            run 0x33
+            @z.registers.sp.read.should eq (sp + 1)
+          end
+        end
+
+        context "dec" do
+          def common register, opcode
+            r = @z.r.public_send(register.to_sym)
+            v = r.read
+            run opcode
+            r.read.should eq (v - 1) % r.mask
+          end
+
+          it "dec_a" do
+            common :a, 0x3d
+          end
+
+          it "dec_b" do
+            common :b, 0x05
+          end
+
+          it "dec_c" do
+            common :c, 0x0d
+          end
+
+          it "dec_d" do
+            common :d, 0x15
+          end
+
+          it "dec_e" do
+            common :e, 0x1d
+          end
+
+          it "dec_h" do
+            common :h, 0x25
+          end
+
+          it "dec_l" do
+            common :l, 0x2d
+          end
+
+          it "dec_bc" do
+            common :bc, 0x0b
+          end
+
+          it "dec_de" do
+            common :de, 0x1b
+          end
+
+          it "dec_hl" do
+            common :hl, 0x2b
+          end
+
+          it "dec_sp" do
+            common :sp, 0x3b
+          end
+        end
+
+        context "ld" do
+          before(:each) do
+            @z.r.a.store 0x01
+            @z.r.b.store 0x02
+            @z.r.c.store 0x03
+            @z.r.d.store 0x04
+            @z.r.e.store 0x05
+            @z.r.h.store 0x06
+            @z.r.l.store 0x07
+          end
+
+          def common destination, target, opcode
+            v = @z.r.public_send(target.to_sym).read
+            run opcode
+            @z.r.public_send(destination.to_sym).read.should eq v
+          end
+
+          it "ld_b_b" do
+            common :b, :b, 0x40
+          end
+
+          it "ld_b_c" do
+            common :b, :c, 0x41
+          end
+
+          it "ld_b_d" do
+            common :b, :d, 0x42
+          end
+
+          it "ld_b_e" do
+            common :b, :e, 0x43
+          end
+
+          it "ld_b_h" do
+            common :b, :h, 0x44
+          end
+
+          it "ld_b_l" do
+            common :b, :l, 0x45
+          end
+
+          it "ld_b_a" do
+            common :b, :a, 0x47
+          end
+
+          it "ld_c_b" do
+            common :c, :b, 0x48
+          end
+
+          it "ld_c_c" do
+            common :c, :c, 0x49
+          end
+
+          it "ld_c_d" do
+            common :c, :d, 0x4a
+          end
+
+          it "ld_c_e" do
+            common :c, :e, 0x4b
+          end
+
+          it "ld_c_h" do
+            common :c, :h, 0x4c
+          end
+
+          it "ld_c_l" do
+            common :c, :l, 0x4d
+          end
+
+          it "ld_c_a" do
+            common :c, :a, 0x4f
+          end
+
+          it "ld_d_b" do
+            common :d, :b, 0x50
+          end
+
+          it "ld_d_c" do
+            common :d, :c, 0x51
+          end
+
+          it "ld_d_d" do
+            common :d, :d, 0x52
+          end
+
+          it "ld_d_e" do
+            common :d, :e, 0x53
+          end
+
+          it "ld_d_h" do
+            common :d, :h, 0x54
+          end
+
+          it "ld_d_l" do
+            common :d, :l, 0x55
+          end
+
+          it "ld_d_a" do
+            common :d, :a, 0x57
+          end
+
+          it "ld_e_b" do
+            common :e, :b, 0x58
+          end
+
+          it "ld_e_c" do
+            common :e, :c, 0x59
+          end
+
+          it "ld_e_d" do
+            common :e, :d, 0x5a
+          end
+
+          it "ld_e_e" do
+            common :e, :e, 0x5b
+          end
+
+          it "ld_e_h" do
+            common :e, :h, 0x5c
+          end
+
+          it "ld_e_l" do
+            common :e, :l, 0x5d
+          end
+
+          it "ld_e_a" do
+            common :e, :a, 0x5f
+          end
+
+          it "ld_h_b" do
+            common :h, :b, 0x60
+          end
+
+          it "ld_h_c" do
+            common :h, :c, 0x61
+          end
+
+          it "ld_h_d" do
+            common :h, :d, 0x62
+          end
+
+          it "ld_h_e" do
+            common :h, :e, 0x63
+          end
+
+          it "ld_h_h" do
+            common :h, :h, 0x64
+          end
+
+          it "ld_h_l" do
+            common :h, :l, 0x65
+          end
+
+          it "ld_h_a" do
+            common :h, :a, 0x67
+          end
+
+          it "ld_l_b" do
+            common :l, :b, 0x68
+          end
+
+          it "ld_l_c" do
+            common :l, :c, 0x69
+          end
+
+          it "ld_l_d" do
+            common :l, :d, 0x6a
+          end
+
+          it "ld_l_e" do
+            common :l, :e, 0x6b
+          end
+
+          it "ld_l_h" do
+            common :l, :h, 0x6c
+          end
+
+          it "ld_l_l" do
+            common :l, :l, 0x6d
+          end
+
+          it "ld_l_a" do
+            common :l, :a, 0x6f
+          end
+
+          it "ld_a_b" do
+            common :a, :b, 0x78
+          end
+
+          it "ld_a_c" do
+            common :a, :c, 0x79
+          end
+
+          it "ld_a_d" do
+            common :a, :d, 0x7a
+          end
+
+          it "ld_a_e" do
+            common :a, :e, 0x7b
+          end
+
+          it "ld_a_h" do
+            common :a, :h, 0x7c
+          end
+
+          it "ld_a_l" do
+            common :a, :l, 0x7d
+          end
+
+          it "ld_a_a" do
+            common :a, :a, 0x7f
+          end
+
+          it "ld_sp_hl" do
+            common :sp, :hl, 0xf9
+          end
+        end
+
+        context "jr" do
+          it "jr nz r8" do
+            @z.r.pc.store 0x0001
+            @z.mmu.write_byte(0x0001, 0xab)
+            run 0x20
+            @z.r.pc.read.should eq 0xffad
+          end
+
+          it "jr z r8" do
+            @z.r.pc.store 0x0001
+            @z.mmu.write_byte 0x0001, 0x94
+            @z.r.set_zero_flag
+            run 0x28
+            @z.r.pc.read.should eq 0xff96
+          end
+        end
+
+        context "ld (immediate value)" do
+          before(:each) do
+            @z.r.pc.store 0x0003
+            @z.mmu.write_byte(0x0003, 0xcb)
+            @z.mmu.write_byte(0x0004, 0xf1)
+          end
+
+          def common destination, opcode, num_bytes=1, indirect=false
+            run opcode
+            if num_bytes == 1
+              expected = 0xcb
+            else
+              expected = 0xf1cb
+            end
+            result = @z.r.public_send(destination.to_sym).read
+            result = @z.mmu.read_byte result if indirect
+            result.should eq expected
+          end
+
+          it "ld bc d16" do
+            common :bc, 0x01, 2
+          end
+
+          it "ld de d16" do
+            common :de, 0x11, 2
+          end
+
+          it "ld hl d16" do
+            common :hl, 0x21, 2
+          end
+
+          it "ld sp d16" do
+            common :sp, 0x31, 2
+          end
+
+          it "ld b d8" do
+            common :b, 0x06
+          end
+
+          it "ld c d8" do
+            common :c, 0x0e
+          end
+
+          it "ld d d8" do
+            common :d, 0x16
+          end
+
+          it "ld e d8" do
+            common :e, 0x1e
+          end
+
+          it "ld h d8" do
+            common :h, 0x26
+          end
+
+          it "ld l d8" do
+            common :l, 0x2e
+          end
+
+          it "ld (hl) d8" do
+            common :hl, 0x36, 1, true
+          end
+
+          it "ld a d8" do
+            common :a, 0x3e
+          end
+        end
+
+        context "ld (indirect target)" do
+          before(:each) do
+            @z.r.a.store 0x01
+            @z.r.b.store 0x02
+            @z.r.c.store 0x03
+            @z.r.d.store 0x04
+            @z.r.e.store 0x05
+            @z.r.h.store 0x06
+            @z.r.l.store 0x07
+          end
+
+          def common destination, target, opcode
+            @z.r.public_send(target.to_sym).store 0x39
+            @z.mmu.write_byte 0x39, 0xb6
+            run opcode
+            @z.r.public_send(destination.to_sym).read.should eq 0xb6
+          end
+
+          it "ldi_a_bc" do
+            common :a, :bc, 0x0a
+          end
+
+          it "ldi_a_de" do
+            common :a, :de, 0x1a
+          end
+
+          it "ldi_a_hl" do
+            common :a, :hl, 0x7e
+          end
+
+          it "ldi_l_hl" do
+            common :l, :hl, 0x6e
+          end
+
+          it "ldi_e_hl" do
+            common :e, :hl, 0x5e
+          end
+
+          it "ldi_c_hl" do
+            common :c, :hl, 0x4e
+          end
+
+          it "ldi_h_hl" do
+            common :h, :hl, 0x66
+          end
+
+          it "ldi_d_hl" do
+            common :d, :hl, 0x56
+          end
+
+          it "ldi_b_hl" do
+            common :b, :hl, 0x46
+          end
+        end
+
+        context "indirect ld with immediate value" do
+          it "ld (a16) a" do
+            @z.r.a.store 0x4b
+            @z.mmu.write_byte 0x0000, 0xc6
+            @z.mmu.write_byte 0x0001, 0x9b
+            run 0xea
+            @z.mmu.read_byte(0x9bc6).should eq 0x4b
+          end
+
+          it "ld a (a16)" do
+            @z.mmu.write_byte 0x0000, 0xc6
+            @z.mmu.write_byte 0x0001, 0x9b
+            @z.mmu.write_byte 0x9bc6, 0x5e
+            run 0xfa
+            @z.r.a.read.should eq 0x5e
+          end
+        end
+
+        context "indirect inc" do
+          it "inc_i_hl" do
+            address = @z.r.hl.read
+            expected = @z.mmu.read_byte(address) + 1
+            run 0x34
+            @z.mmu.read_byte(address).should eq expected
+          end
+        end
+
+        context "indirect dec" do
+          it "dec_i_hl" do
+            address = @z.r.hl.read
+            expected = @z.mmu.read_byte(address) - 1
+            run 0x35
+            @z.mmu.read_byte(address).should eq expected
+          end
+        end
+
+        context "ld increment" do
+          it "ld hl+ a" do
+            address = @z.r.hl.read
+            run 0x22
+            @z.mmu.read_byte(address).should eq @z.r.a.read
+            @z.r.hl.read.should eq address + 1
+          end
+        end
+
+        context "ld decrement" do
+          it "ld hl- a" do
+            @z.r.hl.store 0x4c
+            address = @z.r.hl.read
+            run 0x32
+            @z.mmu.read_byte(address).should eq @z.r.a.read
+            @z.r.hl.read.should eq address - 1
+          end
+        end
+
+        context "ld (indirect destination)" do
+          before(:each) do
+            @z.reset
+            @z.r.a.store 0x01
+            @z.r.b.store 0x02
+            @z.r.c.store 0x03
+            @z.r.d.store 0x04
+            @z.r.e.store 0x05
+            @z.r.h.store 0x06
+            @z.r.l.store 0x07
+          end
+
+          def common destination, target, opcode
+            expected = @z.r.public_send(target.to_sym).read
+            run opcode
+            @z.mmu.read_byte(@z.r.public_send(destination.to_sym).read).should eq expected
+          end
+
+          it "ldi_bc_a" do
+            common :bc, :a, 0x02
+          end
+
+          it "ldi_de_a" do
+            common :de, :a, 0x12
+          end
+
+          it "ldi_hl_b" do
+            common :hl, :b, 0x70
+          end
+
+          it "ldi_hl_c" do
+            common :hl, :c, 0x71
+          end
+
+          it "ldi_hl_d" do
+            common :hl, :d, 0x72
+          end
+
+          it "ldi_hl_e" do
+            common :hl, :e, 0x73
+          end
+
+          it "ldi_hl_h" do
+            common :hl, :h, 0x74
+          end
+
+          it "ldi_hl_l" do
+            common :hl, :l, 0x75
+          end
+
+          it "ldi_hl_a" do
+            common :hl, :a, 0x77
+          end
+
+          it "ld (c) a" do
+            expected = @z.r.a.read
+            address = @z.r.c.read + 0xff00
+            run 0xe2
+            @z.mmu.read_byte(address).should eq expected
+          end
+
+          it "ld (a8) a" do
+            expected = @z.r.a.read
+            address = 0xff35
+            @z.mmu.write_byte(0x00, address)
+            run 0xe0
+            @z.mmu.read_byte(0xff35).should eq expected
+          end
+        end
+
+        context "call" do
+          it "call a16" do
+            @z.r.pc.store 0x1234
+            @z.mmu.write_byte 0x1234, 0x34
+            @z.mmu.write_byte 0x1235, 0x84
+            run 0xcd
+            @z.r.pc.read.should eq 0x8434
+            @z.mmu.read_byte(@z.r.sp.read).should eq 0x36
+            @z.mmu.read_byte(@z.r.sp.read + 1).should eq 0x12
+          end
+        end
+
+        context "return" do
+          it "ret" do
+            @z.r.pc.store 0x1234
+            @z.mmu.write_byte 0x1234, 0x34
+            @z.mmu.write_byte 0x1235, 0x84
+            run 0xcd
+            run 0xc9
+            @z.r.pc.read.should eq 0x1236
+          end
+        end
+
+        context "add_a" do
+          before(:each) do
+            @z.r.a.store 0xfb
+            @z.r.b.store 0x02
+            @z.r.c.store 0x03
+            @z.r.d.store 0x04
+            @z.r.e.store 0xd5
+            @z.r.h.store 0x06
+            @z.r.l.store 0x07
+          end
+
+          def common destination, target, opcode, mask=0xff
+            v = @z.r.public_send(target.to_sym).read + @z.r.public_send(destination.to_sym).read
+            run opcode
+            @z.r.public_send(destination.to_sym).read.should eq v & mask
+          end
+
+          it "add_a_b" do
+            common :a, :b, 0x80
+          end
+
+          it "add_a_c" do
+            common :a, :c, 0x81
+          end
+
+          it "add_a_d" do
+            common :a, :d, 0x82
+          end
+
+          it "add_a_e" do
+            common :a, :e, 0x83
+          end
+
+          it "add_a_h" do
+            common :a, :h, 0x84
+          end
+
+          it "add_a_l" do
+            common :a, :l, 0x85
+          end
+
+          it "add_a_a" do
+            common :a, :a, 0x87
+          end
+
+          it "add_hl_bc" do
+            common :hl, :bc, 0x09, 0xffff
+          end
+
+          it "add_hl_de" do
+            common :hl, :de, 0x19, 0xffff
+          end
+
+          it "add_hl_hl" do
+            common :hl, :hl, 0x29, 0xffff
+          end
+
+          it "add_hl_sp" do
+            common :hl, :sp, 0x39, 0xffff
+          end
+        end
+
+        context "sub_a" do
+          before(:each) do
+            @z.r.a.store 0xfb
+            @z.r.b.store 0x02
+            @z.r.c.store 0x03
+            @z.r.d.store 0x04
+            @z.r.e.store 0xd5
+            @z.r.h.store 0x06
+            @z.r.l.store 0x07
+          end
+
+          def common target, opcode
+            v = @z.r.a.read - @z.r.public_send(target.to_sym).read
+            run opcode
+            @z.r.a.read.should eq (v & 0xFF)
+          end
+
+          it "sub_a_b" do
+            common :b, 0x90
+          end
+
+          it "sub_a_c" do
+            common :c, 0x91
+          end
+
+          it "sub_a_d" do
+            common :d, 0x92
+          end
+
+          it "sub_a_e" do
+            common :e, 0x93
+          end
+
+          it "sub_a_h" do
+            common :h, 0x94
+          end
+
+          it "sub_a_l" do
+            common :l, 0x95
+          end
+
+          it "sub_a_a" do
+            common :a, 0x97
+          end
+        end
+
+        context "indirect add" do
+          it "add a (hl)" do
+            @z.r.hl.store 0x9e
+            @z.mmu.write_byte(@z.r.hl.read, 0x43)
+            @z.r.a.store  0x8b
+            expected = @z.r.a.read + @z.mmu.read_byte(@z.r.hl.read)
+            run 0x86
+            @z.r.a.read.should eq (expected & 0xff)
+          end
+        end
+
+        context "indirect sub" do
+          it "sub a (hl)" do
+            @z.r.hl.store 0x9e
+            @z.mmu.write_byte(@z.r.hl.read, 0x43)
+            @z.r.a.store  0x8b
+            expected = @z.r.a.read - @z.mmu.read_byte(@z.r.hl.read)
+            run 0x96
+            @z.r.a.read.should eq (expected & 0xff)
+          end
+        end
+
+        context "cp" do
+          before(:each) do
+            @z.r.a.store 0xfb
+            @z.r.b.store 0x02
+            @z.r.c.store 0x03
+            @z.r.d.store 0x04
+            @z.r.e.store 0xd5
+            @z.r.h.store 0x06
+            @z.r.l.store 0x07
+          end
+
+          def common target, opcode
+            v = @z.r.a.read
+            run opcode
+            @z.r.a.read.should eq (v & 0xFF)
+          end
+
+          it "cp_b" do
+            common :b, 0xb8
+          end
+
+          it "cp_c" do
+            common :c, 0xb9
+          end
+
+          it "cp_d" do
+            common :d, 0xba
+          end
+
+          it "cp_e" do
+            common :e, 0xbb
+          end
+
+          it "cp_h" do
+            common :h, 0xbc
+          end
+
+          it "cp_l" do
+            common :l, 0xbd
+          end
+
+          it "cp_a" do
+            common :a, 0xbf
+          end
+
+          it "cp d8" do
+            common nil, 0xfe
+          end
+        end
+
+        context "adc" do
+          before(:each) do
+            @z.r.a.store 0xfb
+            @z.r.b.store 0x02
+            @z.r.c.store 0x03
+            @z.r.d.store 0x04
+            @z.r.e.store 0xd5
+            @z.r.h.store 0x06
+            @z.r.l.store 0x07
+          end
+
+          context "no carrry set" do
+            def common target, opcode
+              v = @z.r.a.read + @z.r.public_send(target.to_sym).read
+              run opcode
+              @z.r.a.read.should eq (v & 0xff)
+            end
+
+            before(:each) { @z.r.clear_carry_flag }
+            it "adc_b" do
+              common :b, 0x88
+            end
+
+            it "adc_c" do
+              common :c, 0x89
+            end
+
+            it "adc_d" do
+              common :d, 0x8a
+            end
+
+            it "adc_e" do
+              common :e, 0x8b
+            end
+
+            it "adc_h" do
+              common :h, 0x8c
+            end
+
+            it "adc_l" do
+              common :l, 0x8d
+            end
+
+            it "adc_a" do
+              common :a, 0x8f
+            end
+          end
+
+          context "carrry set" do
+            def common target, opcode
+              v = @z.r.a.read + @z.r.public_send(target.to_sym).read + 1
+              run opcode
+              @z.r.a.read.should eq (v & 0xff)
+            end
+
+            before(:each) { @z.r.set_carry_flag }
+            it "adc_b" do
+              common :b, 0x88
+            end
+
+            it "adc_c" do
+              common :c, 0x89
+            end
+
+            it "adc_d" do
+              common :d, 0x8a
+            end
+
+            it "adc_e" do
+              common :e, 0x8b
+            end
+
+            it "adc_h" do
+              common :h, 0x8c
+            end
+
+            it "adc_l" do
+              common :l, 0x8d
+            end
+
+            it "adc_a" do
+              common :a, 0x8f
+            end
+          end
+        end
+
+        context "sbc" do
+          before(:each) do
+            @z.r.a.store 0xfb
+            @z.r.b.store 0x02
+            @z.r.c.store 0x03
+            @z.r.d.store 0x04
+            @z.r.e.store 0xd5
+            @z.r.h.store 0x06
+            @z.r.l.store 0x07
+          end
+
+          context "no carrry set" do
+            def common target, opcode
+              v = @z.r.a.read - @z.r.public_send(target.to_sym).read
+              run opcode
+              @z.r.a.read.should eq (v & 0xff)
+            end
+
+            before(:each) { @z.r.clear_carry_flag }
+            it "sbc_b" do
+              common :b, 0x98
+            end
+
+            it "sbc_c" do
+              common :c, 0x99
+            end
+
+            it "sbc_d" do
+              common :d, 0x9a
+            end
+
+            it "sbc_e" do
+              common :e, 0x9b
+            end
+
+            it "sbc_h" do
+              common :h, 0x9c
+            end
+
+            it "sbc_l" do
+              common :l, 0x9d
+            end
+
+            it "sbc_a" do
+              common :a, 0x9f
+            end
+          end
+
+          context "carrry set" do
+            def common target, opcode
+              v = @z.r.a.read - @z.r.public_send(target.to_sym).read - 1
+              run opcode
+              @z.r.a.read.should eq (v & 0xff)
+            end
+
+            before(:each) { @z.r.set_carry_flag }
+            it "sbc_b" do
+              common :b, 0x98
+            end
+
+            it "sbc_c" do
+              common :c, 0x99
+            end
+
+            it "sbc_d" do
+              common :d, 0x9a
+            end
+
+            it "sbc_e" do
+              common :e, 0x9b
+            end
+
+            it "sbc_h" do
+              common :h, 0x9c
+            end
+
+            it "sbc_l" do
+              common :l, 0x9d
+            end
+
+            it "sbc_a" do
+              common :a, 0x9f
+            end
+          end
+        end
+
+
+        context "and" do
+          before(:each) do
+            @z.r.a.store 0xfb
+            @z.r.b.store 0x02
+            @z.r.c.store 0x03
+            @z.r.d.store 0x04
+            @z.r.e.store 0xd5
+            @z.r.h.store 0x06
+            @z.r.l.store 0x07
+          end
+
+          def common target, opcode
+            v = @z.r.public_send(target.to_sym).read & @z.r.a.read
+            run opcode
+            @z.r.a.read.should eq (v & 0xFF)
+          end
+
+          it "and_b" do
+            common :b, 0xa0
+          end
+
+          it "and_c" do
+            common :c, 0xa1
+          end
+
+          it "and_d" do
+            common :d, 0xa2
+          end
+
+          it "and_e" do
+            common :e, 0xa3
+          end
+
+          it "and_h" do
+            common :h, 0xa4
+          end
+
+          it "and_l" do
+            common :l, 0xa5
+          end
+
+          it "and_a" do
+            common :a, 0xa7
+          end
+        end
+
+        context "indirect and" do
+          it "and hl" do
+            @z.r.a.store 0x31
+            @z.r.hl.store 0x77
+            @z.mmu.write_byte(@z.r.hl.read, 0xb7)
+            expected = @z.r.a.read & @z.mmu.read_byte(@z.r.hl.read)
+            run 0xa6
+            @z.r.a.read.should eq expected
+          end
+        end
+
+        context "or" do
+          before(:each) do
+            @z.r.a.store 0xfb
+            @z.r.b.store 0x02
+            @z.r.c.store 0x03
+            @z.r.d.store 0x04
+            @z.r.e.store 0xd5
+            @z.r.h.store 0x06
+            @z.r.l.store 0x07
+          end
+
+          def common target, opcode
+            v = @z.r.public_send(target.to_sym).read | @z.r.a.read
+            run opcode
+            @z.r.a.read.should eq (v & 0xFF)
+          end
+
+          it "or_b" do
+            common :b, 0xb0
+          end
+
+          it "or_c" do
+            common :c, 0xb1
+          end
+
+          it "or_d" do
+            common :d, 0xb2
+          end
+
+          it "or_e" do
+            common :e, 0xb3
+          end
+
+          it "or_h" do
+            common :h, 0xb4
+          end
+
+          it "or_l" do
+            common :l, 0xb5
+          end
+
+          it "or_a" do
+            common :a, 0xb7
+          end
+        end
+
+        context "indirect or" do
+          it "or hl" do
+            @z.r.a.store 0x31
+            @z.r.hl.store 0x77
+            @z.mmu.write_byte(@z.r.hl.read, 0xb7)
+            expected = @z.r.a.read | @z.mmu.read_byte(@z.r.hl.read)
+            run 0xb6
+            @z.r.a.read.should eq expected
+          end
+        end
+
+        context "xor" do
+          before(:each) do
+            @z.r.a.store 0xfb
+            @z.r.b.store 0x02
+            @z.r.c.store 0x03
+            @z.r.d.store 0x04
+            @z.r.e.store 0xd5
+            @z.r.h.store 0x06
+            @z.r.l.store 0x07
+          end
+
+          def common target, opcode
+            v = @z.r.public_send(target.to_sym).read ^ @z.r.a.read
+            run opcode
+            @z.r.a.read.should eq (v & 0xFF)
+          end
+
+          it "xor_b" do
+            common :b, 0xa8
+          end
+
+          it "xor_c" do
+            common :c, 0xa9
+          end
+
+          it "xor_d" do
+            common :d, 0xaa
+          end
+
+          it "xor_e" do
+            common :e, 0xab
+          end
+
+          it "xor_h" do
+            common :h, 0xac
+          end
+
+          it "xor_l" do
+            common :l, 0xad
+          end
+
+          it "xor_a" do
+            common :a, 0xaf
+          end
+        end
+
+        context "indirect xor" do
+          it "xor hl" do
+            @z.r.a.store 0x31
+            @z.r.hl.store 0x77
+            @z.mmu.write_byte(@z.r.hl.read, 0xb7)
+            expected = @z.r.a.read ^ @z.mmu.read_byte(@z.r.hl.read)
+            run 0xae
+            @z.r.a.read.should eq expected
+          end
+        end
+
+        context "rst" do
+          def common opcode, offset
+            original_address = @z.r.pc.read
+            run opcode
+            @z.r.pc.read.should eq offset
+            sp = @z.r.sp.read
+            ((@z.mmu.read_byte(sp) << 4) + @z.mmu.read_byte(sp+1)).should eq original_address
+          end
+
+          it "rst 0x00" do
+            common 0xc7, 0x00
+          end
+
+          it "rst 0x08" do
+            common 0xcf, 0x08
+          end
+
+          it "rst 0x10" do
+            common 0xd7, 0x10
+          end
+
+          it "rst 0x18" do
+            common 0xdf, 0x18
+          end
+
+          it "rst 0x20" do
+            common 0xe7, 0x20
+          end
+
+          it "rst 0x28" do
+            common 0xef, 0x28
+          end
+
+          it "rst 0x30" do
+            common 0xf7, 0x30
+          end
+
+          it "rst 0x38" do
+            common 0xff, 0x38
+          end
+        end
+      end
+
+      context "#cb_instructions" do
+        before(:all) { @z = Z80.new }
+        before(:each) { @z.reset }
+
+        def run op
+          @z.dispatch @z.decode 0xcb
+          @z.dispatch @z.decode op.to_i
+        end
+
+        context "#reset" do
+          def common register, op
+            if register == :hl
+              @z.mmu.write_byte 0x43, 0xff
+              @z.r.hl.store 0x43
+            else
+              @z.r.public_send(register.to_sym).store 0xff
+            end
+            run op
+
+            if register == :hl
+              @z.mmu.read_byte(@z.r.hl.read).should eq @exp
+            else
+              @z.r.public_send(register.to_sym).read.should eq @exp
+            end
+          end
+
+          context "0" do
+            before(:all) { @exp = 0xfe }
+
+            it "res 0 b" do
+              common :b, 0x80
+            end
+
+            it "res 0 c" do
+              common :c, 0x81
+            end
+
+            it "res 0 d" do
+              common :d, 0x82
+            end
+
+            it "res 0 e" do
+              common :e, 0x83
+            end
+
+            it "res 0 h" do
+              common :h, 0x84
+            end
+
+            it "res 0 l" do
+              common :l, 0x85
+            end
+
+            it "res 0 hl" do
+              common :hl, 0x86
+            end
+
+            it "res 0 a" do
+              common :a, 0x87
+            end
+          end
+
+          context "1" do
+            before(:all) { @exp = 0xfd }
+
+            it "res 1 b" do
+              common :b, 0x88
+            end
+
+            it "res 1 c" do
+              common :c, 0x89
+            end
+
+            it "res 1 d" do
+              common :d, 0x8a
+            end
+
+            it "res 1 e" do
+              common :e, 0x8b
+            end
+
+            it "res 1 h" do
+              common :h, 0x8c
+            end
+
+            it "res 1 l" do
+              common :l, 0x8d
+            end
+
+            it "res 1 hl" do
+              common :hl, 0x8e
+            end
+
+            it "res 1 a" do
+              common :a, 0x8f
+            end
+          end
+
+          context "2" do
+            before(:all) { @exp = 0xfb }
+
+            it "res 2 b" do
+              common :b, 0x90
+            end
+
+            it "res 2 c" do
+              common :c, 0x91
+            end
+
+            it "res 2 d" do
+              common :d, 0x92
+            end
+
+            it "res 2 e" do
+              common :e, 0x93
+            end
+
+            it "res 2 h" do
+              common :h, 0x94
+            end
+
+            it "res 2 l" do
+              common :l, 0x95
+            end
+
+            it "res 2 hl" do
+              common :hl, 0x96
+            end
+
+            it "res 2 a" do
+              common :a, 0x97
+            end
+          end
+
+          context "3" do
+            before(:all) { @exp = 0xf7 }
+
+            it "res 3 b" do
+              common :b, 0x98
+            end
+
+            it "res 3 c" do
+              common :c, 0x99
+            end
+
+            it "res 3 d" do
+              common :d, 0x9a
+            end
+
+            it "res 3 e" do
+              common :e, 0x9b
+            end
+
+            it "res 3 h" do
+              common :h, 0x9c
+            end
+
+            it "res 3 l" do
+              common :l, 0x9d
+            end
+
+            it "res 3 hl" do
+              common :hl, 0x9e
+            end
+
+            it "res 3 a" do
+              common :a, 0x9f
+            end
+          end
+
+          context "4" do
+            before(:all) { @exp = 0xef }
+
+            it "res 4 b" do
+              common :b, 0xa0
+            end
+
+            it "res 4 c" do
+              common :c, 0xa1
+            end
+
+            it "res 4 d" do
+              common :d, 0xa2
+            end
+
+            it "res 4 e" do
+              common :e, 0xa3
+            end
+
+            it "res 4 h" do
+              common :h, 0xa4
+            end
+
+            it "res 4 l" do
+              common :l, 0xa5
+            end
+
+            it "res 4 hl" do
+              common :hl, 0xa6
+            end
+
+            it "res 4 a" do
+              common :a, 0xa7
+            end
+          end
+
+          context "5" do
+            before(:all) { @exp = 0xdf }
+
+            it "res 5 b" do
+              common :b, 0xa8
+            end
+
+            it "res 5 c" do
+              common :c, 0xa9
+            end
+
+            it "res 5 d" do
+              common :d, 0xaa
+            end
+
+            it "res 5 e" do
+              common :e, 0xab
+            end
+
+            it "res 5 h" do
+              common :h, 0xac
+            end
+
+            it "res 5 l" do
+              common :l, 0xad
+            end
+
+            it "res 5 hl" do
+              common :hl, 0xae
+            end
+
+            it "res 5 a" do
+              common :a, 0xaf
+            end
+          end
+
+          context "6" do
+            before(:all) { @exp = 0xbf }
+
+            it "res 6 b" do
+              common :b, 0xb0
+            end
+
+            it "res 6 c" do
+              common :c, 0xb1
+            end
+
+            it "res 6 d" do
+              common :d, 0xb2
+            end
+
+            it "res 6 e" do
+              common :e, 0xb3
+            end
+
+            it "res 6 h" do
+              common :h, 0xb4
+            end
+
+            it "res 6 l" do
+              common :l, 0xb5
+            end
+
+            it "res 6 hl" do
+              common :hl, 0xb6
+            end
+
+            it "res 6 a" do
+              common :a, 0xb7
+            end
+          end
+
+          context "7" do
+            before(:all) { @exp = 0x7f }
+
+            it "res 7 b" do
+              common :b, 0xb8
+            end
+
+            it "res 7 c" do
+              common :c, 0xb9
+            end
+
+            it "res 7 d" do
+              common :d, 0xba
+            end
+
+            it "res 7 e" do
+              common :e, 0xbb
+            end
+
+            it "res 7 h" do
+              common :h, 0xbc
+            end
+
+            it "res 7 l" do
+              common :l, 0xbd
+            end
+
+            it "res 7 hl" do
+              common :hl, 0xbe
+            end
+
+            it "res 7 a" do
+              common :a, 0xbf
+            end
+          end
+        end
+        context "#set" do
+          def common register, op
+            if register == :hl
+              @z.mmu.write_byte 0x43, 0x00
+              @z.r.hl.store 0x43
+            else
+              @z.r.public_send(register.to_sym).store 0x00
+            end
+            run op
+
+            if register == :hl
+              @z.mmu.read_byte(@z.r.hl.read).should eq @exp
+            else
+              @z.r.public_send(register.to_sym).read.should eq @exp
+            end
+          end
+
+          context "0" do
+            before(:all) { @exp = 0x01 }
+
+            it "set 0 b" do
+              common :b, 0xc0
+            end
+
+            it "set 0 c" do
+              common :c, 0xc1
+            end
+
+            it "set 0 d" do
+              common :d, 0xc2
+            end
+
+            it "set 0 e" do
+              common :e, 0xc3
+            end
+
+            it "set 0 h" do
+              common :h, 0xc4
+            end
+
+            it "set 0 l" do
+              common :l, 0xc5
+            end
+
+            it "set 0 hl" do
+              common :hl, 0xc6
+            end
+
+            it "set 0 a" do
+              common :a, 0xc7
+            end
+          end
+
+          context "1" do
+            before(:all) { @exp = 0x02 }
+
+            it "set 1 b" do
+              common :b, 0xc8
+            end
+
+            it "set 1 c" do
+              common :c, 0xc9
+            end
+
+            it "set 1 d" do
+              common :d, 0xca
+            end
+
+            it "set 1 e" do
+              common :e, 0xcb
+            end
+
+            it "set 1 h" do
+              common :h, 0xcc
+            end
+
+            it "set 1 l" do
+              common :l, 0xcd
+            end
+
+            it "set 1 hl" do
+              common :hl, 0xce
+            end
+
+            it "set 1 a" do
+              common :a, 0xcf
+            end
+          end
+
+          context "2" do
+            before(:all) { @exp = 0x04 }
+
+            it "set 2 b" do
+              common :b, 0xd0
+            end
+
+            it "set 2 c" do
+              common :c, 0xd1
+            end
+
+            it "set 2 d" do
+              common :d, 0xd2
+            end
+
+            it "set 2 e" do
+              common :e, 0xd3
+            end
+
+            it "set 2 h" do
+              common :h, 0xd4
+            end
+
+            it "set 2 l" do
+              common :l, 0xd5
+            end
+
+            it "set 2 hl" do
+              common :hl, 0xd6
+            end
+
+            it "set 2 a" do
+              common :a, 0xd7
+            end
+          end
+
+          context "3" do
+            before(:all) { @exp = 0x08 }
+
+            it "set 3 b" do
+              common :b, 0xd8
+            end
+
+            it "set 3 c" do
+              common :c, 0xd9
+            end
+
+            it "set 3 d" do
+              common :d, 0xda
+            end
+
+            it "set 3 e" do
+              common :e, 0xdb
+            end
+
+            it "set 3 h" do
+              common :h, 0xdc
+            end
+
+            it "set 3 l" do
+              common :l, 0xdd
+            end
+
+            it "set 3 hl" do
+              common :hl, 0xde
+            end
+
+            it "set 3 a" do
+              common :a, 0xdf
+            end
+          end
+
+          context "4" do
+            before(:all) { @exp = 0x10 }
+
+            it "set 4 b" do
+              common :b, 0xe0
+            end
+
+            it "set 4 c" do
+              common :c, 0xe1
+            end
+
+            it "set 4 d" do
+              common :d, 0xe2
+            end
+
+            it "set 4 e" do
+              common :e, 0xe3
+            end
+
+            it "set 4 h" do
+              common :h, 0xe4
+            end
+
+            it "set 4 l" do
+              common :l, 0xe5
+            end
+
+            it "set 4 hl" do
+              common :hl, 0xe6
+            end
+
+            it "set 4 a" do
+              common :a, 0xe7
+            end
+          end
+
+          context "5" do
+            before(:all) { @exp = 0x20 }
+
+            it "set 5 b" do
+              common :b, 0xe8
+            end
+
+            it "set 5 c" do
+              common :c, 0xe9
+            end
+
+            it "set 5 d" do
+              common :d, 0xea
+            end
+
+            it "set 5 e" do
+              common :e, 0xeb
+            end
+
+            it "set 5 h" do
+              common :h, 0xec
+            end
+
+            it "set 5 l" do
+              common :l, 0xed
+            end
+
+            it "set 5 hl" do
+              common :hl, 0xee
+            end
+
+            it "set 5 a" do
+              common :a, 0xef
+            end
+          end
+
+          context "6" do
+            before(:all) { @exp = 0x40 }
+
+            it "set 6 b" do
+              common :b, 0xf0
+            end
+
+            it "set 6 c" do
+              common :c, 0xf1
+            end
+
+            it "set 6 d" do
+              common :d, 0xf2
+            end
+
+            it "set 6 e" do
+              common :e, 0xf3
+            end
+
+            it "set 6 h" do
+              common :h, 0xf4
+            end
+
+            it "set 6 l" do
+              common :l, 0xf5
+            end
+
+            it "set 6 hl" do
+              common :hl, 0xf6
+            end
+
+            it "set 6 a" do
+              common :a, 0xf7
+            end
+          end
+
+          context "7" do
+            before(:all) { @exp = 0x80 }
+
+            it "set 7 b" do
+              common :b, 0xf8
+            end
+
+            it "set 7 c" do
+              common :c, 0xf9
+            end
+
+            it "set 7 d" do
+              common :d, 0xfa
+            end
+
+            it "set 7 e" do
+              common :e, 0xfb
+            end
+
+            it "set 7 h" do
+              common :h, 0xfc
+            end
+
+            it "set 7 l" do
+              common :l, 0xfd
+            end
+
+            it "set 7 hl" do
+              common :hl, 0xfe
+            end
+
+            it "set 7 a" do
+              common :a, 0xff
+            end
+          end
+        end
+
+        context "#bit" do
+          def common register, op
+            if register == :hl
+              @z.mmu.write_byte 0x43, 0xab
+              @z.r.hl.store 0x43
+            else
+              @z.r.public_send(register.to_sym).store 0xab
+            end
+            run op
+
+            @z.r.zero_flag?.should eq @exp
+          end
+
+          context "0" do
+            before(:all) { @exp = false }
+
+            it "bit 0 b" do
+              common :b, 0x40
+            end
+
+            it "bit 0 c" do
+              common :c, 0x41
+            end
+
+            it "bit 0 d" do
+              common :d, 0x42
+            end
+
+            it "bit 0 e" do
+              common :e, 0x43
+            end
+
+            it "bit 0 h" do
+              common :h, 0x44
+            end
+
+            it "bit 0 l" do
+              common :l, 0x45
+            end
+
+            it "bit 0 hl" do
+              common :hl, 0x46
+            end
+
+            it "bit 0 a" do
+              common :a, 0x47
+            end
+          end
+
+          context "1" do
+            before(:all) { @exp = false }
+
+            it "bit 1 b" do
+              common :b, 0x48
+            end
+
+            it "bit 1 c" do
+              common :c, 0x49
+            end
+
+            it "bit 1 d" do
+              common :d, 0x4a
+            end
+
+            it "bit 1 e" do
+              common :e, 0x4b
+            end
+
+            it "bit 1 h" do
+              common :h, 0x4c
+            end
+
+            it "bit 1 l" do
+              common :l, 0x4d
+            end
+
+            it "bit 1 hl" do
+              common :hl, 0x4e
+            end
+
+            it "bit 1 a" do
+              common :a, 0x4f
+            end
+          end
+
+          context "2" do
+            before(:all) { @exp = true }
+
+            it "bit 2 b" do
+              common :b, 0x50
+            end
+
+            it "bit 2 c" do
+              common :c, 0x51
+            end
+
+            it "bit 2 d" do
+              common :d, 0x52
+            end
+
+            it "bit 2 e" do
+              common :e, 0x53
+            end
+
+            it "bit 2 h" do
+              common :h, 0x54
+            end
+
+            it "bit 2 l" do
+              common :l, 0x55
+            end
+
+            it "bit 2 hl" do
+              common :hl, 0x56
+            end
+
+            it "bit 2 a" do
+              common :a, 0x57
+            end
+          end
+
+          context "3" do
+            before(:all) { @exp = false }
+
+            it "bit 3 b" do
+              common :b, 0x58
+            end
+
+            it "bit 3 c" do
+              common :c, 0x59
+            end
+
+            it "bit 3 d" do
+              common :d, 0x5a
+            end
+
+            it "bit 3 e" do
+              common :e, 0x5b
+            end
+
+            it "bit 3 h" do
+              common :h, 0x5c
+            end
+
+            it "bit 3 l" do
+              common :l, 0x5d
+            end
+
+            it "bit 3 hl" do
+              common :hl, 0x5e
+            end
+
+            it "bit 3 a" do
+              common :a, 0x5f
+            end
+          end
+
+          context "4" do
+            before(:all) { @exp = true }
+
+            it "bit 4 b" do
+              common :b, 0x60
+            end
+
+            it "bit 4 c" do
+              common :c, 0x61
+            end
+
+            it "bit 4 d" do
+              common :d, 0x62
+            end
+
+            it "bit 4 e" do
+              common :e, 0x63
+            end
+
+            it "bit 4 h" do
+              common :h, 0x64
+            end
+
+            it "bit 4 l" do
+              common :l, 0x65
+            end
+
+            it "bit 4 hl" do
+              common :hl, 0x66
+            end
+
+            it "bit 4 a" do
+              common :a, 0x67
+            end
+          end
+
+          context "5" do
+            before(:all) { @exp = false }
+
+            it "bit 5 b" do
+              common :b, 0x68
+            end
+
+            it "bit 5 c" do
+              common :c, 0x69
+            end
+
+            it "bit 5 d" do
+              common :d, 0x6a
+            end
+
+            it "bit 5 e" do
+              common :e, 0x6b
+            end
+
+            it "bit 5 h" do
+              common :h, 0x6c
+            end
+
+            it "bit 5 l" do
+              common :l, 0x6d
+            end
+
+            it "bit 5 hl" do
+              common :hl, 0x6e
+            end
+
+            it "bit 5 a" do
+              common :a, 0x6f
+            end
+          end
+
+          context "6" do
+            before(:all) { @exp = true }
+
+            it "bit 6 b" do
+              common :b, 0x70
+            end
+
+            it "bit 6 c" do
+              common :c, 0x71
+            end
+
+            it "bit 6 d" do
+              common :d, 0x72
+            end
+
+            it "bit 6 e" do
+              common :e, 0x73
+            end
+
+            it "bit 6 h" do
+              common :h, 0x74
+            end
+
+            it "bit 6 l" do
+              common :l, 0x75
+            end
+
+            it "bit 6 hl" do
+              common :hl, 0x76
+            end
+
+            it "bit 6 a" do
+              common :a, 0x77
+            end
+          end
+
+          context "7" do
+            before(:all) { @exp = false }
+
+            it "bit 7 b" do
+              common :b, 0x78
+            end
+
+            it "bit 7 c" do
+              common :c, 0x79
+            end
+
+            it "bit 7 d" do
+              common :d, 0x7a
+            end
+
+            it "bit 7 e" do
+              common :e, 0x7b
+            end
+
+            it "bit 7 h" do
+              common :h, 0x7c
+            end
+
+            it "bit 7 l" do
+              common :l, 0x7d
+            end
+
+            it "bit 7 hl" do
+              common :hl, 0x7e
+            end
+
+            it "bit 7 a" do
+              common :a, 0x7f
+            end
+          end
+        end
+
+        context "rl" do
+          it "rl b" do
+            @z.r.b.store 0b10101010
+            run 0x10
+            @z.r.b.read.should eq 0b01010100
+            @z.r.carry_flag?.should be_true
+          end
+
+          it "rl c" do
+            @z.r.c.store 0b10000000
+            run 0x11
+            @z.r.c.read.should eq 0b00000000
+            @z.r.carry_flag?.should be_true
+            @z.r.zero_flag?.should be_true
+          end
+
+          it "rl d" do
+            @z.r.d.store 0b00000000
+            @z.r.set_carry_flag
+            run 0x12
+            @z.r.d.read.should eq 0b00000001
+            @z.r.carry_flag?.should be_false
+            @z.r.zero_flag?.should be_false
+          end
+
+          it "rl e" do
+            @z.r.e.store 0b10011001
+            @z.r.set_carry_flag
+            run 0x13
+            @z.r.e.read.should eq 0b00110011
+            @z.r.carry_flag?.should be_true
+          end
+
+          it "rl h" do
+            @z.r.h.store 0b11111111
+            run 0x14
+            @z.r.h.read.should eq 0b11111110
+            @z.r.carry_flag?.should be_true
+          end
+
+          it "rl l" do
+            @z.r.l.store 0b01111111
+            @z.r.set_carry_flag
+            run 0x15
+            @z.r.l.read.should eq 0b11111111
+            @z.r.carry_flag?.should be_false
+          end
+
+          it "rl (hl)" do
+            @z.mmu.write_byte 0x1d3b, 0b01010101
+            @z.r.hl.store 0x1d3b
+            run 0x16
+            @z.mmu.read_byte(0x1d3b).should eq 0b10101010
+            @z.r.hl.read.should eq 0x1d3b
+          end
+
+          it "rl a" do
+            @z.r.a.store 0b00100110
+            run 0x17
+            @z.r.a.read.should eq 0b01001100
+            @z.r.carry_flag?.should be_false
+          end
+        end
+
+        context "rlc" do
+          it "rlc b" do
+            @z.r.b.store 0b10101010
+            run 0x00
+            @z.r.b.read.should eq 0b01010101
+            @z.r.carry_flag?.should be_true
+          end
+
+          it "rlc c" do
+            @z.r.c.store 0b10000000
+            run 0x01
+            @z.r.c.read.should eq 0b00000001
+            @z.r.carry_flag?.should be_true
+            @z.r.zero_flag?.should be_false
+          end
+
+          it "rlc d" do
+            @z.r.d.store 0b00000000
+            @z.r.set_carry_flag
+            run 0x02
+            @z.r.d.read.should eq 0b00000000
+            @z.r.carry_flag?.should be_false
+            @z.r.zero_flag?.should be_true
+          end
+
+          it "rlc e" do
+            @z.r.e.store 0b10011001
+            @z.r.set_carry_flag
+            run 0x03
+            @z.r.e.read.should eq 0b00110011
+            @z.r.carry_flag?.should be_true
+          end
+
+          it "rlc h" do
+            @z.r.h.store 0b11111111
+            run 0x04
+            @z.r.h.read.should eq 0b11111111
+            @z.r.carry_flag?.should be_true
+          end
+
+          it "rlc l" do
+            @z.r.l.store 0b01111111
+            @z.r.set_carry_flag
+            run 0x05
+            @z.r.l.read.should eq 0b11111110
+            @z.r.carry_flag?.should be_false
+          end
+
+          it "rlc (hl)" do
+            @z.mmu.write_byte 0x1d3b, 0b01010101
+            @z.r.hl.store 0x1d3b
+            run 0x06
+            @z.mmu.read_byte(0x1d3b).should eq 0b10101010
+            @z.r.carry_flag?.should be_false
+            @z.r.hl.read.should eq 0x1d3b
+          end
+
+          it "rlc a" do
+            @z.r.a.store 0b00100110
+            run 0x07
+            @z.r.a.read.should eq 0b01001100
+            @z.r.carry_flag?.should be_false
+          end
+        end
+
+        context "rr" do
+          it "rr b" do
+            @z.r.b.store 0b10101010
+            run 0x18
+            @z.r.b.read.should eq 0b01010101
+            @z.r.carry_flag?.should be_false
+          end
+
+          it "rr c" do
+            @z.r.c.store 0b10000001
+            run 0x19
+            @z.r.c.read.should eq 0b01000000
+            @z.r.carry_flag?.should be_true
+            @z.r.zero_flag?.should be_false
+          end
+
+          it "rr d" do
+            @z.r.d.store 0b00000000
+            @z.r.set_carry_flag
+            run 0x1a
+            @z.r.d.read.should eq 0b10000000
+            @z.r.carry_flag?.should be_false
+            @z.r.zero_flag?.should be_false
+          end
+
+          it "rr e" do
+            @z.r.e.store 0b10011001
+            @z.r.set_carry_flag
+            run 0x1b
+            @z.r.e.read.should eq 0b11001100
+            @z.r.carry_flag?.should be_true
+          end
+
+          it "rr h" do
+            @z.r.h.store 0b11111111
+            run 0x1c
+            @z.r.h.read.should eq 0b01111111
+            @z.r.carry_flag?.should be_true
+          end
+
+          it "rr l" do
+            @z.r.l.store 0b11111110
+            @z.r.set_carry_flag
+            run 0x1d
+            @z.r.l.read.should eq 0b11111111
+            @z.r.carry_flag?.should be_false
+          end
+
+          it "rr (hl)" do
+            @z.mmu.write_byte 0x1d3b, 0b01010101
+            @z.r.hl.store 0x1d3b
+            run 0x1e
+            @z.mmu.read_byte(0x1d3b).should eq 0b00101010
+            @z.r.hl.read.should eq 0x1d3b
+            @z.r.carry_flag?.should be_true
+          end
+
+          it "rr a" do
+            @z.r.a.store 0b00100110
+            run 0x1f
+            @z.r.a.read.should eq 0b00010011
+            @z.r.carry_flag?.should be_false
+          end
+        end
+
+        context "rrc" do
+          it "rrc b" do
+            @z.r.b.store 0b10101010
+            run 0x08
+            @z.r.b.read.should eq 0b01010101
+            @z.r.carry_flag?.should be_false
+          end
+
+          it "rrc c" do
+            @z.r.c.store 0b00000001
+            run 0x09
+            @z.r.c.read.should eq 0b10000000
+            @z.r.carry_flag?.should be_true
+            @z.r.zero_flag?.should be_false
+          end
+
+          it "rrc d" do
+            @z.r.d.store 0b00000000
+            @z.r.set_carry_flag
+            run 0x0a
+            @z.r.d.read.should eq 0b00000000
+            @z.r.carry_flag?.should be_false
+            @z.r.zero_flag?.should be_true
+          end
+
+          it "rrc e" do
+            @z.r.e.store 0b10011001
+            @z.r.set_carry_flag
+            run 0x0b
+            @z.r.e.read.should eq 0b11001100
+            @z.r.carry_flag?.should be_true
+          end
+
+          it "rrc h" do
+            @z.r.h.store 0b11111111
+            run 0x0c
+            @z.r.h.read.should eq 0b11111111
+            @z.r.carry_flag?.should be_true
+          end
+
+          it "rrc l" do
+            @z.r.l.store 0b11111110
+            @z.r.set_carry_flag
+            run 0x0d
+            @z.r.l.read.should eq 0b01111111
+            @z.r.carry_flag?.should be_false
+          end
+
+          it "rrc (hl)" do
+            @z.mmu.write_byte 0x1d3b, 0b01010101
+            @z.r.hl.store 0x1d3b
+            run 0x0e
+            @z.mmu.read_byte(0x1d3b).should eq 0b10101010
+            @z.r.hl.read.should eq 0x1d3b
+          end
+
+          it "rrc a" do
+            @z.r.a.store 0b00100110
+            run 0x0f
+            @z.r.a.read.should eq 0b0010011
+            @z.r.carry_flag?.should be_false
+          end
+        end
+
+        context "swap" do
+          it "swap b" do
+            @z.r.b.store 0b10101010
+            run 0x30
+            @z.r.b.read.should eq 0b10101010
+          end
+
+          it "swap c" do
+            @z.r.c.store 0b00000000
+            run 0x31
+            @z.r.c.read.should eq 0b00000000
+            @z.r.zero_flag?.should be_true
+          end
+
+          it "swap d" do
+            @z.r.d.store 0b00010000
+            run 0x32
+            @z.r.d.read.should eq 0b00000001
+            @z.r.zero_flag?.should be_false
+          end
+
+          it "swap e" do
+            @z.r.e.store 0b10011011
+            run 0x33
+            @z.r.e.read.should eq 0b10111001
+          end
+
+          it "swap h" do
+            @z.r.h.store 0b01011010
+            run 0x34
+            @z.r.h.read.should eq 0b10100101
+          end
+
+          it "swap l" do
+            @z.r.l.store 0b11111101
+            run 0x35
+            @z.r.l.read.should eq 0b11011111
+          end
+
+          it "swap (hl)" do
+            @z.mmu.write_byte 0x1d3b, 0b01010111
+            @z.r.hl.store 0x1d3b
+            run 0x36
+            @z.mmu.read_byte(0x1d3b).should eq 0b01110101
+            @z.r.hl.read.should eq 0x1d3b
+          end
+
+          it "swap a" do
+            @z.r.a.store 0b00100110
+            run 0x37
+            @z.r.a.read.should eq 0b01100010
+          end
+        end
+      end
+    end
+  end
+end