GBRb 0.1.0
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- checksums.yaml +7 -0
- data/.gitignore +17 -0
- data/.travis.yml +5 -0
- data/Gemfile +4 -0
- data/LICENSE.txt +22 -0
- data/README.md +39 -0
- data/Rakefile +6 -0
- data/bin/display +9 -0
- data/bin/gbrb +12 -0
- data/gbrb.gemspec +26 -0
- data/lib/gbrb.rb +9 -0
- data/lib/gbrb/bios +256 -0
- data/lib/gbrb/cartridge.rb +15 -0
- data/lib/gbrb/cpu.rb +7 -0
- data/lib/gbrb/cpu/concatenated_register.rb +44 -0
- data/lib/gbrb/cpu/flags_register.rb +42 -0
- data/lib/gbrb/cpu/instruction.rb +648 -0
- data/lib/gbrb/cpu/register.rb +44 -0
- data/lib/gbrb/cpu/register_ensemble.rb +59 -0
- data/lib/gbrb/cpu/z80.rb +584 -0
- data/lib/gbrb/gb.rb +125 -0
- data/lib/gbrb/graphics.rb +14 -0
- data/lib/gbrb/graphics/gpu.rb +196 -0
- data/lib/gbrb/graphics/mode_clock.rb +51 -0
- data/lib/gbrb/graphics/screen_client.rb +31 -0
- data/lib/gbrb/graphics/screen_server.rb +90 -0
- data/lib/gbrb/mmu.rb +96 -0
- data/lib/gbrb/version.rb +3 -0
- data/misc/parse_tiles +27 -0
- data/perf/cpu_perf_spec.rb +23 -0
- data/spec/gbrb/cartridge_spec.rb +19 -0
- data/spec/gbrb/cpu/concatenated_register_spec.rb +36 -0
- data/spec/gbrb/cpu/flags_register_spec.rb +91 -0
- data/spec/gbrb/cpu/instruction_spec.rb +283 -0
- data/spec/gbrb/cpu/register_ensemble_spec.rb +84 -0
- data/spec/gbrb/cpu/register_spec.rb +86 -0
- data/spec/gbrb/cpu/z80_spec.rb +2534 -0
- data/spec/gbrb/graphics/mode_clock_spec.rb +82 -0
- data/spec/gbrb/mmu_spec.rb +61 -0
- data/spec/gbrb/version_spec.rb +10 -0
- data/spec/spec_helper.rb +4 -0
- metadata +154 -0
data/lib/gbrb/cpu.rb
ADDED
@@ -0,0 +1,44 @@
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require_relative '../cpu'
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module GBRb::CPU
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class ConcatenatedRegister
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def initialize high, low
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@high = high
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@low = low
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8
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@bits = @high.bits + @low.bits
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end
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10
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def store value
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value &= mask - 1
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@high.store value >> @high.bits
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14
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@low.store value << @low.bits >> @low.bits
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15
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end
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16
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def read
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@low.read + (@high.read << @high.bits)
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19
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end
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20
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21
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def zero?
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22
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@low.zero? && @high.zero?
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23
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end
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24
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def == other
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other.read == read && other.bits == bits
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27
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end
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def mask
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30
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@mask ||= 0x10 ** (@bits/4)
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end
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32
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def half_mask
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@half_mask ||= 0x10 ** (@bits/8)
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end
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def clear
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@high.clear
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@low.clear
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end
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attr_reader :bits
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end
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end
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@@ -0,0 +1,42 @@
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require_relative '../cpu'
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require_relative 'register'
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4
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module GBRb::CPU
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class FlagsRegister < Register
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ZERO_FLAG_POS = 0x80
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7
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ADD_SUB_FLAG_POS = 0x40
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8
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HALF_CARRY_FLAG_POS = 0x20
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CARRY_FLAG_POS = 0x10
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FLAGS = { zero: ZERO_FLAG_POS,
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add_sub: ADD_SUB_FLAG_POS,
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half_carry: HALF_CARRY_FLAG_POS,
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carry: CARRY_FLAG_POS
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}
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FLAGS.each_pair do |flag, position|
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method_name = "#{flag}_flag?".to_sym
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send :define_method, method_name do
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not (@value & position).zero?
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end
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end
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FLAGS.each_pair do |flag, position|
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method_name = "set_#{flag}_flag".to_sym
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send :define_method, method_name do
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store @value | position
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end
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end
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FLAGS.each_pair do |flag, position|
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method_name = "clear_#{flag}_flag".to_sym
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send :define_method, method_name do
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store @value & ~position
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35
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end
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end
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37
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38
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def initialize value=0x0
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39
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super value, 8
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40
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end
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41
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end
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42
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end
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@@ -0,0 +1,648 @@
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require_relative '../cpu'
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module GBRb::CPU
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class Instruction
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attr_reader :i, :m, :t
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def initialize m=1, t=4, immediates=0, *extra
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@m = m
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@t = t
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@immediates = immediates
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11
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end
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12
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def immediate_count
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@immediates
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end
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def call r, mem
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nil
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end
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21
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def carry? left, right, mask
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(mask-1 & left).public_send(@op, mask-1 & right) & mask == mask
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23
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end
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end
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class Stop < Instruction; end
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class Scf < Instruction
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def call r, mem
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r.clear_half_carry_flag
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r.clear_add_sub_flag
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r.set_carry_flag
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end
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end
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class Cpl < Instruction
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def call r, mem
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r.set_add_sub_flag
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r.set_half_carry_flag
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40
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r.a.store r.a.read ^ 0xff
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41
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end
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42
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end
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43
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44
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class Ccf < Instruction
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45
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def call r, mem
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46
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if r.carry_flag?
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47
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r.clear_carry_flag
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else
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49
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r.set_carry_flag
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50
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end
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51
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r.clear_add_sub_flag
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52
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r.clear_half_carry_flag
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53
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end
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54
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end
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55
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56
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class Inc < Instruction
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def initialize register, m=1, t=4, flags=true, indirect=false
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super m, t
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@register = register
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@flags = flags
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@op = :+
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@indirect = indirect
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end
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def call r, mem
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67
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reg = r.public_send(@register.to_sym)
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tmp = reg.read
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if @indirect
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v = mem.read_byte(tmp) + 1
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71
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mem.write_byte(tmp, v)
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72
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else
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reg.store tmp + 1
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end
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if @flags
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r.clear_add_sub_flag
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reg.zero? ? r.set_zero_flag : r.clear_zero_flag
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if carry? tmp, 0x01, reg.half_mask
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79
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r.set_half_carry_flag
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80
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else
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81
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r.clear_half_carry_flag
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82
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end
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83
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end
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84
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end
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85
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end
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86
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87
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class Dec < Instruction
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88
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def initialize register, m=1, t=4, flags=true, indirect=false
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89
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super m, t
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90
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91
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@register = register
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@flags = flags
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93
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@op = :-
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94
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@indirect = indirect
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95
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end
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96
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97
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def call r, mem
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98
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reg = r.public_send(@register.to_sym)
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99
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tmp = reg.read
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100
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if @indirect
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v = mem.read_byte(tmp) - 1
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102
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mem.write_byte(tmp, v)
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103
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else
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104
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reg.store tmp - 0x01
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105
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end
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106
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if @flags
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107
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r.set_add_sub_flag
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108
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if reg.zero?
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r.set_zero_flag
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110
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else
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111
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r.clear_zero_flag
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112
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end
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113
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if carry? tmp, 0x01, reg.half_mask
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114
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r.set_half_carry_flag
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115
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else
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116
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r.clear_half_carry_flag
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117
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end
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118
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end
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119
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end
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end
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121
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|
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class Ld < Instruction
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def initialize destination, target, m=1, t=4, indirect_dest=false, indirect_target=false, immediates=0, offset=0x00
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super m, t, immediates
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125
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126
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@destination = destination
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@target = target
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128
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@indirect_dest = indirect_dest
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@indirect_target = indirect_target
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@offset = offset
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end
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132
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|
133
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def call r, mem, v=nil
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134
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if not v
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135
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v = r.public_send(@target.to_sym).read
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136
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end
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137
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|
138
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if @indirect_target
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139
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v = mem.read_byte(v + @offset)
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140
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target_reg = r.public_send(@destination.to_sym)
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141
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if @indirect_target == :increment
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142
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target_reg.store target_reg.read + 1
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143
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elsif @indirect_target == :decrement
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144
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target_reg.store target_reg.read - 1
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145
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end
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146
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end
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147
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+
|
148
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+
|
149
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if @indirect_dest
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150
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if @indirect_dest == :immediate
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151
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if @target.to_s.chars.length == 2
|
152
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mem.write_word(v + @offset, r.public_send(@target.to_sym).read)
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153
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else
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154
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mem.write_byte(v + @offset, r.public_send(@target.to_sym).read)
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155
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end
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156
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else
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157
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reg = r.public_send(@destination.to_sym)
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158
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mem.write_byte(reg.read + @offset, v)
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159
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if @indirect_dest == :increment
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160
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reg.store reg.read + 1
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161
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elsif @indirect_dest == :decrement
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162
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reg.store reg.read - 1
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163
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end
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164
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end
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165
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else
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166
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r.public_send(@destination.to_sym).store v
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167
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end
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168
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end
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169
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end
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170
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|
171
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class Ldh < Ld
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172
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def call r, mem, address
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173
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if @indirect_dest
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174
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value = r.public_send(@target.to_sym).read
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175
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mem.write_byte address + @offset, value
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176
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elsif @indirect_target
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177
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value = mem.read_byte address + @offset
|
178
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r.public_send(@destination.to_sym).store value
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179
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end
|
180
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end
|
181
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end
|
182
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+
|
183
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class Ldhlsp < Instruction
|
184
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def initialize m=2, t=12, immediates=1
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185
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super
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186
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@op = :+
|
187
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end
|
188
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+
|
189
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def call r, mem, offset
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190
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sign = (offset >> 7 == 1) ? :- : :+
|
191
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offset = ((offset ^ 0xff) + 1) & 0xff
|
192
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value = r.sp.read.public_send(sign, offset)
|
193
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r.hl.store value
|
194
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r.clear_zero_flag
|
195
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r.clear_add_sub_flag
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196
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carry?(value, 0x00, r.hl.mask) ? r.set_carry_flag : r.clear_carry_flag
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197
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carry?(value, 0x00, r.hl.half_mask) ? r.set_half_carry_flag : r.clear_half_carry_flag
|
198
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end
|
199
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+
end
|
200
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+
|
201
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class Jump < Instruction
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202
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def initialize condition, m=2, t_high=12, t_low=8, immediates=1
|
203
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super m, t_low, immediates
|
204
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@t_high = t_high
|
205
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@condition = condition.downcase.to_sym
|
206
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+
end
|
207
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+
|
208
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def call r, mem, offset
|
209
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do_it = case @condition
|
210
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when :c
|
211
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r.carry_flag?
|
212
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when :none
|
213
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true
|
214
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when :nc
|
215
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not r.carry_flag?
|
216
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when :nz
|
217
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not r.zero_flag?
|
218
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when :z
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219
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r.zero_flag?
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220
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else
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221
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false
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222
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end
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223
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+
|
224
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if do_it
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225
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@t = @t_high
|
226
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if @immediates == 1
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227
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sign = (offset >> 7 == 1) ? :- : :+
|
228
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offset = ((offset ^ 0xff) + 1) & 0xff if sign == :-
|
229
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r.pc.store r.pc.read.public_send(sign, offset)
|
230
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else
|
231
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r.pc.store offset
|
232
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+
end
|
233
|
+
end
|
234
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+
end
|
235
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+
end
|
236
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+
|
237
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class Rl < Instruction
|
238
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+
def initialize target, carry=false, indirect=false, m=2, t=8
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239
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super m, t
|
240
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@target = target.to_sym
|
241
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@carry = carry
|
242
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@indirect = indirect
|
243
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+
end
|
244
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+
|
245
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def call r, mem
|
246
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+
if @indirect
|
247
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address = r.public_send(@target).read
|
248
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v = mem.read_byte(address) << 1
|
249
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else
|
250
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v = r.public_send(@target).read << 1
|
251
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+
end
|
252
|
+
|
253
|
+
carry_in = if @carry
|
254
|
+
v & 0x100 == 0x100 ? 1 : 0
|
255
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+
else
|
256
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+
r.carry_flag? ? 1 : 0
|
257
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+
end
|
258
|
+
|
259
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+
v += carry_in
|
260
|
+
|
261
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+
if @indirect
|
262
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+
mem.write_byte(address, v)
|
263
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+
else
|
264
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+
r.public_send(@target).store v
|
265
|
+
end
|
266
|
+
|
267
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+
r.clear_add_sub_flag
|
268
|
+
r.clear_half_carry_flag
|
269
|
+
v & 0xff == 0 ? r.set_zero_flag : r.clear_zero_flag
|
270
|
+
carry_out = v >> 8
|
271
|
+
carry_out == 1 ? r.set_carry_flag : r.clear_carry_flag
|
272
|
+
end
|
273
|
+
end
|
274
|
+
|
275
|
+
class Rr < Instruction
|
276
|
+
def initialize target, carry=false, indirect=false, m=2, t=8
|
277
|
+
super m, t
|
278
|
+
@target = target.to_sym
|
279
|
+
@carry = carry
|
280
|
+
@indirect = indirect
|
281
|
+
end
|
282
|
+
|
283
|
+
def call r, mem
|
284
|
+
if @indirect
|
285
|
+
address = r.public_send(@target).read
|
286
|
+
v = mem.read_byte(address)
|
287
|
+
else
|
288
|
+
v = r.public_send(@target).read
|
289
|
+
end
|
290
|
+
|
291
|
+
carry_out = v & 0x01
|
292
|
+
|
293
|
+
carry_in = if @carry
|
294
|
+
carry_out
|
295
|
+
else
|
296
|
+
r.carry_flag? ? 1 : 0
|
297
|
+
end
|
298
|
+
|
299
|
+
v >>= 1
|
300
|
+
|
301
|
+
v += carry_in << 7
|
302
|
+
|
303
|
+
if @indirect
|
304
|
+
original = mem.read_byte address
|
305
|
+
mem.write_byte(address, v)
|
306
|
+
else
|
307
|
+
r.public_send(@target).store v
|
308
|
+
end
|
309
|
+
|
310
|
+
r.clear_add_sub_flag
|
311
|
+
r.clear_half_carry_flag
|
312
|
+
v & 0xff == 0 ? r.set_zero_flag : r.clear_zero_flag
|
313
|
+
carry_out == 1 ? r.set_carry_flag : r.clear_carry_flag
|
314
|
+
end
|
315
|
+
end
|
316
|
+
|
317
|
+
class Swap < Instruction
|
318
|
+
def initialize target, m=2, t=8, indirect=false
|
319
|
+
@target = target
|
320
|
+
@indirect = indirect
|
321
|
+
super m, t
|
322
|
+
end
|
323
|
+
|
324
|
+
def call r, mem
|
325
|
+
initial = r.public_send(@target).read
|
326
|
+
initial = mem.read_byte(initial) if @indirect
|
327
|
+
high = initial >> 4
|
328
|
+
low = initial & ((1 << 4) - 1)
|
329
|
+
|
330
|
+
result = (low << 4) + high
|
331
|
+
|
332
|
+
if @indirect
|
333
|
+
mem.write_byte r.public_send(@target).read, result
|
334
|
+
mem.read_byte(r.public_send(@target).read) == 0 ? r.set_zero_flag : r.clear_zero_flag
|
335
|
+
else
|
336
|
+
r.public_send(@target).store result
|
337
|
+
r.public_send(@target).read == 0 ? r.set_zero_flag : r.clear_zero_flag
|
338
|
+
end
|
339
|
+
r.clear_add_sub_flag
|
340
|
+
r.clear_half_carry_flag
|
341
|
+
r.clear_carry_flag
|
342
|
+
end
|
343
|
+
end
|
344
|
+
|
345
|
+
class Arithmetic < Instruction
|
346
|
+
def initialize target, m, t, indirect, immediates=0
|
347
|
+
super m, t, immediates
|
348
|
+
@target = target
|
349
|
+
@indirect = indirect
|
350
|
+
end
|
351
|
+
|
352
|
+
def carry? left, right, mask
|
353
|
+
(mask-1 & left).public_send(@op, mask-1 & right) & mask == mask
|
354
|
+
end
|
355
|
+
|
356
|
+
def call r, mem, right_value
|
357
|
+
right_value ||= r.public_send(@target.to_sym).read
|
358
|
+
right_value = mem.read_byte(right_value) if @indirect
|
359
|
+
a_value = r.a.read
|
360
|
+
if carry? a_value, right_value, r.a.half_mask
|
361
|
+
r.set_half_carry_flag
|
362
|
+
else
|
363
|
+
r.clear_half_carry_flag
|
364
|
+
end
|
365
|
+
if carry? a_value, right_value, r.a.mask
|
366
|
+
r.set_carry_flag
|
367
|
+
else
|
368
|
+
r.clear_carry_flag
|
369
|
+
end
|
370
|
+
a_value = a_value.public_send(@op, right_value) & 0xff
|
371
|
+
r.a.store a_value unless @skip_store
|
372
|
+
a_value == 0x00 ? r.set_zero_flag : r.clear_zero_flag
|
373
|
+
end
|
374
|
+
end
|
375
|
+
|
376
|
+
class Add < Arithmetic
|
377
|
+
def initialize target, m=1, t=4, indirect=false, immediates=0
|
378
|
+
super
|
379
|
+
@op = :+
|
380
|
+
end
|
381
|
+
|
382
|
+
def call r, mem, right_value=nil
|
383
|
+
super
|
384
|
+
r.clear_add_sub_flag
|
385
|
+
end
|
386
|
+
end
|
387
|
+
|
388
|
+
class AddHl < Instruction
|
389
|
+
def initialize target, m=1, t=8
|
390
|
+
super m, t
|
391
|
+
@target = target.to_sym
|
392
|
+
@op = :+
|
393
|
+
end
|
394
|
+
|
395
|
+
def call r, mem
|
396
|
+
left = r.hl.read
|
397
|
+
right = r.public_send(@target).read
|
398
|
+
r.hl.store left + right
|
399
|
+
r.set_carry_flag if carry? left, right, r.hl.mask
|
400
|
+
r.set_half_carry_flag if carry? left, right, r.hl.half_mask
|
401
|
+
end
|
402
|
+
end
|
403
|
+
|
404
|
+
class Sub < Arithmetic
|
405
|
+
def initialize target, m=1, t=4, indirect=false, immediates=0
|
406
|
+
super
|
407
|
+
@op = :-
|
408
|
+
end
|
409
|
+
|
410
|
+
def call r, mem, right_value=nil
|
411
|
+
super
|
412
|
+
r.set_add_sub_flag
|
413
|
+
end
|
414
|
+
end
|
415
|
+
|
416
|
+
class Cp < Sub
|
417
|
+
def initialize *args
|
418
|
+
super
|
419
|
+
@skip_store = true
|
420
|
+
end
|
421
|
+
end
|
422
|
+
|
423
|
+
class Adc < Add
|
424
|
+
def call r, mem, right_value=nil
|
425
|
+
carry = r.carry_flag? ? 1 : 0
|
426
|
+
super r, mem, r.public_send(@target.to_sym).read + carry
|
427
|
+
end
|
428
|
+
end
|
429
|
+
|
430
|
+
class Sbc < Sub
|
431
|
+
def call r, mem, right_value=nil
|
432
|
+
carry = r.carry_flag? ? 1 : 0
|
433
|
+
super r, mem, r.public_send(@target.to_sym).read + carry
|
434
|
+
end
|
435
|
+
end
|
436
|
+
|
437
|
+
class Boolean < Instruction
|
438
|
+
def initialize target, m, t, indirect, immediates=0
|
439
|
+
@target = target
|
440
|
+
@indirect = indirect
|
441
|
+
super m, t, immediates
|
442
|
+
end
|
443
|
+
|
444
|
+
def call r, mem, v=nil
|
445
|
+
if v
|
446
|
+
value = v
|
447
|
+
else
|
448
|
+
value = r.public_send(@target.to_sym).read
|
449
|
+
value = mem.read_byte value if @indirect
|
450
|
+
end
|
451
|
+
r.a.store r.a.read.public_send(@op, value)
|
452
|
+
r.a.zero? ? r.set_zero_flag : r.clear_zero_flag
|
453
|
+
r.clear_carry_flag
|
454
|
+
r.clear_add_sub_flag
|
455
|
+
end
|
456
|
+
end
|
457
|
+
|
458
|
+
class And < Boolean
|
459
|
+
def initialize target, m=1, t=4, indirect=false, immediates=0
|
460
|
+
@op = :&
|
461
|
+
super
|
462
|
+
end
|
463
|
+
|
464
|
+
def call r, mem, v=nil
|
465
|
+
super
|
466
|
+
r.set_half_carry_flag
|
467
|
+
end
|
468
|
+
end
|
469
|
+
|
470
|
+
class Or < Boolean
|
471
|
+
def initialize target, m=1, t=4, indirect=false
|
472
|
+
@op = :|
|
473
|
+
super
|
474
|
+
end
|
475
|
+
|
476
|
+
def call r, mem
|
477
|
+
super
|
478
|
+
r.clear_half_carry_flag
|
479
|
+
end
|
480
|
+
end
|
481
|
+
|
482
|
+
class Xor < Boolean
|
483
|
+
def initialize target, m=1, t=4, indirect=false, immediates=0
|
484
|
+
@op = :^
|
485
|
+
super
|
486
|
+
end
|
487
|
+
|
488
|
+
def call r, mem, right_value=nil
|
489
|
+
super
|
490
|
+
r.clear_half_carry_flag
|
491
|
+
end
|
492
|
+
end
|
493
|
+
|
494
|
+
class Pop < Instruction
|
495
|
+
def initialize target, m=1, t=12
|
496
|
+
super m, t
|
497
|
+
@targets = target.to_s.chars.map{|a| a.to_sym}.reverse
|
498
|
+
end
|
499
|
+
|
500
|
+
def call r, mem
|
501
|
+
@targets.each do |target|
|
502
|
+
r.public_send(target).store mem.read_byte(r.sp.read)
|
503
|
+
r.sp.store r.sp.read + 1
|
504
|
+
end
|
505
|
+
end
|
506
|
+
end
|
507
|
+
|
508
|
+
class Push < Instruction
|
509
|
+
def initialize target, m=1, t=16
|
510
|
+
super m, t
|
511
|
+
@targets = target.to_s.chars.map{|a| a.to_sym}
|
512
|
+
end
|
513
|
+
|
514
|
+
def call r, mem
|
515
|
+
@targets.each do |target|
|
516
|
+
r.sp.store r.sp.read - 1
|
517
|
+
mem.write_byte(r.sp.read, r.public_send(target).read)
|
518
|
+
end
|
519
|
+
end
|
520
|
+
end
|
521
|
+
|
522
|
+
class Rst < Instruction
|
523
|
+
def initialize offset
|
524
|
+
@offset = offset
|
525
|
+
super 1, 16
|
526
|
+
end
|
527
|
+
|
528
|
+
def call r, mem
|
529
|
+
r.sp.store r.sp.read - 2
|
530
|
+
mem.write_word r.sp.read, r.pc.read
|
531
|
+
r.pc.store 0x0000 + @offset
|
532
|
+
end
|
533
|
+
end
|
534
|
+
|
535
|
+
class Call < Instruction
|
536
|
+
def initialize m=3, t=24, immediates=2, condition=:none
|
537
|
+
@condition = condition
|
538
|
+
super
|
539
|
+
end
|
540
|
+
|
541
|
+
def call r, mem, addr
|
542
|
+
condition_met = case @condition
|
543
|
+
when :Z
|
544
|
+
r.zero_flag?
|
545
|
+
when :none
|
546
|
+
true
|
547
|
+
else
|
548
|
+
false
|
549
|
+
end
|
550
|
+
if condition_met
|
551
|
+
r.sp.store r.sp.read - 2
|
552
|
+
mem.write_word(r.sp.read, r.pc.read)
|
553
|
+
r.pc.store addr
|
554
|
+
end
|
555
|
+
end
|
556
|
+
end
|
557
|
+
|
558
|
+
class Ret < Instruction
|
559
|
+
def initialize m=1, t=16, t_high=16, condition=:none
|
560
|
+
@condition = condition
|
561
|
+
@t_high = t_high
|
562
|
+
super m, t, 0
|
563
|
+
end
|
564
|
+
|
565
|
+
def call r, mem
|
566
|
+
condition_met = case @condition
|
567
|
+
when :NZ
|
568
|
+
not r.zero_flag?
|
569
|
+
when :none
|
570
|
+
true
|
571
|
+
else
|
572
|
+
false
|
573
|
+
end
|
574
|
+
if condition_met
|
575
|
+
@t = @t_high
|
576
|
+
low = mem.read_byte(r.sp.read)
|
577
|
+
r.sp.store r.sp.read + 1
|
578
|
+
high = mem.read_byte(r.sp.read)
|
579
|
+
r.sp.store r.sp.read + 1
|
580
|
+
|
581
|
+
r.pc.store (high << 8) + low
|
582
|
+
end
|
583
|
+
end
|
584
|
+
end
|
585
|
+
|
586
|
+
class EnableInterrupts < Instruction; end
|
587
|
+
class DisableInterrupts < Instruction; end
|
588
|
+
|
589
|
+
class Res < Instruction
|
590
|
+
def initialize bit, target, indirect=false, m=2, t=16
|
591
|
+
super m, t
|
592
|
+
@bit = bit
|
593
|
+
@mask = 0xff - 0b10 ** bit
|
594
|
+
@target = target.to_sym
|
595
|
+
@indirect = indirect
|
596
|
+
end
|
597
|
+
|
598
|
+
def call r, mem
|
599
|
+
if @indirect
|
600
|
+
addr = r.public_send(@target).read
|
601
|
+
mem.write_byte(addr, mem.read_byte(addr) & @mask)
|
602
|
+
else
|
603
|
+
r.public_send(@target).store r.public_send(@target).read & @mask
|
604
|
+
end
|
605
|
+
end
|
606
|
+
end
|
607
|
+
|
608
|
+
class Set < Instruction
|
609
|
+
def initialize bit, target, indirect=false, m=2, t=16
|
610
|
+
super m, t
|
611
|
+
@bit = bit
|
612
|
+
@mask = 0b10 ** bit
|
613
|
+
@target = target.to_sym
|
614
|
+
@indirect = indirect
|
615
|
+
end
|
616
|
+
|
617
|
+
def call r, mem
|
618
|
+
if @indirect
|
619
|
+
addr = r.public_send(@target).read
|
620
|
+
mem.write_byte(addr, mem.read_byte(addr) | @mask)
|
621
|
+
else
|
622
|
+
r.public_send(@target).store r.public_send(@target).read | @mask
|
623
|
+
end
|
624
|
+
end
|
625
|
+
end
|
626
|
+
|
627
|
+
class Bit < Instruction
|
628
|
+
def initialize bit, target, indirect=false, m=2, t=8
|
629
|
+
super m,t
|
630
|
+
@target = target
|
631
|
+
@bit = bit
|
632
|
+
@indirect = indirect
|
633
|
+
@mask = 1 << @bit
|
634
|
+
end
|
635
|
+
|
636
|
+
def call r, mem
|
637
|
+
if @indirect
|
638
|
+
v = mem.read_byte r.public_send(@target).read
|
639
|
+
else
|
640
|
+
v = r.public_send(@target).read
|
641
|
+
end
|
642
|
+
|
643
|
+
v & @mask != @mask ? r.set_zero_flag : r.clear_zero_flag
|
644
|
+
r.set_half_carry_flag
|
645
|
+
r.clear_add_sub_flag
|
646
|
+
end
|
647
|
+
end
|
648
|
+
end
|