BOAST 1.0.7 → 1.0.8
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- checksums.yaml +4 -4
- data/BOAST.gemspec +2 -1
- data/lib/BOAST/Language/Algorithm.rb +33 -28
- data/lib/BOAST/Language/Architectures.rb +210 -0
- data/lib/BOAST/Language/CPUID_by_name.rb +5675 -0
- data/lib/BOAST/Language/DataTypes.rb +24 -85
- data/lib/BOAST/Language/Index.rb +12 -0
- data/lib/BOAST/Language/Inspectable.rb +1 -1
- data/lib/BOAST/Language/Intrinsics.rb +148 -10
- data/lib/BOAST/Language/Operators.rb +376 -136
- data/lib/BOAST/Language/Procedure.rb +1 -1
- data/lib/BOAST/Language/State.rb +14 -0
- data/lib/BOAST/Language/Transitions.rb +1 -1
- data/lib/BOAST/Language/Variable.rb +81 -31
- data/lib/BOAST/Runtime/CKernel.rb +6 -2
- data/lib/BOAST/Runtime/CRuntime.rb +1 -0
- data/lib/BOAST/Runtime/CompiledRuntime.rb +9 -12
- data/lib/BOAST/Runtime/Compilers.rb +3 -0
- data/lib/BOAST/Runtime/Config.rb +5 -7
- data/lib/BOAST/Runtime/FORTRANRuntime.rb +19 -11
- data/lib/BOAST/Runtime/MAQAO.rb +10 -3
- data/lib/BOAST.rb +2 -0
- metadata +24 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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1
1
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---
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2
2
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SHA1:
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3
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-
metadata.gz:
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4
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-
data.tar.gz:
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3
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+
metadata.gz: bc45ecb1aebfa764bd9f502b867b26fc817a0b76
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4
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+
data.tar.gz: 2033f7f6c650a7de70b801d1751f34d47f1ff085
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5
5
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SHA512:
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6
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-
metadata.gz:
|
7
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-
data.tar.gz:
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6
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+
metadata.gz: e653262ee7e2b165e7c44f86a5c9209a58f7b9892b7844ce0e0846e8086f9354fc559b97aafdf03a93c309d4a24809726f78872d63d8cdca505273d0efeca54d
|
7
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+
data.tar.gz: 09b6fce380eb9daa8090d1d1c2509bda205854ebffbb24a340fe0276c57372fff1e87df67d879213d275a098f0bf787ba9e85891eed0c6bf37dde4a5036eb8ce
|
data/BOAST.gemspec
CHANGED
@@ -1,6 +1,6 @@
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1
1
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Gem::Specification.new do |s|
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2
2
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s.name = 'BOAST'
|
3
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-
s.version = "1.0.
|
3
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+
s.version = "1.0.8"
|
4
4
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s.author = "Brice Videau"
|
5
5
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s.email = "brice.videau@imag.fr"
|
6
6
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s.homepage = "https://github.com/Nanosim-LIG/boast"
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@@ -17,5 +17,6 @@ Gem::Specification.new do |s|
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|
17
17
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s.add_dependency 'os', '~> 0.9', '>=0.9.6'
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18
18
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s.add_dependency 'PAPI', '~> 0', '>=0.101'
|
19
19
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s.add_dependency 'ffi', '~> 1.9', '>=1.9.3'
|
20
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+
s.add_dependency 'rgl', '~> 0.5', '>=0.5.1'
|
20
21
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s.add_dependency 'rake', '>=0.9'
|
21
22
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end
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@@ -12,7 +12,7 @@ module BOAST
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12
12
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13
13
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module PrivateStateAccessor
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14
14
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15
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-
private_state_accessor :output, :lang, :architecture
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15
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+
private_state_accessor :output, :lang, :architecture, :model, :address_size
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16
16
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private_state_accessor :default_int_size, :default_real_size
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17
17
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private_state_accessor :default_align
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18
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private_state_accessor :array_start
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@@ -48,7 +48,7 @@ module BOAST
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48
48
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49
49
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end
|
50
50
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|
51
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-
state_accessor :output, :lang, :architecture
|
51
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+
state_accessor :output, :lang, :architecture, :model, :address_size
|
52
52
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state_accessor :default_int_size, :default_real_size
|
53
53
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state_accessor :default_align
|
54
54
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state_accessor :array_start
|
@@ -61,40 +61,45 @@ module BOAST
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61
61
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boolean_state_accessor :use_vla
|
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boolean_state_accessor :decl_module
|
63
63
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-
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65
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-
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66
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-
|
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-
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-
|
69
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-
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64
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+
default_state_getter :address_size, OS.bits/8
|
65
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+
default_state_getter :lang, FORTRAN, '"const_get(#{envs})"', :BOAST_LANG
|
66
|
+
default_state_getter :model, "native"
|
67
|
+
default_state_getter :debug, false
|
68
|
+
default_state_getter :use_vla, false
|
69
|
+
default_state_getter :replace_constants, true
|
70
|
+
default_state_getter :default_int_signed, true
|
71
|
+
default_state_getter :default_int_size, 4
|
72
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+
default_state_getter :default_real_size, 8
|
73
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+
default_state_getter :default_align, 1
|
74
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+
default_state_getter :indent_level, 0
|
75
|
+
default_state_getter :indent_increment, 2
|
76
|
+
default_state_getter :array_start, 1
|
77
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+
|
78
|
+
alias use_vla_old? use_vla?
|
79
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+
class << self
|
80
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+
alias use_vla_old? use_vla?
|
70
81
|
end
|
71
82
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|
72
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-
def
|
73
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-
|
74
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-
|
75
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-
return debug
|
83
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+
def use_vla?
|
84
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+
return false if [CL,CUDA].include?(lang)
|
85
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+
return use_vla_old?
|
76
86
|
end
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87
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|
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-
|
79
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-
|
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-
|
81
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-
|
88
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+
module_function :use_vla?
|
89
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+
|
90
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+
module_function
|
91
|
+
|
92
|
+
def get_default_architecture
|
93
|
+
architecture = const_get(ENV["ARCHITECTURE"]) if ENV["ARCHITECTURE"]
|
94
|
+
architecture = const_get(ENV["ARCH"]) if not architecture and ENV["ARCH"]
|
95
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+
return architecture if architecture
|
96
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+
return ARM if YAML::load( OS.report )["host_cpu"].match("arm")
|
97
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+
return X86
|
82
98
|
end
|
83
99
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|
84
100
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@@output = STDOUT
|
85
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-
@@lang = get_default_lang
|
86
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-
@@replace_constants = true
|
87
|
-
@@default_int_size = 4
|
88
|
-
@@default_int_signed = true
|
89
|
-
@@default_real_size = 8
|
90
|
-
@@default_align = 1
|
91
|
-
@@indent_level = 0
|
92
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-
@@indent_increment = 2
|
93
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-
@@array_start = 1
|
94
101
|
@@chain_code = false
|
95
|
-
@@architecture =
|
96
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-
@@debug = get_default_debug
|
97
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-
@@use_vla = get_default_use_vla
|
102
|
+
@@architecture = get_default_architecture
|
98
103
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@@decl_module = false
|
99
104
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|
100
105
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@@env = Hash::new{|h, k| h[k] = []}
|
@@ -0,0 +1,210 @@
|
|
1
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+
module BOAST
|
2
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+
X86architectures ={"pentium2"=>["MMX"],
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3
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+
"pentium3"=>["MMX", "SSE"],
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4
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+
"pentium3m"=>["MMX", "SSE"],
|
5
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+
"pentium-m"=>["MMX", "SSE", "SSE2"],
|
6
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+
"pentium4"=>["MMX", "SSE", "SSE2"],
|
7
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+
"pentium4m"=>["MMX", "SSE", "SSE2"],
|
8
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+
"prescott"=>["MMX", "SSE", "SSE2", "SSE3"],
|
9
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+
"nocona"=>["MMX", "SSE", "SSE2", "SSE3"],
|
10
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+
"core2"=>["MMX", "SSE", "SSE2", "SSE3", "SSSE3"],
|
11
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+
"nehalem"=>
|
12
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["MMX", "SSE", "SSE2", "SSE3", "SSSE3", "SSE4.1", "SSE4.2", "POPCNT"],
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13
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+
"westmere"=>
|
14
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+
["MMX",
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"SSE",
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"SSE2",
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"SSE3",
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"SSSE3",
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"SSE4.1",
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20
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"SSE4.2",
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"POPCNT",
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"AES",
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23
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+
"PCLMUL"],
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24
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+
"sandybridge"=>
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["MMX",
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"SSE",
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"SSE2",
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"SSE3",
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"SSSE3",
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"SSE4.1",
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"SSE4.2",
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+
"POPCNT",
|
33
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+
"AVX",
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"AES",
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35
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"PCLMUL"],
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36
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+
"ivybridge"=>
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["MMX",
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"SSE",
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"SSE2",
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"SSE3",
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"SSSE3",
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"SSE4.1",
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"SSE4.2",
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"POPCNT",
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"AVX",
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+
"AES",
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"PCLMUL",
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"FSGSBASE",
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"RDRND",
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"F16C"],
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+
"haswell"=>
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["MOVBE",
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"MMX",
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"SSE",
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"SSE2",
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"SSE3",
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"SSSE3",
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"SSE4.1",
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"SSE4.2",
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"POPCNT",
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"AVX",
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"AVX2",
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"AES",
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"PCLMUL",
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"FSGSBASE",
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"RDRND",
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"FMA",
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"BMI",
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"BMI2",
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"F16C"],
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"broadwell"=>
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["MOVBE",
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"MMX",
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"SSE",
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"SSE2",
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"SSE3",
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"SSSE3",
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"SSE4.1",
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"SSE4.2",
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"POPCNT",
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"AVX",
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"AVX2",
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"AES",
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"PCLMUL",
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+
"FSGSBASE",
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+
"RDRND",
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+
"FMA",
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"BMI",
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"BMI2",
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"F16C",
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"RDSEED",
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"ADCX",
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"PREFETCHW"],
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+
"bonnell"=>["MOVBE", "MMX", "SSE", "SSE2", "SSE3", "SSSE3"],
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+
"silvermont"=>
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["MOVBE",
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"MMX",
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"SSE",
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"SSE2",
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"SSE3",
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"SSSE3",
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"SSE4.1",
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"SSE4.2",
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"POPCNT",
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"AES",
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"PCLMUL",
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"RDRND"],
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"bdver1"=>
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["FMA4",
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"AVX",
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"XOP",
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"LWP",
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"AES",
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"PCL_MUL",
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"CX16",
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"MMX",
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"SSE",
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"SSE2",
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"SSE3",
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"SSE4A",
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"SSSE3",
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"SSE4.1",
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"SSE4.2",
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"ABM"],
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+
"bdver2"=>
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["BMI",
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+
"TBM",
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"F16C",
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+
"FMA",
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+
"FMA4",
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+
"AVX",
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+
"XOP",
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+
"LWP",
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"AES",
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+
"PCL_MUL",
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+
"CX16",
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+
"MMX",
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138
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+
"SSE",
|
139
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+
"SSE2",
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140
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+
"SSE3",
|
141
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+
"SSE4A",
|
142
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+
"SSSE3",
|
143
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+
"SSE4.1",
|
144
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+
"SSE4.2",
|
145
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+
"ABM"],
|
146
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+
"bdver3"=>
|
147
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+
["BMI",
|
148
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+
"TBM",
|
149
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+
"F16C",
|
150
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+
"FMA",
|
151
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+
"FMA4",
|
152
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+
"FSGSBASE",
|
153
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+
"AVX",
|
154
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+
"XOP",
|
155
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+
"LWP",
|
156
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+
"AES",
|
157
|
+
"PCL_MUL",
|
158
|
+
"CX16",
|
159
|
+
"MMX",
|
160
|
+
"SSE",
|
161
|
+
"SSE2",
|
162
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+
"SSE3",
|
163
|
+
"SSE4A",
|
164
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+
"SSSE3",
|
165
|
+
"SSE4.1",
|
166
|
+
"SSE4.2",
|
167
|
+
"ABM"],
|
168
|
+
"bdver4"=>
|
169
|
+
["BMI2",
|
170
|
+
"TBM",
|
171
|
+
"F16C",
|
172
|
+
"FMA",
|
173
|
+
"FMA4",
|
174
|
+
"FSGSBASE",
|
175
|
+
"AVX",
|
176
|
+
"AVX2",
|
177
|
+
"XOP",
|
178
|
+
"LWP",
|
179
|
+
"AES",
|
180
|
+
"PCL_MUL",
|
181
|
+
"CX16",
|
182
|
+
"MOVBE",
|
183
|
+
"MMX",
|
184
|
+
"SSE",
|
185
|
+
"SSE2",
|
186
|
+
"SSE3",
|
187
|
+
"SSE4A",
|
188
|
+
"SSSE3",
|
189
|
+
"SSE4.1",
|
190
|
+
"SSE4.2",
|
191
|
+
"ABM"],
|
192
|
+
"btver1"=>["MMX", "SSE", "SSE2", "SSE3", "SSSE3", "SSE4A", "CX16", "ABM"],
|
193
|
+
"btver2"=>
|
194
|
+
["MOVBE",
|
195
|
+
"F16C",
|
196
|
+
"BMI",
|
197
|
+
"AVX",
|
198
|
+
"PCL_MUL",
|
199
|
+
"AES",
|
200
|
+
"SSE4.2",
|
201
|
+
"SSE4.1",
|
202
|
+
"CX16",
|
203
|
+
"ABM",
|
204
|
+
"SSE4A",
|
205
|
+
"SSSE3",
|
206
|
+
"SSE3",
|
207
|
+
"SSE2",
|
208
|
+
"SSE",
|
209
|
+
"MMX"]}
|
210
|
+
end
|