zena-sdk 0.1.4__cp38-abi3-win_amd64.whl

qsys/transpiler/validate.py

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+from __future__ import annotations
+
+from dataclasses import dataclass
+
+from ..backends.base import Backend
+from ..errors import ValidationError
+from ..ir.types import Instruction
+
+# Spec for supported ops in our current IR
+# name -> (num_qubits, num_params, allows_clbits)
+GATE_SPECS = {
+    "x": (1, 0, False),
+    "sx": (1, 0, False),
+    "rz": (1, 1, False),
+    "cx": (2, 0, False),
+    "measure": (1, 0, True),  # (q, c) pair
+}
+
+
+@dataclass(frozen=True)
+class ValidationReport:
+    ok: bool
+    needs_routing: (
+        bool  # True if there exists a CX that is not directly allowed by coupling map
+    )
+    messages: list[str]
+
+
+def _check_gate_shape(inst: Instruction) -> None:
+    name = inst.name
+    if name not in GATE_SPECS:
+        raise ValidationError(f"Unknown operation: {name}")
+
+    q_needed, p_needed, allow_c = GATE_SPECS[name]
+
+    if len(inst.qubits) != q_needed:
+        raise ValidationError(
+            f"Gate '{name}' expects {q_needed} qubit(s), got {len(inst.qubits)}: {inst.qubits}"
+        )
+
+    if len(inst.params) != p_needed:
+        raise ValidationError(
+            f"Gate '{name}' expects {p_needed} parameter(s), got {len(inst.params)}: {inst.params}"
+        )
+
+    if inst.clbits is not None and not allow_c:
+        raise ValidationError(
+            f"Gate '{name}' does not take classical bits (got {inst.clbits})"
+        )
+
+    if inst.clbits is None and allow_c:
+        # measure must provide clbits (we encode them in Instruction.clbits)
+        raise ValidationError("Measure must specify destination classical bit(s)")
+
+
+def _check_index_bounds(inst: Instruction, n_qubits: int, n_clbits: int) -> None:
+    # Qubit indices must be within 0..n_qubits-1 and distinct for multi-qubit ops
+    for q in inst.qubits:
+        if q < 0 or q >= n_qubits:
+            raise ValidationError(f"Qubit index out of range in op {inst}: q={q}")
+
+    if len(inst.qubits) != len(set(inst.qubits)):
+        raise ValidationError(f"Repeated qubit index in op {inst}")
+
+    # Classical indices (if any) must be within 0..n_clbits-1 and distinct
+    if inst.clbits is not None:
+        for c in inst.clbits:
+            if c < 0 or c >= n_clbits:
+                raise ValidationError(
+                    f"Classical bit index out of range in op {inst}: c={c}"
+                )
+        if len(inst.clbits) != len(set(inst.clbits)):
+            raise ValidationError(f"Repeated classical bit index in op {inst}")
+
+
+def _cx_needs_routing(
+    control: int, target: int, coupling_map: list[tuple[int, int]]
+) -> bool:
+    """Return True if (control,target) is not directly supported by coupling_map (undirected)."""
+    if not coupling_map:
+        # If backend provides no map, assume fully connected (dev convenience)
+        return False
+    return (control, target) not in coupling_map and (
+        target,
+        control,
+    ) not in coupling_map
+
+
+def validate(circuit, backend: Backend) -> ValidationReport:
+    """
+    Validate a circuit against basic rules and the backend's size/basis.
+
+    - Checks gate names, arity, parameter counts.
+    - Checks qubit/clbit index ranges and duplicates.
+    - Checks that every op name is in backend.target.basis_gates.
+    - Does NOT fail for CX connectivity; instead marks needs_routing=True when a CX
+      doesn't match the coupling map (routing pass will handle it in 5.3).
+    """
+    msgs: list[str] = []
+    n_qubits = circuit.n_qubits
+    n_clbits = getattr(circuit, "n_clbits", 0)
+    tgt = backend.target
+
+    if n_qubits > tgt.n_qubits:
+        raise ValidationError(
+            f"Circuit uses {n_qubits} qubits but backend supports only {tgt.n_qubits}"
+        )
+
+    needs_routing = False
+    basis = set(tgt.basis_gates)
+
+    for inst in circuit.instructions:
+        # Name is supported by our IR and by backend basis
+        _check_gate_shape(inst)
+        if inst.name not in basis:
+            raise ValidationError(
+                f"Gate '{inst.name}' not in backend basis_gates: {sorted(basis)}"
+            )
+
+        # Index ranges / duplicates
+        _check_index_bounds(inst, n_qubits, n_clbits)
+
+        # Connectivity hint (don’t fail; mark for routing)
+        if inst.name == "cx":
+            c, t = inst.qubits
+            if _cx_needs_routing(c, t, tgt.coupling_map):
+                needs_routing = True
+
+    if needs_routing:
+        msgs.append("Routing required: at least one CX not on a coupling edge.")
+
+    return ValidationReport(ok=True, needs_routing=needs_routing, messages=msgs)

qsys/viz/__init__.py

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+# viz package

qsys/viz/text_drawer.py

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+from __future__ import annotations
+from typing import List
+from ..ir.types import Instruction
+
+# Conventions
+# - Qubits are rendered top (q0) → bottom (q{n-1}) for readability.
+# - Columns advance in time, one column per instruction (simple MVP).
+# - Supported ops: x, sx, rz(theta), cx, measure.
+# - For measure, we annotate the destination classical bit as M[c].
+# - Little-endian execution still applies (this is only visualization).
+
+CELL_W = 5  # width per column (room for labels like "rz(π/2)" short form later)
+
+
+def _empty_canvas(n_qubits: int, n_cols: int) -> List[List[str]]:
+    rows = []
+    for _ in range(n_qubits):
+        row = ["─" * CELL_W for _ in range(n_cols)]
+        rows.append(row)
+    return rows
+
+
+def _place_label(cell: str, label: str) -> str:
+    # Center label within CELL_W using monospaced assumptions
+    pad = max(0, CELL_W - len(label))
+    left = pad // 2
+    right = pad - left
+    return " " * left + label + " " * right
+
+
+def _rz_label(theta: float) -> str:
+    # Keep it compact; 3 significant digits
+    return f"rz({theta:.3g})"
+
+
+def draw_ascii(n_qubits: int, instructions: List[Instruction]) -> str:
+    n_cols = max(1, len(instructions))
+    canvas = _empty_canvas(n_qubits, n_cols)
+
+    # Helper to map logical qubit index to row (q0 at top)
+    def row_of(q: int) -> int:
+        return q  # q0 at row 0, q1 at row 1, ...
+
+    for col, inst in enumerate(instructions):
+        name, qs, ps, cs = inst.name, inst.qubits, inst.params, inst.clbits
+
+        if name in ("x", "sx", "rz", "measure"):
+            q = qs[0]
+            r = row_of(q)
+            if name == "x":
+                canvas[r][col] = _place_label(canvas[r][col], "X")
+            elif name == "sx":
+                canvas[r][col] = _place_label(canvas[r][col], "SX")
+            elif name == "rz":
+                canvas[r][col] = _place_label(canvas[r][col], _rz_label(float(ps[0])))
+            elif name == "measure":
+                lbl = "M" if cs is None or len(cs) == 0 else f"M[{cs[0]}]"
+                canvas[r][col] = _place_label(canvas[r][col], lbl)
+            # leave other rows in this column as wires
+            continue
+
+        if name == "cx":
+            c, t = qs
+            rc = row_of(c)
+            rt = row_of(t)
+            top, bot = sorted((rc, rt))
+            # Place control and target symbols
+            canvas[rc][col] = _place_label(canvas[rc][col], "●")  # control
+            canvas[rt][col] = _place_label(
+                canvas[rt][col], "X"
+            )  # target (CNOT symbolized as X)
+            # Draw vertical wire between them in this column
+            for r in range(top + 1, bot):
+                canvas[r][col] = _place_label(canvas[r][col], "│")
+            continue
+
+        # Unknown op: show as name
+        for q in qs:
+            r = row_of(q)
+            canvas[r][col] = _place_label(canvas[r][col], name.upper())
+
+    # Build header with qubit labels
+    lines: List[str] = []
+    for q in range(n_qubits):
+        label = f"q{q}: "
+        line = label + "".join(canvas[q])
+        lines.append(line)
+
+    return "\n".join(lines)

simulator_statevector/__init__.py

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+from .simulator_statevector import *
+
+__doc__ = simulator_statevector.__doc__
+if hasattr(simulator_statevector, "__all__"):
+    __all__ = simulator_statevector.__all__

zena/__init__.py

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+from .circuit import QuantumCircuit, QuantumRegister, ClassicalRegister
+from .providers.aer import Aer
+from .execute import execute
+from .visualization import plot_histogram
+from .compiler import transpile
+
+__version__ = "0.1.0"

zena/circuit/__init__.py

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+from .quantum_circuit import QuantumCircuit
+from .register import QuantumRegister, ClassicalRegister

zena/circuit/quantum_circuit.py

@@ -0,0 +1,218 @@
+"""
+QuantumCircuit class mimicking Qiskit's API, delegating to qsys.
+"""
+from typing import Union, List, Optional
+from .register import QuantumRegister, ClassicalRegister
+
+# Import the core composer from existing codebase
+# We treat qsys as the internal engine
+try:
+    from qsys.circuit.quantum_circuit import QuantumCircuit as QSysCircuit
+except ImportError as e:
+    # Fallback/Mock for development if qsys is not in path
+    print(f"DEBUG: Failed to import qsys: {e}")
+    QSysCircuit = None
+
+class QuantumCircuit:
+    """
+    QuantumCircuit adaptable to Zena SDK.
+    """
+    def __init__(self, *regs, name: Optional[str] = None):
+        self.name = name
+        self.qregs = []
+        self.cregs = []
+        self._qubits = []
+        self._clbits = []
+        
+        # Parse arguments similar to Qiskit (int or Register)
+        if len(regs) == 0:
+            # Empty circuit
+            pass
+        elif all(isinstance(r, int) for r in regs):
+            # Case: QuantumCircuit(n_qubits, n_clbits)
+            n_qubits = regs[0]
+            n_clbits = regs[1] if len(regs) > 1 else 0
+            self.add_register(QuantumRegister(n_qubits, 'q'))
+            if n_clbits > 0:
+                self.add_register(ClassicalRegister(n_clbits, 'c'))
+        else:
+            # Case: QuantumCircuit(qreg, creg)
+            for r in regs:
+                if isinstance(r, (QuantumRegister, ClassicalRegister)):
+                    self.add_register(r)
+                else:
+                    raise TypeError("Arguments must be integers or Registers")
+
+        # Initialize the underlying qsys Core Circuit
+        if QSysCircuit:
+            self._core_circuit = QSysCircuit(len(self._qubits), len(self._clbits))
+        else:
+            self._core_circuit = None
+            print("Warning: qsys.circuit not found. Core delegation disabled.")
+
+    def add_register(self, register: Union[QuantumRegister, ClassicalRegister]):
+        if isinstance(register, QuantumRegister):
+            self.qregs.append(register)
+            # Flatten qubits mapping (simplistic for now)
+            start_index = len(self._qubits)
+            self._qubits.extend([i for i in range(start_index, start_index + register.size)])
+        elif isinstance(register, ClassicalRegister):
+            self.cregs.append(register)
+            start_index = len(self._clbits)
+            self._clbits.extend([i for i in range(start_index, start_index + register.size)])
+            
+    def h(self, qubit):
+        """Apply Hadamard gate."""
+        q_idx = self._resolve_index(qubit)
+        if self._core_circuit:
+            self._core_circuit.h(q_idx)
+        return self
+
+    def x(self, qubit):
+        """Apply Pauli-X gate."""
+        q_idx = self._resolve_index(qubit)
+        if self._core_circuit:
+            self._core_circuit.x(q_idx)
+        return self
+
+    def y(self, qubit):
+        """Apply Pauli-Y gate."""
+        q_idx = self._resolve_index(qubit)
+        if self._core_circuit:
+            # Note: qsys uses string name 'y' for Instruction, which execute.py handles
+            from qsys.ir.types import Instruction
+            self._core_circuit._instructions.append(Instruction(name="y", qubits=(q_idx,)))
+        return self
+
+    def z(self, qubit):
+        """Apply Pauli-Z gate."""
+        q_idx = self._resolve_index(qubit)
+        if self._core_circuit:
+            from qsys.ir.types import Instruction
+            self._core_circuit._instructions.append(Instruction(name="z", qubits=(q_idx,)))
+        return self
+
+    def s(self, qubit):
+        """Apply S gate."""
+        q_idx = self._resolve_index(qubit)
+        if self._core_circuit:
+            from qsys.ir.types import Instruction
+            self._core_circuit._instructions.append(Instruction(name="s", qubits=(q_idx,)))
+        return self
+
+    def sdg(self, qubit):
+        """Apply S-dagger gate."""
+        q_idx = self._resolve_index(qubit)
+        if self._core_circuit:
+            from qsys.ir.types import Instruction
+            self._core_circuit._instructions.append(Instruction(name="sdg", qubits=(q_idx,)))
+        return self
+
+    def t(self, qubit):
+        """Apply T gate."""
+        q_idx = self._resolve_index(qubit)
+        if self._core_circuit:
+            from qsys.ir.types import Instruction
+            self._core_circuit._instructions.append(Instruction(name="t", qubits=(q_idx,)))
+        return self
+
+    def tdg(self, qubit):
+        """Apply T-dagger gate."""
+        q_idx = self._resolve_index(qubit)
+        if self._core_circuit:
+            from qsys.ir.types import Instruction
+            self._core_circuit._instructions.append(Instruction(name="tdg", qubits=(q_idx,)))
+        return self
+
+    def sx(self, qubit):
+        """Apply sqrt-X gate."""
+        q_idx = self._resolve_index(qubit)
+        if self._core_circuit:
+            self._core_circuit.sx(q_idx)
+        return self
+
+    def rx(self, theta, qubit):
+        """Apply RX gate."""
+        q_idx = self._resolve_index(qubit)
+        if self._core_circuit:
+            from qsys.ir.types import Instruction
+            self._core_circuit._instructions.append(
+                Instruction(name="rx", qubits=(q_idx,), params=(float(theta),))
+            )
+        return self
+
+    def ry(self, theta, qubit):
+        """Apply RY gate."""
+        q_idx = self._resolve_index(qubit)
+        if self._core_circuit:
+            from qsys.ir.types import Instruction
+            self._core_circuit._instructions.append(
+                Instruction(name="ry", qubits=(q_idx,), params=(float(theta),))
+            )
+        return self
+
+    def rz(self, theta, qubit):
+        """Apply RZ gate."""
+        q_idx = self._resolve_index(qubit)
+        if self._core_circuit:
+            self._core_circuit.rz(q_idx, theta)
+        return self
+
+    def cx(self, control_qubit, target_qubit):
+        """Apply CNOT gate."""
+        c_idx = self._resolve_index(control_qubit)
+        t_idx = self._resolve_index(target_qubit)
+        if self._core_circuit:
+            self._core_circuit.cx(c_idx, t_idx)
+        return self
+
+    def swap(self, qubit1, qubit2):
+        """Apply SWAP gate."""
+        q1_idx = self._resolve_index(qubit1)
+        q2_idx = self._resolve_index(qubit2)
+        if self._core_circuit:
+            from qsys.ir.types import Instruction
+            self._core_circuit._instructions.append(Instruction(name="swap", qubits=(q1_idx, q2_idx)))
+        return self
+
+    def measure(self, qubits, clbits):
+        """Measure quantum bits into classical bits."""
+        if isinstance(qubits, int):
+            qubits = [qubits]
+        if isinstance(clbits, int):
+            clbits = [clbits]
+
+        if len(qubits) != len(clbits):
+            raise ValueError("Number of qubits and classical bits must match.")
+
+        for q, c in zip(qubits, clbits):
+            q_idx = self._resolve_index(q)
+            c_idx = self._resolve_cbit_index(c)
+            if self._core_circuit:
+                self._core_circuit.measure(q_idx, c_idx)
+        return self
+
+    def draw(self, output='text'):
+        """Draw the circuit."""
+        if self._core_circuit:
+            return self._core_circuit.draw(mode=output)
+        return "Core circuit not initialized."
+
+    def _resolve_index(self, qubit) -> int:
+        """
+        Resolve user input (int or bit object) to flat integer index for qsys.
+        For now, we assume user passes integers as indices.
+        """
+        # TODO: Support Qubit object (e.g. qreg[0])
+        if isinstance(qubit, int):
+            if qubit < 0 or qubit >= len(self._qubits):
+                raise IndexError(f"Qubit index {qubit} out of range.")
+            return qubit
+        raise TypeError("Qubit must be an integer index for now.")
+
+    def _resolve_cbit_index(self, cbit) -> int:
+        if isinstance(cbit, int):
+             if cbit < 0 or cbit >= len(self._clbits):
+                raise IndexError(f"Clbit index {cbit} out of range.")
+             return cbit
+        raise TypeError("Clbit must be an integer index for now.")

zena/circuit/register.py

@@ -0,0 +1,28 @@
+"""
+Quantum and Classical Registers.
+"""
+from typing import Optional
+
+class Register:
+    """Base class for registers."""
+    def __init__(self, size: int, name: Optional[str] = None):
+        if size <= 0:
+            raise ValueError("Register size must be positive")
+        self.size = size
+        self.name = name
+        
+    def __len__(self):
+        return self.size
+        
+    def __repr__(self):
+        return f"{self.__class__.__name__}({self.size}, '{self.name}')"
+
+class QuantumRegister(Register):
+    """Implement a quantum register."""
+    def __init__(self, size: int, name: Optional[str] = "q"):
+        super().__init__(size, name)
+
+class ClassicalRegister(Register):
+    """Implement a classical register."""
+    def __init__(self, size: int, name: Optional[str] = "c"):
+        super().__init__(size, name)

zena/compiler/__init__.py

@@ -0,0 +1,72 @@
+"""
+Zena Compiler module.
+"""
+from typing import Union, List, Optional
+from ..circuit import QuantumCircuit
+from ..providers.backend import Backend
+
+# Import qsys transpiler
+try:
+    from qsys.transpiler.passes import transpile as qsys_transpile
+except ImportError:
+    qsys_transpile = None
+
+def transpile(circuits: Union[QuantumCircuit, List[QuantumCircuit]],
+              backend: Optional[Backend] = None,
+              **kwargs):
+    """
+    Transpile the circuit(s) for a given backend.
+    
+    Args:
+        circuits: Circuit or list of circuits to transpile.
+        backend: Backend to target (optional).
+        
+    Returns:
+        The transpiled circuit(s).
+    """
+    if not qsys_transpile:
+        print("Warning: qsys transpiler not found. Returning circuit(s) as is.")
+        return circuits
+
+    is_list = isinstance(circuits, list)
+    if not is_list:
+        circuits = [circuits]
+
+    transpiled_circuits = []
+    for qc in circuits:
+        if not hasattr(qc, "_core_circuit") or not qc._core_circuit:
+            transpiled_circuits.append(qc)
+            continue
+            
+        # Call qsys transpiler on the internal core circuit
+        # qsys.transpile expects (core_circuit, backend)
+        # Note: In Phase 2, we passed use_transpiler=False because our Zena Backends
+        # didn't have .target. To make this work, we'll need to pass the wrapped qsys backend
+        # if available, or a default one.
+        
+        # For now, let's just use the opt1q if no backend is provided
+        from qsys.transpiler.opt1q import optimize_1q
+        
+        core_qc = qc._core_circuit
+        
+        if backend:
+            # If backend is provided, we try to use the full qsys transpile
+            # We need to extract the underlying qsys backend from Zena backend if possible
+            # Or just pass the Zena backend if it has the required properties (target, etc.)
+            try:
+                # We expect qsys.transpile to handle cases where backend might be None or simplified
+                # but if it needs .target, we might need a fallback.
+                transpiled_core = qsys_transpile(core_qc, backend, **kwargs)
+            except Exception as e:
+                print(f"Warning: full transpile failed ({e}). Falling back to 1q optimization.")
+                transpiled_core = optimize_1q(core_qc)
+        else:
+            # Default optimization if no backend
+            transpiled_core = optimize_1q(core_qc)
+            
+        # Update the Zena circuit with the transpiled core
+        # In a real SDK, we'd probably return a NEW Zena circuit
+        qc._core_circuit = transpiled_core
+        transpiled_circuits.append(qc)
+
+    return transpiled_circuits[0] if not is_list else transpiled_circuits

zena/execute.py

@@ -0,0 +1,35 @@
+"""
+Execute function.
+"""
+from .providers.aer import Aer
+from .compiler import transpile
+
+def execute(experiments, backend=None, shots=1024, **kwargs):
+    """
+    Execute a list of circuits or a single circuit on a backend.
+    
+    Args:
+        experiments (QuantumCircuit or list): Circuit(s) to execute.
+        backend (Backend): The backend to execute on.
+        shots (int): Number of shots (default: 1024).
+        
+    Returns:
+        Job: A job object containing the result.
+    """
+    if backend is None:
+        # Default to statevector simulator if none provided
+        backend = Aer.get_backend("statevector_simulator")
+        
+    # Transpile the circuits before execution
+    experiments = transpile(experiments, backend=backend)
+        
+    if not isinstance(experiments, list):
+        experiments = [experiments]
+        
+    # For now, we only support single circuit execution in this simplified wrapper
+    # In full implementation, we would loop and aggregate results
+    if len(experiments) > 1:
+        raise NotImplementedError("Batch execution not yet fully supported in this simplified wrapper.")
+        
+    circuit = experiments[0]
+    return backend.run(circuit, shots=shots, **kwargs)

zena/providers/__init__.py

@@ -0,0 +1,5 @@
+"""
+Zena Providers module.
+"""
+class Aer:
+    pass