yowasp-yosys 0.61.0.0.post1073__py3-none-any.whl → 0.62.0.0.post1088__py3-none-any.whl

yowasp_yosys/share/ecp5/cells_bb.v

@@ -1,24 +1,29 @@
 // Created by cells_xtra.py from Lattice models
 
 (* blackbox *) (* keep *)
-module GSR (...);
+module GSR(GSR);
     input GSR;
 endmodule
 
 (* blackbox *)
-module PUR (...);
+module PUR(PUR);
     parameter RST_PULSE = 1;
     input PUR;
 endmodule
 
 (* blackbox *) (* keep *)
-module SGSR (...);
+module SGSR(GSR, CLK);
     input GSR;
     input CLK;
 endmodule
 
 (* blackbox *)
-module PDPW16KD (...);
+module PDPW16KD(DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28, DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18, DI17, DI16, DI15
+, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6, ADW5, ADW4, ADW3
+, ADW2, ADW1, ADW0, BE3, BE2, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR13, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5
+, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28, DO27
+, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6
+, DO5, DO4, DO3, DO2, DO1, DO0);
     parameter CLKRMUX = "CLKR";
     parameter CLKWMUX = "CLKW";
     parameter DATA_WIDTH_W = 36;
@@ -208,7 +213,18 @@ module PDPW16KD (...);
 endmodule
 
 (* blackbox *)
-module MULT18X18D (...);
+module MULT18X18D(A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0, B17, B16, B15
+, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0, C17, C16, C15, C14, C13, C12
+, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, SIGNEDA, SIGNEDB, SOURCEA, SOURCEB, CLK3, CLK2, CLK1, CLK0, CE3
+, CE2, CE1, CE0, RST3, RST2, RST1, RST0, SRIA17, SRIA16, SRIA15, SRIA14, SRIA13, SRIA12, SRIA11, SRIA10, SRIA9, SRIA8, SRIA7, SRIA6, SRIA5, SRIA4
+, SRIA3, SRIA2, SRIA1, SRIA0, SRIB17, SRIB16, SRIB15, SRIB14, SRIB13, SRIB12, SRIB11, SRIB10, SRIB9, SRIB8, SRIB7, SRIB6, SRIB5, SRIB4, SRIB3, SRIB2, SRIB1
+, SRIB0, SROA17, SROA16, SROA15, SROA14, SROA13, SROA12, SROA11, SROA10, SROA9, SROA8, SROA7, SROA6, SROA5, SROA4, SROA3, SROA2, SROA1, SROA0, SROB17, SROB16
+, SROB15, SROB14, SROB13, SROB12, SROB11, SROB10, SROB9, SROB8, SROB7, SROB6, SROB5, SROB4, SROB3, SROB2, SROB1, SROB0, ROA17, ROA16, ROA15, ROA14, ROA13
+, ROA12, ROA11, ROA10, ROA9, ROA8, ROA7, ROA6, ROA5, ROA4, ROA3, ROA2, ROA1, ROA0, ROB17, ROB16, ROB15, ROB14, ROB13, ROB12, ROB11, ROB10
+, ROB9, ROB8, ROB7, ROB6, ROB5, ROB4, ROB3, ROB2, ROB1, ROB0, ROC17, ROC16, ROC15, ROC14, ROC13, ROC12, ROC11, ROC10, ROC9, ROC8, ROC7
+, ROC6, ROC5, ROC4, ROC3, ROC2, ROC1, ROC0, P35, P34, P33, P32, P31, P30, P29, P28, P27, P26, P25, P24, P23, P22
+, P21, P20, P19, P18, P17, P16, P15, P14, P13, P12, P11, P10, P9, P8, P7, P6, P5, P4, P3, P2, P1
+, P0, SIGNEDP);
     parameter REG_INPUTA_CLK = "NONE";
     parameter REG_INPUTA_CE = "CE0";
     parameter REG_INPUTA_RST = "RST0";
@@ -470,7 +486,28 @@ module MULT18X18D (...);
 endmodule
 
 (* blackbox *)
-module ALU54B (...);
+module ALU54B(CE3, CE2, CE1, CE0, CLK3, CLK2, CLK1, CLK0, RST3, RST2, RST1, RST0, SIGNEDIA, SIGNEDIB, SIGNEDCIN, A35, A34, A33, A32, A31, A30
+, A29, A28, A27, A26, A25, A24, A23, A22, A21, A20, A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9
+, A8, A7, A6, A5, A4, A3, A2, A1, A0, B35, B34, B33, B32, B31, B30, B29, B28, B27, B26, B25, B24
+, B23, B22, B21, B20, B19, B18, B17, B16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3
+, B2, B1, B0, C53, C52, C51, C50, C49, C48, C47, C46, C45, C44, C43, C42, C41, C40, C39, C38, C37, C36
+, C35, C34, C33, C32, C31, C30, C29, C28, C27, C26, C25, C24, C23, C22, C21, C20, C19, C18, C17, C16, C15
+, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, CFB53, CFB52, CFB51, CFB50, CFB49, CFB48
+, CFB47, CFB46, CFB45, CFB44, CFB43, CFB42, CFB41, CFB40, CFB39, CFB38, CFB37, CFB36, CFB35, CFB34, CFB33, CFB32, CFB31, CFB30, CFB29, CFB28, CFB27
+, CFB26, CFB25, CFB24, CFB23, CFB22, CFB21, CFB20, CFB19, CFB18, CFB17, CFB16, CFB15, CFB14, CFB13, CFB12, CFB11, CFB10, CFB9, CFB8, CFB7, CFB6
+, CFB5, CFB4, CFB3, CFB2, CFB1, CFB0, MA35, MA34, MA33, MA32, MA31, MA30, MA29, MA28, MA27, MA26, MA25, MA24, MA23, MA22, MA21
+, MA20, MA19, MA18, MA17, MA16, MA15, MA14, MA13, MA12, MA11, MA10, MA9, MA8, MA7, MA6, MA5, MA4, MA3, MA2, MA1, MA0
+, MB35, MB34, MB33, MB32, MB31, MB30, MB29, MB28, MB27, MB26, MB25, MB24, MB23, MB22, MB21, MB20, MB19, MB18, MB17, MB16, MB15
+, MB14, MB13, MB12, MB11, MB10, MB9, MB8, MB7, MB6, MB5, MB4, MB3, MB2, MB1, MB0, CIN53, CIN52, CIN51, CIN50, CIN49, CIN48
+, CIN47, CIN46, CIN45, CIN44, CIN43, CIN42, CIN41, CIN40, CIN39, CIN38, CIN37, CIN36, CIN35, CIN34, CIN33, CIN32, CIN31, CIN30, CIN29, CIN28, CIN27
+, CIN26, CIN25, CIN24, CIN23, CIN22, CIN21, CIN20, CIN19, CIN18, CIN17, CIN16, CIN15, CIN14, CIN13, CIN12, CIN11, CIN10, CIN9, CIN8, CIN7, CIN6
+, CIN5, CIN4, CIN3, CIN2, CIN1, CIN0, OP10, OP9, OP8, OP7, OP6, OP5, OP4, OP3, OP2, OP1, OP0, R53, R52, R51, R50
+, R49, R48, R47, R46, R45, R44, R43, R42, R41, R40, R39, R38, R37, R36, R35, R34, R33, R32, R31, R30, R29
+, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, R16, R15, R14, R13, R12, R11, R10, R9, R8
+, R7, R6, R5, R4, R3, R2, R1, R0, CO53, CO52, CO51, CO50, CO49, CO48, CO47, CO46, CO45, CO44, CO43, CO42, CO41
+, CO40, CO39, CO38, CO37, CO36, CO35, CO34, CO33, CO32, CO31, CO30, CO29, CO28, CO27, CO26, CO25, CO24, CO23, CO22, CO21, CO20
+, CO19, CO18, CO17, CO16, CO15, CO14, CO13, CO12, CO11, CO10, CO9, CO8, CO7, CO6, CO5, CO4, CO3, CO2, CO1, CO0, EQZ
+, EQZM, EQOM, EQPAT, EQPATB, OVER, UNDER, OVERUNDER, SIGNEDR);
     parameter REG_INPUTC0_CLK = "NONE";
     parameter REG_INPUTC0_CE = "CE0";
     parameter REG_INPUTC0_RST = "RST0";
@@ -970,7 +1007,7 @@ module ALU54B (...);
 endmodule
 
 (* blackbox *)
-module CLKDIVF (...);
+module CLKDIVF(CLKI, RST, ALIGNWD, CDIVX);
     parameter GSR = "DISABLED";
     parameter DIV = "2.0";
     input CLKI;
@@ -980,7 +1017,7 @@ module CLKDIVF (...);
 endmodule
 
 (* blackbox *)
-module PCSCLKDIV (...);
+module PCSCLKDIV(CLKI, RST, SEL2, SEL1, SEL0, CDIV1, CDIVX);
     parameter GSR = "DISABLED";
     input CLKI;
     input RST;
@@ -992,7 +1029,7 @@ module PCSCLKDIV (...);
 endmodule
 
 (* blackbox *)
-module DCSC (...);
+module DCSC(CLK1, CLK0, SEL1, SEL0, MODESEL, DCSOUT);
     parameter DCSMODE = "POS";
     input CLK1;
     input CLK0;
@@ -1003,21 +1040,21 @@ module DCSC (...);
 endmodule
 
 (* blackbox *)
-module DCCA (...);
+module DCCA(CLKI, CE, CLKO);
     input CLKI;
     input CE;
     output CLKO;
 endmodule
 
 (* blackbox *)
-module ECLKSYNCB (...);
+module ECLKSYNCB(ECLKI, STOP, ECLKO);
     input ECLKI;
     input STOP;
     output ECLKO;
 endmodule
 
 (* blackbox *)
-module ECLKBRIDGECS (...);
+module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT);
     input CLK0;
     input CLK1;
     input SEL;
@@ -1025,7 +1062,7 @@ module ECLKBRIDGECS (...);
 endmodule
 
 (* blackbox *)
-module DELAYF (...);
+module DELAYF(A, LOADN, MOVE, DIRECTION, Z, CFLAG);
     parameter DEL_MODE = "USER_DEFINED";
     parameter DEL_VALUE = 0;
     input A;
@@ -1037,7 +1074,7 @@ module DELAYF (...);
 endmodule
 
 (* blackbox *)
-module DELAYG (...);
+module DELAYG(A, Z);
     parameter DEL_MODE = "USER_DEFINED";
     parameter DEL_VALUE = 0;
     input A;
@@ -1045,13 +1082,14 @@ module DELAYG (...);
 endmodule
 
 (* blackbox *) (* keep *)
-module USRMCLK (...);
+module USRMCLK(USRMCLKI, USRMCLKTS);
     input USRMCLKI;
     input USRMCLKTS;
 endmodule
 
 (* blackbox *)
-module DQSBUFM (...);
+module DQSBUFM(DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL, ECLK, SCLK, RST, DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0, PAUSE, RDLOADN, RDMOVE
+, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, DQSR90, DQSW, DQSW270, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, DATAVALID, BURSTDET, RDCFLAG, WRCFLAG);
     parameter DQS_LI_DEL_VAL = 4;
     parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
     parameter DQS_LO_DEL_VAL = 0;
@@ -1098,7 +1136,7 @@ module DQSBUFM (...);
 endmodule
 
 (* blackbox *)
-module DDRDLLA (...);
+module DDRDLLA(CLK, RST, UDDCNTLN, FREEZE, DDRDEL, LOCK, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0);
     parameter FORCE_MAX_DELAY = "NO";
     parameter GSR = "ENABLED";
     input CLK;
@@ -1118,7 +1156,7 @@ module DDRDLLA (...);
 endmodule
 
 (* blackbox *)
-module DLLDELD (...);
+module DLLDELD(A, DDRDEL, LOADN, MOVE, DIRECTION, Z, CFLAG);
     input A;
     input DDRDEL;
     input LOADN;
@@ -1129,7 +1167,7 @@ module DLLDELD (...);
 endmodule
 
 (* blackbox *)
-module IDDRX1F (...);
+module IDDRX1F(D, SCLK, RST, Q0, Q1);
     parameter GSR = "ENABLED";
     input D;
     input SCLK;
@@ -1139,7 +1177,7 @@ module IDDRX1F (...);
 endmodule
 
 (* blackbox *)
-module IDDRX2F (...);
+module IDDRX2F(D, SCLK, ECLK, RST, ALIGNWD, Q3, Q2, Q1, Q0);
     parameter GSR = "ENABLED";
     input D;
     input SCLK;
@@ -1153,7 +1191,7 @@ module IDDRX2F (...);
 endmodule
 
 (* blackbox *)
-module IDDR71B (...);
+module IDDR71B(D, SCLK, ECLK, RST, ALIGNWD, Q6, Q5, Q4, Q3, Q2, Q1, Q0);
     parameter GSR = "ENABLED";
     input D;
     input SCLK;
@@ -1170,7 +1208,7 @@ module IDDR71B (...);
 endmodule
 
 (* blackbox *)
-module IDDRX2DQA (...);
+module IDDRX2DQA(SCLK, ECLK, DQSR90, D, RST, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, Q3, Q2, Q1, Q0, QWL);
     parameter GSR = "ENABLED";
     input SCLK;
     input ECLK;
@@ -1191,7 +1229,7 @@ module IDDRX2DQA (...);
 endmodule
 
 (* blackbox *)
-module ODDRX1F (...);
+module ODDRX1F(SCLK, RST, D0, D1, Q);
     parameter GSR = "ENABLED";
     input SCLK;
     input RST;
@@ -1201,7 +1239,7 @@ module ODDRX1F (...);
 endmodule
 
 (* blackbox *)
-module ODDRX2F (...);
+module ODDRX2F(SCLK, ECLK, RST, D3, D2, D1, D0, Q);
     parameter GSR = "ENABLED";
     input SCLK;
     input ECLK;
@@ -1214,7 +1252,7 @@ module ODDRX2F (...);
 endmodule
 
 (* blackbox *)
-module ODDR71B (...);
+module ODDR71B(SCLK, ECLK, RST, D6, D5, D4, D3, D2, D1, D0, Q);
     parameter GSR = "ENABLED";
     input SCLK;
     input ECLK;
@@ -1230,7 +1268,7 @@ module ODDR71B (...);
 endmodule
 
 (* blackbox *)
-module OSHX2A (...);
+module OSHX2A(D1, D0, SCLK, ECLK, RST, Q);
     parameter GSR = "ENABLED";
     input D1;
     input D0;
@@ -1241,7 +1279,7 @@ module OSHX2A (...);
 endmodule
 
 (* blackbox *)
-module TSHX2DQA (...);
+module TSHX2DQA(T1, T0, SCLK, ECLK, DQSW270, RST, Q);
     parameter GSR = "ENABLED";
     parameter REGSET = "SET";
     input T1;
@@ -1254,7 +1292,7 @@ module TSHX2DQA (...);
 endmodule
 
 (* blackbox *)
-module TSHX2DQSA (...);
+module TSHX2DQSA(T1, T0, SCLK, ECLK, DQSW, RST, Q);
     parameter GSR = "ENABLED";
     parameter REGSET = "SET";
     input T1;
@@ -1267,7 +1305,7 @@ module TSHX2DQSA (...);
 endmodule
 
 (* blackbox *)
-module ODDRX2DQA (...);
+module ODDRX2DQA(D3, D2, D1, D0, DQSW270, SCLK, ECLK, RST, Q);
     parameter GSR = "ENABLED";
     input D3;
     input D2;
@@ -1281,7 +1319,7 @@ module ODDRX2DQA (...);
 endmodule
 
 (* blackbox *)
-module ODDRX2DQSB (...);
+module ODDRX2DQSB(D3, D2, D1, D0, SCLK, ECLK, DQSW, RST, Q);
     parameter GSR = "ENABLED";
     input D3;
     input D2;
@@ -1295,7 +1333,8 @@ module ODDRX2DQSB (...);
 endmodule
 
 (* blackbox *)
-module EHXPLLL (...);
+module EHXPLLL(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG, STDBY, PLLWAKESYNC, RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK
+, CLKINTFB);
     parameter CLKI_DIV = 1;
     parameter CLKFB_DIV = 1;
     parameter CLKOP_DIV = 8;
@@ -1357,7 +1396,7 @@ module EHXPLLL (...);
 endmodule
 
 (* blackbox *)
-module DTR (...);
+module DTR(STARTPULSE, DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0);
     parameter DTR_TEMP = 25;
     input STARTPULSE;
     output DTROUT7;
@@ -1371,13 +1410,13 @@ module DTR (...);
 endmodule
 
 (* blackbox *)
-module OSCG (...);
+module OSCG(OSC);
     parameter DIV = 128;
     output OSC;
 endmodule
 
 (* blackbox *)
-module EXTREFB (...);
+module EXTREFB(REFCLKP, REFCLKN, REFCLKO);
     parameter REFCK_PWDNB = "DONTCARE";
     parameter REFCK_RTERM = "DONTCARE";
     parameter REFCK_DCBIAS_EN = "DONTCARE";
@@ -1389,7 +1428,7 @@ module EXTREFB (...);
 endmodule
 
 (* blackbox *) (* keep *)
-module JTAGG (...);
+module JTAGG(TCK, TMS, TDI, JTDO2, JTDO1, TDO, JTDI, JTCK, JRTI2, JRTI1, JSHIFT, JUPDATE, JRSTN, JCE2, JCE1);
     parameter ER1 = "ENABLED";
     parameter ER2 = "ENABLED";
     (* iopad_external_pin *)
@@ -1414,7 +1453,20 @@ module JTAGG (...);
 endmodule
 
 (* blackbox *) (* keep *)
-module DCUA (...);
+module DCUA(CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN, D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND, CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK, CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2
+, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3, CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7, CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11, CH0_FF_TX_D_12, CH1_FF_TX_D_12
+, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15, CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19, CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23
+, CH1_FF_TX_D_23, CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX, CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP, CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX
+, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE, CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST, CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB
+, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX, D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7, D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX, CH0_SCIEN, CH1_SCIEN
+, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE, D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0, D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7
+, D_SCAN_MODE, D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6, D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11, CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND
+, D_TXPLL_LOL_TO_ND, CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK, CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1, CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3
+, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5, CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9, CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13, CH0_FF_RX_D_14
+, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17, CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21, CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE
+, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON, CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN, CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED, CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE
+, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3, D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7, D_COUT0, D_COUT1, D_COUT2
+, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19, D_REFCLKI, D_FFS_PLOL);
     parameter D_MACROPDB = "DONTCARE";
     parameter D_IB_PWDNB = "DONTCARE";
     parameter D_XGE_MODE = "DONTCARE";