yowasp-yosys 0.60.0.0.post1055__py3-none-any.whl → 0.61.0.0.post1073__py3-none-any.whl

yowasp_yosys/share/gowin/brams.txt

@@ -2,6 +2,7 @@ ram block $__GOWIN_SP_ {
 	abits 14;
 	widths 1 2 4 9 18 36 per_port;
 	cost 128;
+	byte 9;
 	init no_undef;
 	port srsw "A" {
 		clock posedge;
@@ -24,6 +25,7 @@ ram block $__GOWIN_SP_ {
 				rdwr old;
 			}
 		}
+		wrbe_separate;
 	}
 }
 
@@ -31,6 +33,7 @@ ram block $__GOWIN_DP_ {
 	abits 14;
 	widths 1 2 4 9 18 per_port;
 	cost 128;
+	byte 9;
 	init no_undef;
 	port srsw "A" "B" {
 		clock posedge;
@@ -53,6 +56,7 @@ ram block $__GOWIN_DP_ {
 				rdwr old;
 			}
 		}
+		wrbe_separate;
 	}
 }
 
@@ -60,6 +64,7 @@ ram block $__GOWIN_SDP_ {
 	abits 14;
 	widths 1 2 4 9 18 36 per_port;
 	cost 128;
+	byte 9;
 	init no_undef;
 	port sr "R" {
 		clock posedge;
@@ -75,5 +80,6 @@ ram block $__GOWIN_SDP_ {
 	port sw "W" {
 		clock posedge;
 		clken;
+		wrbe_separate;
 	}
 }

yowasp_yosys/share/gowin/brams_map.v

@@ -14,7 +14,7 @@
 `define x8_width(width) (width / 9 * 8 + width % 9)
 `define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]}
 `define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]}
-`define addrbe_always(width, addr) (width < 18 ? addr :  width == 18 ? {addr[13:4], 4'b0011} : {addr[13:5], 5'b01111})
+`define addrbe(width, addr, w_be) (width < 18 ? addr :  width == 18 ? {addr[13:4], 2'b00, w_be[1:0]} : {addr[13:5], 1'b0, w_be[3:0]})
 
 
 `define INIT(func) \
@@ -90,6 +90,7 @@ parameter OPTION_RESET_MODE = "SYNC";
 
 parameter PORT_A_WIDTH = 36;
 parameter PORT_A_OPTION_WRITE_MODE = 0;
+parameter PORT_A_WR_BE_WIDTH = 4;
 
 input PORT_A_CLK;
 input PORT_A_CLK_EN;
@@ -97,13 +98,14 @@ input PORT_A_WR_EN;
 input PORT_A_RD_SRST;
 input PORT_A_RD_ARST;
 input [13:0] PORT_A_ADDR;
+input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
 input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
 output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
 
 `DEF_FUNCS
 
 wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
-wire [13:0] AD = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);
+wire [13:0] AD = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);
 
 generate
 
@@ -173,9 +175,11 @@ parameter OPTION_RESET_MODE = "SYNC";
 
 parameter PORT_A_WIDTH = 18;
 parameter PORT_A_OPTION_WRITE_MODE = 0;
+parameter PORT_A_WR_BE_WIDTH = 4;
 
 parameter PORT_B_WIDTH = 18;
 parameter PORT_B_OPTION_WRITE_MODE = 0;
+parameter PORT_B_WR_BE_WIDTH = 4;
 
 input PORT_A_CLK;
 input PORT_A_CLK_EN;
@@ -183,6 +187,7 @@ input PORT_A_WR_EN;
 input PORT_A_RD_SRST;
 input PORT_A_RD_ARST;
 input [13:0] PORT_A_ADDR;
+input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
 input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
 output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
 
@@ -192,6 +197,7 @@ input PORT_B_WR_EN;
 input PORT_B_RD_SRST;
 input PORT_B_RD_ARST;
 input [13:0] PORT_B_ADDR;
+input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;
 input [PORT_A_WIDTH-1:0] PORT_B_WR_DATA;
 output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;
 
@@ -199,8 +205,8 @@ output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;
 
 wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
 wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST;
-wire [13:0] ADA = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);
-wire [13:0] ADB = `addrbe_always(PORT_B_WIDTH, PORT_B_ADDR);
+wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_B_WR_BE);
+wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE);
 
 generate
 
@@ -306,6 +312,7 @@ parameter OPTION_RESET_MODE = "SYNC";
 
 parameter PORT_R_WIDTH = 18;
 parameter PORT_W_WIDTH = 18;
+parameter PORT_W_WR_BE_WIDTH = 4;
 
 input PORT_R_CLK;
 input PORT_R_CLK_EN;
@@ -318,12 +325,13 @@ input PORT_W_CLK;
 input PORT_W_CLK_EN;
 input PORT_W_WR_EN;
 input [13:0] PORT_W_ADDR;
+input [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE;
 input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
 
 `DEF_FUNCS
 
 wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST;
-wire [13:0] ADW = `addrbe_always(PORT_W_WIDTH, PORT_W_ADDR);
+wire [13:0] ADW = `addrbe(PORT_W_WIDTH, PORT_W_ADDR, PORT_W_WR_BE);
 wire WRE = PORT_W_CLK_EN & PORT_W_WR_EN;
 
 generate

yowasp_yosys/share/gowin/brams_map_gw5a.v

@@ -14,7 +14,7 @@
 `define x8_width(width) (width / 9 * 8 + width % 9)
 `define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]}
 `define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]}
-`define addrbe_always(width, addr) (width < 18 ? addr :  width == 18 ? {addr[13:4], 4'b0011} : {addr[13:5], 5'b01111})
+`define addrbe(width, addr, w_be) (width < 18 ? addr :  width == 18 ? {addr[13:4], 2'b00, w_be[1:0]} : {addr[13:5], 1'b0, w_be[3:0]})
 
 
 `define INIT(func) \
@@ -90,6 +90,7 @@ parameter OPTION_RESET_MODE = "SYNC";
 
 parameter PORT_A_WIDTH = 36;
 parameter PORT_A_OPTION_WRITE_MODE = 0;
+parameter PORT_A_WR_BE_WIDTH = 4;
 
 input PORT_A_CLK;
 input PORT_A_CLK_EN;
@@ -97,13 +98,14 @@ input PORT_A_WR_EN;
 input PORT_A_RD_SRST;
 input PORT_A_RD_ARST;
 input [13:0] PORT_A_ADDR;
+input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
 input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
 output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
 
 `DEF_FUNCS
 
 wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
-wire [13:0] AD = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);
+wire [13:0] AD = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);
 
 generate
 
@@ -173,9 +175,11 @@ parameter OPTION_RESET_MODE = "SYNC";
 
 parameter PORT_A_WIDTH = 18;
 parameter PORT_A_OPTION_WRITE_MODE = 0;
+parameter PORT_A_WR_BE_WIDTH = 4;
 
 parameter PORT_B_WIDTH = 18;
 parameter PORT_B_OPTION_WRITE_MODE = 0;
+parameter PORT_B_WR_BE_WIDTH = 4;
 
 input PORT_A_CLK;
 input PORT_A_CLK_EN;
@@ -183,6 +187,7 @@ input PORT_A_WR_EN;
 input PORT_A_RD_SRST;
 input PORT_A_RD_ARST;
 input [13:0] PORT_A_ADDR;
+input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
 input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
 output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
 
@@ -192,6 +197,7 @@ input PORT_B_WR_EN;
 input PORT_B_RD_SRST;
 input PORT_B_RD_ARST;
 input [13:0] PORT_B_ADDR;
+input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE;
 input [PORT_A_WIDTH-1:0] PORT_B_WR_DATA;
 output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;
 
@@ -199,8 +205,8 @@ output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;
 
 wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
 wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST;
-wire [13:0] ADA = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);
-wire [13:0] ADB = `addrbe_always(PORT_B_WIDTH, PORT_B_ADDR);
+wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_B_WR_BE);
+wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE);
 
 generate
 
@@ -306,6 +312,7 @@ parameter OPTION_RESET_MODE = "SYNC";
 
 parameter PORT_R_WIDTH = 18;
 parameter PORT_W_WIDTH = 18;
+parameter PORT_W_WR_BE_WIDTH = 4;
 
 input PORT_R_CLK;
 input PORT_R_CLK_EN;
@@ -318,12 +325,13 @@ input PORT_W_CLK;
 input PORT_W_CLK_EN;
 input PORT_W_WR_EN;
 input [13:0] PORT_W_ADDR;
+input [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE;
 input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
 
 `DEF_FUNCS
 
 wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST;
-wire [13:0] ADW = `addrbe_always(PORT_W_WIDTH, PORT_W_ADDR);
+wire [13:0] ADW = `addrbe(PORT_W_WIDTH, PORT_W_ADDR, PORT_W_WR_BE);
 wire WRE = PORT_W_CLK_EN & PORT_W_WR_EN;
 
 generate

yowasp_yosys/share/include/kernel/celltypes.h

@@ -305,18 +305,18 @@ struct CellTypes
 		cell_types.clear();
 	}
 
-	bool cell_known(const RTLIL::IdString &type) const
+	bool cell_known(RTLIL::IdString type) const
 	{
 		return cell_types.count(type) != 0;
 	}
 
-	bool cell_output(const RTLIL::IdString &type, const RTLIL::IdString &port) const
+	bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const
 	{
 		auto it = cell_types.find(type);
 		return it != cell_types.end() && it->second.outputs.count(port) != 0;
 	}
 
-	bool cell_input(const RTLIL::IdString &type, const RTLIL::IdString &port) const
+	bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const
 	{
 		auto it = cell_types.find(type);
 		return it != cell_types.end() && it->second.inputs.count(port) != 0;
@@ -332,7 +332,7 @@ struct CellTypes
 		return RTLIL::PortDir(is_input + is_output * 2);
 	}
 
-	bool cell_evaluable(const RTLIL::IdString &type) const
+	bool cell_evaluable(RTLIL::IdString type) const
 	{
 		auto it = cell_types.find(type);
 		return it != cell_types.end() && it->second.is_evaluable;

yowasp_yosys/share/include/kernel/hashlib.h

@@ -1321,6 +1321,12 @@ public:
 		return i < 0 ? 0 : 1;
 	}
 
+	int lookup(const K &key) const
+	{
+		Hasher::hash_t hash = database.do_hash(key);
+		return database.do_lookup_no_rehash(key, hash);
+	}
+
 	void expect(const K &key, int i)
 	{
 		int j = (*this)(key);

yowasp_yosys/share/include/kernel/log.h

@@ -291,54 +291,6 @@ void log_abort_internal(const char *file, int line);
 #define log_ping() YOSYS_NAMESPACE_PREFIX log("-- %s:%d %s --\n", __FILE__, __LINE__, __PRETTY_FUNCTION__)
 
 
-// ---------------------------------------------------
-// This is the magic behind the code coverage counters
-// ---------------------------------------------------
-
-#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__))
-
-#define cover(_id) do { \
-    static CoverData __d __attribute__((section("yosys_cover_list"), aligned(1), used)) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \
-    __d.counter.fetch_add(1, std::memory_order_relaxed); \
-} while (0)
-
-struct CoverData {
-	const char *file, *func, *id;
-	int line;
-	std::atomic<int> counter;
-};
-
-// this two symbols are created by the linker __start_yosys_cover_listfor the "yosys_cover_list" ELF section
-extern "C" struct CoverData __start_yosys_cover_list[];
-extern "C" struct CoverData __stop_yosys_cover_list[];
-
-extern dict<std::string, std::pair<std::string, int>> extra_coverage_data;
-
-void cover_extra(std::string parent, std::string id, bool increment = true);
-dict<std::string, std::pair<std::string, int>> get_coverage_data();
-
-#define cover_list(_id, ...) do { cover(_id); \
-	std::string r = cover_list_worker(_id, __VA_ARGS__); \
-	log_assert(r.empty()); \
-} while (0)
-
-static inline std::string cover_list_worker(std::string, std::string last) {
-	return last;
-}
-
-template<typename... T>
-std::string cover_list_worker(std::string prefix, std::string first, T... rest) {
-	std::string selected = cover_list_worker(prefix, rest...);
-	cover_extra(prefix, prefix + "." + first, first == selected);
-	return first == selected ? "" : selected;
-}
-
-#else
-#  define cover(...) do { } while (0)
-#  define cover_list(...) do { } while (0)
-#endif
-
-
 // ------------------------------------------------------------
 // everything below this line are utilities for troubleshooting
 // ------------------------------------------------------------

yowasp_yosys/share/include/kernel/modtools.h

@@ -161,7 +161,7 @@ struct ModIndex : public RTLIL::Monitor
 #endif
 	}
 
-	void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
+	void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
 	{
 		log_assert(module == cell->module);
 

yowasp_yosys/share/include/kernel/rtlil.h

@@ -223,8 +223,8 @@ struct RTLIL::IdString
 
 	constexpr inline IdString() : index_(0) { }
 	inline IdString(const char *str) : index_(insert(std::string_view(str))) { }
-	constexpr inline IdString(const IdString &str) : index_(str.index_) { }
-	inline IdString(IdString &&str) : index_(str.index_) { str.index_ = 0; }
+	constexpr IdString(const IdString &str) = default;
+	IdString(IdString &&str) = default;
 	inline IdString(const std::string &str) : index_(insert(std::string_view(str))) { }
 	inline IdString(std::string_view str) : index_(insert(str)) { }
 	constexpr inline IdString(StaticId id) : index_(static_cast<short>(id)) {}
@@ -241,8 +241,6 @@ struct RTLIL::IdString
 		*this = id;
 	}
 
-	constexpr inline const IdString &id_string() const { return *this; }
-
 	inline const char *c_str() const {
 		if (index_ >= 0)
 			return global_id_storage_.at(index_).buf;
@@ -372,7 +370,7 @@ struct RTLIL::IdString
 		return Substrings(global_autoidx_id_storage_.at(index_).prefix, -index_);
 	}
 
-	inline bool lt_by_name(const IdString &rhs) const {
+	inline bool lt_by_name(IdString rhs) const {
 		Substrings lhs_it = substrings();
 		Substrings rhs_it = rhs.substrings();
 		std::string_view lhs_substr = lhs_it.first();
@@ -399,12 +397,12 @@ struct RTLIL::IdString
 		}
 	}
 
-	inline bool operator<(const IdString &rhs) const {
+	inline bool operator<(IdString rhs) const {
 		return index_ < rhs.index_;
 	}
 
-	inline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }
-	inline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }
+	inline bool operator==(IdString rhs) const { return index_ == rhs.index_; }
+	inline bool operator!=(IdString rhs) const { return index_ != rhs.index_; }
 
 	// The methods below are just convenience functions for better compatibility with std::string.
 
@@ -528,7 +526,7 @@ struct RTLIL::IdString
 		return (... || in(args));
 	}
 
-	bool in(const IdString &rhs) const { return *this == rhs; }
+	bool in(IdString rhs) const { return *this == rhs; }
 	bool in(const char *rhs) const { return *this == rhs; }
 	bool in(const std::string &rhs) const { return *this == rhs; }
 	inline bool in(const pool<IdString> &rhs) const;
@@ -646,13 +644,13 @@ private:
 namespace hashlib {
 	template <>
 	struct hash_ops<RTLIL::IdString> {
-		static inline bool cmp(const RTLIL::IdString &a, const RTLIL::IdString &b) {
+		static inline bool cmp(RTLIL::IdString a, RTLIL::IdString b) {
 			return a == b;
 		}
-		[[nodiscard]] static inline Hasher hash(const RTLIL::IdString &id) {
+		[[nodiscard]] static inline Hasher hash(RTLIL::IdString id) {
 			return id.hash_top();
 		}
-		[[nodiscard]] static inline Hasher hash_into(const RTLIL::IdString &id, Hasher h) {
+		[[nodiscard]] static inline Hasher hash_into(RTLIL::IdString id, Hasher h) {
 			return id.hash_into(h);
 		}
 	};
@@ -759,11 +757,11 @@ namespace RTLIL {
 		return str.substr(1);
 	}
 
-	static inline std::string unescape_id(const RTLIL::IdString &str) {
+	static inline std::string unescape_id(RTLIL::IdString str) {
 		return unescape_id(str.str());
 	}
 
-	static inline const char *id2cstr(const RTLIL::IdString &str) {
+	static inline const char *id2cstr(RTLIL::IdString str) {
 		return log_id(str);
 	}
 
@@ -780,7 +778,7 @@ namespace RTLIL {
 	};
 
 	struct sort_by_id_str {
-		bool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {
+		bool operator()(RTLIL::IdString a, RTLIL::IdString b) const {
 			return a.lt_by_name(b);
 		}
 	};
@@ -1246,22 +1244,22 @@ struct RTLIL::AttrObject
 {
 	dict<RTLIL::IdString, RTLIL::Const> attributes;
 
-	bool has_attribute(const RTLIL::IdString &id) const;
+	bool has_attribute(RTLIL::IdString id) const;
 
-	void set_bool_attribute(const RTLIL::IdString &id, bool value=true);
-	bool get_bool_attribute(const RTLIL::IdString &id) const;
+	void set_bool_attribute(RTLIL::IdString id, bool value=true);
+	bool get_bool_attribute(RTLIL::IdString id) const;
 
 	[[deprecated("Use Module::get_blackbox_attribute() instead.")]]
 	bool get_blackbox_attribute(bool ignore_wb=false) const {
 		return get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));
 	}
 
-	void set_string_attribute(const RTLIL::IdString& id, string value);
-	string get_string_attribute(const RTLIL::IdString &id) const;
+	void set_string_attribute(RTLIL::IdString  id, string value);
+	string get_string_attribute(RTLIL::IdString id) const;
 
-	void set_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);
-	void add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);
-	pool<string> get_strpool_attribute(const RTLIL::IdString &id) const;
+	void set_strpool_attribute(RTLIL::IdString  id, const pool<string> &data);
+	void add_strpool_attribute(RTLIL::IdString  id, const pool<string> &data);
+	pool<string> get_strpool_attribute(RTLIL::IdString id) const;
 
 	void set_src_attribute(const std::string &src) {
 		set_string_attribute(ID::src, src);
@@ -1273,8 +1271,8 @@ struct RTLIL::AttrObject
 	void set_hdlname_attribute(const vector<string> &hierarchy);
 	vector<string> get_hdlname_attribute() const;
 
-	void set_intvec_attribute(const RTLIL::IdString& id, const vector<int> &data);
-	vector<int> get_intvec_attribute(const RTLIL::IdString &id) const;
+	void set_intvec_attribute(RTLIL::IdString  id, const vector<int> &data);
+	vector<int> get_intvec_attribute(RTLIL::IdString id) const;
 };
 
 struct RTLIL::NamedObject : public RTLIL::AttrObject
@@ -1781,18 +1779,18 @@ struct RTLIL::Selection
 
 	// checks if the given module exists in the current design and is a
 	// boxed module, warning the user if the current design is not set
-	bool boxed_module(const RTLIL::IdString &mod_name) const;
+	bool boxed_module(RTLIL::IdString mod_name) const;
 
 	// checks if the given module is included in this selection
-	bool selected_module(const RTLIL::IdString &mod_name) const;
+	bool selected_module(RTLIL::IdString mod_name) const;
 
 	// checks if the given module is wholly included in this selection,
 	// i.e. not partially selected
-	bool selected_whole_module(const RTLIL::IdString &mod_name) const;
+	bool selected_whole_module(RTLIL::IdString mod_name) const;
 
 	// checks if the given member from the given module is included in this
 	// selection
-	bool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;
+	bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const;
 
 	// optimizes this selection for the given design by:
 	// - removing non-existent modules and members, any boxed modules and
@@ -1862,7 +1860,7 @@ struct RTLIL::Monitor
 	virtual ~Monitor() { }
 	virtual void notify_module_add(RTLIL::Module*) { }
 	virtual void notify_module_del(RTLIL::Module*) { }
-	virtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }
+	virtual void notify_connect(RTLIL::Cell*, RTLIL::IdString, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }
 	virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }
 	virtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }
 	virtual void notify_blackout(RTLIL::Module*) { }
@@ -1897,11 +1895,11 @@ struct RTLIL::Design
 	~Design();
 
 	RTLIL::ObjRange<RTLIL::Module*> modules();
-	RTLIL::Module *module(const RTLIL::IdString &name);
-	const RTLIL::Module *module(const RTLIL::IdString &name) const;
+	RTLIL::Module *module(RTLIL::IdString name);
+	const RTLIL::Module *module(RTLIL::IdString name) const;
 	RTLIL::Module *top_module() const;
 
-	bool has(const RTLIL::IdString &id) const {
+	bool has(RTLIL::IdString id) const {
 		return modules_.count(id) != 0;
 	}
 
@@ -1928,15 +1926,15 @@ struct RTLIL::Design
 	void optimize();
 
 	// checks if the given module is included in the current selection
-	bool selected_module(const RTLIL::IdString &mod_name) const;
+	bool selected_module(RTLIL::IdString mod_name) const;
 
 	// checks if the given module is wholly included in the current
 	// selection, i.e. not partially selected
-	bool selected_whole_module(const RTLIL::IdString &mod_name) const;
+	bool selected_whole_module(RTLIL::IdString mod_name) const;
 
 	// checks if the given member from the given module is included in the
 	// current selection
-	bool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;
+	bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const;
 
 	// checks if the given module is included in the current selection
 	bool selected_module(RTLIL::Module *mod) const;
@@ -2068,7 +2066,7 @@ public:
 	virtual ~Module();
 	virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);
 	virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);
-	virtual size_t count_id(const RTLIL::IdString& id);
+	virtual size_t count_id(RTLIL::IdString id);
 	virtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);
 	virtual bool reprocess_if_necessary(RTLIL::Design *design);
 
@@ -2120,32 +2118,37 @@ public:
 		return design->selected_member(name, member->name);
 	}
 
-	RTLIL::Wire* wire(const RTLIL::IdString &id) {
+	RTLIL::Wire* wire(RTLIL::IdString id) {
 		auto it = wires_.find(id);
 		return it == wires_.end() ? nullptr : it->second;
 	}
-	RTLIL::Cell* cell(const RTLIL::IdString &id) {
+	RTLIL::Cell* cell(RTLIL::IdString id) {
 		auto it = cells_.find(id);
 		return it == cells_.end() ? nullptr : it->second;
 	}
 
-	const RTLIL::Wire* wire(const RTLIL::IdString &id) const{
+	const RTLIL::Wire* wire(RTLIL::IdString id) const{
 		auto it = wires_.find(id);
 		return it == wires_.end() ? nullptr : it->second;
 	}
-	const RTLIL::Cell* cell(const RTLIL::IdString &id) const {
+	const RTLIL::Cell* cell(RTLIL::IdString id) const {
 		auto it = cells_.find(id);
 		return it == cells_.end() ? nullptr : it->second;
 	}
 
 	RTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }
+	int wires_size() const { return wires_.size(); }
+	RTLIL::Wire* wire_at(int index) const { return wires_.element(index)->second; }
 	RTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }
+	int cells_size() const { return cells_.size(); }
+	RTLIL::Cell* cell_at(int index) const { return cells_.element(index)->second; }
 
 	void add(RTLIL::Binding *binding);
 
 	// Removing wires is expensive. If you have to remove wires, remove them all at once.
 	void remove(const pool<RTLIL::Wire*> &wires);
 	void remove(RTLIL::Cell *cell);
+	void remove(RTLIL::Memory *memory);
 	void remove(RTLIL::Process *process);
 
 	void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
@@ -2490,23 +2493,23 @@ public:
 	dict<RTLIL::IdString, RTLIL::Const> parameters;
 
 	// access cell ports
-	bool hasPort(const RTLIL::IdString &portname) const;
-	void unsetPort(const RTLIL::IdString &portname);
-	void setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);
-	const RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;
+	bool hasPort(RTLIL::IdString portname) const;
+	void unsetPort(RTLIL::IdString portname);
+	void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal);
+	const RTLIL::SigSpec &getPort(RTLIL::IdString portname) const;
 	const dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;
 
 	// information about cell ports
 	bool known() const;
-	bool input(const RTLIL::IdString &portname) const;
-	bool output(const RTLIL::IdString &portname) const;
-	PortDir port_dir(const RTLIL::IdString &portname) const;
+	bool input(RTLIL::IdString portname) const;
+	bool output(RTLIL::IdString portname) const;
+	PortDir port_dir(RTLIL::IdString portname) const;
 
 	// access cell parameters
-	bool hasParam(const RTLIL::IdString &paramname) const;
-	void unsetParam(const RTLIL::IdString &paramname);
-	void setParam(const RTLIL::IdString &paramname, RTLIL::Const value);
-	const RTLIL::Const &getParam(const RTLIL::IdString &paramname) const;
+	bool hasParam(RTLIL::IdString paramname) const;
+	void unsetParam(RTLIL::IdString paramname);
+	void setParam(RTLIL::IdString paramname, RTLIL::Const value);
+	const RTLIL::Const &getParam(RTLIL::IdString paramname) const;
 
 	void sort();
 	void check();

yowasp_yosys/share/include/kernel/scopeinfo.h

@@ -433,10 +433,10 @@ enum class ScopeinfoAttrs {
 };
 
 // Check whether the flattened module or flattened cell corresponding to a $scopeinfo cell had a specific attribute.
-bool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);
+bool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, RTLIL::IdString id);
 
 // Get a specific attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.
-RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);
+RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, RTLIL::IdString id);
 
 // Get all attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.
 dict<RTLIL::IdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs);

yowasp_yosys/share/include/kernel/threading.h

@@ -127,9 +127,9 @@ class ThreadPool
 public:
 	// Computes the number of worker threads to use.
 	// `reserved_cores` cores are set aside for other threads (e.g. work on the main thread).
-	// `max_threads` --- don't return more workers than this.
+	// `max_worker_threads` --- don't return more workers than this.
 	// The result may be 0.
-	static int pool_size(int reserved_cores, int max_threads);
+	static int pool_size(int reserved_cores, int max_worker_threads);
 
 	// Create a pool of threads running the given closure (parameterized by thread number).
 	// `pool_size` must be the result of a `pool_size()` call.

yowasp_yosys/share/include/kernel/yosys.h

@@ -81,6 +81,7 @@ extern std::set<std::string> yosys_input_files, yosys_output_files;
 
 // from kernel/version_*.o (cc source generated from Makefile)
 extern const char *yosys_version_str;
+extern const char *yosys_git_hash_str;
 const char* yosys_maybe_version();
 
 // from passes/cmds/design.cc

yowasp_yosys/share/include/kernel/yosys_common.h

@@ -299,8 +299,8 @@ RTLIL::IdString new_id_suffix(std::string_view file, int line, std::string_view
 
 #define NEW_ID \
 	YOSYS_NAMESPACE_PREFIX RTLIL::IdString::new_autoidx_with_prefix([](std::string_view func) -> const std::string * { \
-		static const std::string *prefix = YOSYS_NAMESPACE_PREFIX create_id_prefix(__FILE__, __LINE__, func); \
-		return prefix; \
+		static std::unique_ptr<const std::string> prefix(YOSYS_NAMESPACE_PREFIX create_id_prefix(__FILE__, __LINE__, func)); \
+		return prefix.get(); \
 	}(__FUNCTION__))
 #define NEW_ID_SUFFIX(suffix) \
 	YOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)

{yowasp_yosys-0.60.0.0.post1055.dist-info → yowasp_yosys-0.61.0.0.post1073.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: yowasp-yosys
-Version: 0.60.0.0.post1055
+Version: 0.61.0.0.post1073
 Summary: Yosys Open SYnthesis Suite
 Author-email: Catherine <whitequark@whitequark.org>
 License-Expression: ISC

{yowasp_yosys-0.60.0.0.post1055.dist-info → yowasp_yosys-0.61.0.0.post1073.dist-info}/RECORD

@@ -2,7 +2,7 @@ yowasp_yosys/__init__.py,sha256=cxu6bMlZ6zRpCzKp2wdFs7LNt5-btnJD6ghvdkDs6Y0,1189
 yowasp_yosys/sby.py,sha256=BZwSqLk064cKvGITogDi3OqlQtRJJ-8J4_KG5Z7ktoc,19736
 yowasp_yosys/smtbmc.py,sha256=kFTdW-sYuRU0f4YxRJuwYNIB1b9AFJeXM1sIIBdPJW0,74358
 yowasp_yosys/witness.py,sha256=m3iV2Nydm0p4G79VRaaX3lGul-nGnuxeKnx20MCJgi0,17279
-yowasp_yosys/yosys.wasm,sha256=8x-WIGlfuAP07MDDJRSAmMWVFIbJ_yG__bZC8CKulbA,38249085
+yowasp_yosys/yosys.wasm,sha256=VzvDKtS1s2MRE9p4FnQjQmZijOZjvK7Kh0a9GBCOLj8,38525292
 yowasp_yosys/share/abc9_map.v,sha256=uWDqMpBQTeeadH1BlHVwkCy2StKF892xbgBgMKLK5-w,923
 yowasp_yosys/share/abc9_model.v,sha256=IfMyEGOEUBdZyiVule0wMhrVYVYQpmSIcxygbgtHItI,653
 yowasp_yosys/share/abc9_unmap.v,sha256=w107Y3iJjMU6D_6_aYLf2NziXTnAhpa5_CFAwaYO1iU,638
@@ -71,9 +71,9 @@ yowasp_yosys/share/gatemate/mul_map.v,sha256=K18Fz6kC9mYhBcn0wwGG-K7i84sf_eCE9D8
 yowasp_yosys/share/gatemate/mux_map.v,sha256=nbJ3z5o19Z4Qe5Ts7VRmlhSKpBVB5lLpDzPCRIF0y94,1493
 yowasp_yosys/share/gatemate/reg_map.v,sha256=X9cGplW-ChE81RemEi4t8WsSTadzTV297S78OmH5KUc,1871
 yowasp_yosys/share/gowin/arith_map.v,sha256=zZFw-f2IypjF0RUHVxuY-bsB0BE_0aADYhUAB841jn0,2104
-yowasp_yosys/share/gowin/brams.txt,sha256=oYWuv7DOKabN7_0ITRlW3xDbzyw5NfyoWAiTK19v31w,1193
-yowasp_yosys/share/gowin/brams_map.v,sha256=detpD8qAIJYjyPRYgiWUw4oYVIWGlt70itO5xpgeEOs,8602
-yowasp_yosys/share/gowin/brams_map_gw5a.v,sha256=NbwB-Uq7iOqfpW8cCfXc2CTYavqA0dW0USUjIulm1GQ,8566
+yowasp_yosys/share/gowin/brams.txt,sha256=avNmdWgyelxa2pftPMfyzvm8V7uxooadDTEcukGLXWY,1271
+yowasp_yosys/share/gowin/brams_map.v,sha256=7l1X2NEJX7BRHJuZtNjrRWK64VChsutWbNjZKg9c3vQ,8961
+yowasp_yosys/share/gowin/brams_map_gw5a.v,sha256=5vjsdOUKfUPjsKdVwozOKCO6_JJQtKI69qqSvODlWYA,8925
 yowasp_yosys/share/gowin/cells_map.v,sha256=Zmq2VlZOFBHhUN65j3DOWdgKpKBMoSTiqgYBpx9-j_k,6100
 yowasp_yosys/share/gowin/cells_sim.v,sha256=YkA_QnUhZSQ6albnTBpCVS3nJxgbuRBEd7803XKRGe8,47291
 yowasp_yosys/share/gowin/cells_xtra_gw1n.v,sha256=vg3Aj2q4O32ycnNIH6P-7QHuhm49VoNlnRpkeiSh9rM,63441
@@ -116,7 +116,7 @@ yowasp_yosys/share/include/kernel/binding.h,sha256=BKfMhNf_HflihwCXEqyZuB1zp9xzV
 yowasp_yosys/share/include/kernel/bitpattern.h,sha256=rRRttYNswPAdX9uCvQDXLvtt5CXwINPnv7szPl_Obzc,5499
 yowasp_yosys/share/include/kernel/cellaigs.h,sha256=CdYos67IpmAgLvBbJ8EC3hWg6WhBIBy9jmhdoZ36HVE,1391
 yowasp_yosys/share/include/kernel/celledges.h,sha256=fF_sHJOpN_qQ1P0x8KKoJE9ulDMusfjkF0dBpTMs19E,2216
-yowasp_yosys/share/include/kernel/celltypes.h,sha256=wO-YpmQMvOzSk-sX06kmND3TfsODAbYeqPIfH13uX5A,19355
+yowasp_yosys/share/include/kernel/celltypes.h,sha256=UW-H_c2RAthQrCv1_gYbIRMnQqSB5kQBKl5o8uD2yu0,19313
 yowasp_yosys/share/include/kernel/consteval.h,sha256=lPo6CAW42gdhVLBTd-nBiIp25UrWIzR0f2R0JQo3Dzk,11038
 yowasp_yosys/share/include/kernel/constids.inc,sha256=AaGaUMW3jnbdKfG3RvgrXkQ0aM7M3Y3Wh6FzuzpWwLo,12927
 yowasp_yosys/share/include/kernel/cost.h,sha256=TRW3KGPVLv5MxAmNbSh1mnzwTc-QHvZXSh9Wfc6mw3U,2921
@@ -126,25 +126,25 @@ yowasp_yosys/share/include/kernel/ffinit.h,sha256=3O8XfLnskgmxpMUn9te-HI9XAa_Bab
 yowasp_yosys/share/include/kernel/ffmerge.h,sha256=xl1_h88ZmLIxpli7vpiiU35R_Y4cZq728-A72abuzMg,6309
 yowasp_yosys/share/include/kernel/fmt.h,sha256=0UT-aDVX7_KnzlaNyK3iMsSzoICa4Q0HhqsFIrwHBMw,2790
 yowasp_yosys/share/include/kernel/gzip.h,sha256=wpAZ9hA13HEpWgZnth46JHvVLSA_qdS-JZB5gh83-QA,1847
-yowasp_yosys/share/include/kernel/hashlib.h,sha256=fPOd7Sy-ZAjWOOl2JNEg-f2BB2dobns9OENzZUhefGI,39598
+yowasp_yosys/share/include/kernel/hashlib.h,sha256=-OKaWi9X3NcBbiUwXfSLx9uRtXmLlzNmnNk6qjOLTH8,39734
 yowasp_yosys/share/include/kernel/io.h,sha256=7f9YHpRlplk9cskEYF4ZN7BahXq831McRkuHZ4-PeV4,15791
 yowasp_yosys/share/include/kernel/json.h,sha256=i2wmIMZ2SCE5zc6IIIVLx4XZ2-HQiZEFJ0ao_cMInK0,2849
-yowasp_yosys/share/include/kernel/log.h,sha256=pB-dTx-quNH64wgF9pFKWRDSrqg8M2CwsbDzE27WFbI,17020
+yowasp_yosys/share/include/kernel/log.h,sha256=1OqUlMHuy5SVc1Q9_tuUKAp7279nCnn0LUhyYOrkwGI,15394
 yowasp_yosys/share/include/kernel/macc.h,sha256=pBdSo9tnjpOC77UUqFDzgQMzZCjixdhmOrLnSi9QUeI,8918
 yowasp_yosys/share/include/kernel/mem.h,sha256=2mCPY8QygVoDI1NC-cG0a0xaMwSihpcjfaGEyEDN7vs,15498
-yowasp_yosys/share/include/kernel/modtools.h,sha256=mRnzc5TIsdIbHlFSTk2Yc0y85ttknhK-dAlti3neSI8,14388
+yowasp_yosys/share/include/kernel/modtools.h,sha256=NV-7n9bjHiCCAVJNQiOhJ8_C-6uDryIBAJ1tszd0Byg,14381
 yowasp_yosys/share/include/kernel/qcsat.h,sha256=ibhpJRu0youjDXPllXrDJi851VpwW1kbJ_y94_X6JhU,2804
 yowasp_yosys/share/include/kernel/register.h,sha256=RY6IBb9hTKx9dY11He7eiCBmOEiyGenoD3qof6dJH_I,7987
-yowasp_yosys/share/include/kernel/rtlil.h,sha256=09Q1hJEkq_XD-_1K750JOymES_7B_idU2ZHftFcH27c,116926
+yowasp_yosys/share/include/kernel/rtlil.h,sha256=6PmfMBY3nHo9BRZ4Ygrx6-zHgcKfYUwqlGlTg-OETYo,116736
 yowasp_yosys/share/include/kernel/satgen.h,sha256=KcGW7ofH4_oTw0TtT22-azGaOOc_2yCTsz6N1-AeDiY,10535
-yowasp_yosys/share/include/kernel/scopeinfo.h,sha256=EAU3vSTIwH1RrbSC7HVoTWh4SLfHMSIoidQPvT1Mo7g,11797
+yowasp_yosys/share/include/kernel/scopeinfo.h,sha256=jTvWovLxC7RFGcrMCw6Jj49JqAhEo0kmBHRIsIgLbLo,11783
 yowasp_yosys/share/include/kernel/sexpr.h,sha256=CUDKFehVoGmakYBYLpEKUtlM0Dd3oI6TNW_cKz-qe0g,4720
 yowasp_yosys/share/include/kernel/sigtools.h,sha256=5s1qkeGjV2pbwrWRNaNgay8qHfKzk7TgK1jQM-C2Dco,10652
-yowasp_yosys/share/include/kernel/threading.h,sha256=OidU8rY1QCeTdMR6DD_heUg8BUOj3NjsiQ6cl0A1be0,4656
+yowasp_yosys/share/include/kernel/threading.h,sha256=wUiqdbkcrRPzDJDrMLmzdVP07w8SXZfaG4YM9xXGmEg,4670
 yowasp_yosys/share/include/kernel/timinginfo.h,sha256=JNRktUWp7ow_wn4P5BxlOkv7hNS7qKbws7Gjs6VSUx8,7367
 yowasp_yosys/share/include/kernel/utils.h,sha256=6WTFqPm117PbGUDjQVhFlzSnkuE8N2LfO2RXungS1xo,7925
-yowasp_yosys/share/include/kernel/yosys.h,sha256=g-tNpYJFkJtChmou9eVZxM7BFplJWra7WZ_y7hdRR_o,3454
-yowasp_yosys/share/include/kernel/yosys_common.h,sha256=fPQxbE7bjqcUl5nmHx7DH9uGbtBWe_vjOpQOOeNTJgw,8642
+yowasp_yosys/share/include/kernel/yosys.h,sha256=bZ3-68AzdfhE750rImxzXypMmpl9vHCV29hWZIH9U0c,3493
+yowasp_yosys/share/include/kernel/yosys_common.h,sha256=-CpIYF3XOGZrLBrjV1dAgUFBSVE1r5bZIGzVFYTIrEo,8663
 yowasp_yosys/share/include/kernel/yw.h,sha256=Gr5zqBNUSKXOKhdw7tl9-KcCiZg3xFcK9Msj7LMawdI,5470
 yowasp_yosys/share/include/libs/ezsat/ezminisat.h,sha256=bSrDL6VRinpXdULoR8P9lQaT1Dy4kAEZfTcKjRKOdjg,2098
 yowasp_yosys/share/include/libs/ezsat/ezsat.h,sha256=eggeGwS9pFyxSYGT0RtOqX189pbXFAKDfPZzIYTmqIk,14523
@@ -334,8 +334,8 @@ yowasp_yosys/share/xilinx/xc5v_dsp_map.v,sha256=I4lg0RQ54fBBba_7NNvUgwS4tQ1yLIsU
 yowasp_yosys/share/xilinx/xc6s_dsp_map.v,sha256=gTxHocB-Dn5G4BplWgri_tLhT6DIO2S0X-yu4iBKYyk,562
 yowasp_yosys/share/xilinx/xc7_dsp_map.v,sha256=zrzreQi7mElrAMtrayxtiO_Bw00S6zsjSjSVcjmJPH0,884
 yowasp_yosys/share/xilinx/xcu_dsp_map.v,sha256=gzCgl1emrHGcigVmU0nP0pW7dlhQ01SaWwXzHHcqt-o,882
-yowasp_yosys-0.60.0.0.post1055.dist-info/METADATA,sha256=gGpDRSrohNQfGxdjcwyc84sHRv4vpGVbHNjAT81D41g,2523
-yowasp_yosys-0.60.0.0.post1055.dist-info/WHEEL,sha256=lTU6B6eIfYoiQJTZNc-fyaR6BpL6ehTzU3xGYxn2n8k,91
-yowasp_yosys-0.60.0.0.post1055.dist-info/entry_points.txt,sha256=p_9sIVi2ZqsqgYYo14PywYkwHYTa76fMEq3LxweXJpc,220
-yowasp_yosys-0.60.0.0.post1055.dist-info/top_level.txt,sha256=_yiNT8kLYkcD1TEuUCzQ_MkON1c3xuIRV59zXds4zd4,13
-yowasp_yosys-0.60.0.0.post1055.dist-info/RECORD,,
+yowasp_yosys-0.61.0.0.post1073.dist-info/METADATA,sha256=5ntw83w-zBVuQAGcHkbof_zeAIeGFgd3K2I2V0e6tFc,2523
+yowasp_yosys-0.61.0.0.post1073.dist-info/WHEEL,sha256=lTU6B6eIfYoiQJTZNc-fyaR6BpL6ehTzU3xGYxn2n8k,91
+yowasp_yosys-0.61.0.0.post1073.dist-info/entry_points.txt,sha256=p_9sIVi2ZqsqgYYo14PywYkwHYTa76fMEq3LxweXJpc,220
+yowasp_yosys-0.61.0.0.post1073.dist-info/top_level.txt,sha256=_yiNT8kLYkcD1TEuUCzQ_MkON1c3xuIRV59zXds4zd4,13
+yowasp_yosys-0.61.0.0.post1073.dist-info/RECORD,,