yowasp-yosys 0.56.0.0.post964__py3-none-any.whl → 0.56.0.141.post974.dev0__py3-none-any.whl

yowasp_yosys/share/include/frontends/ast/ast.h

@@ -28,6 +28,7 @@
 
 #include "kernel/rtlil.h"
 #include "kernel/fmt.h"
+#include "frontends/verilog/verilog_location.h"
 #include <stdint.h>
 #include <set>
 
@@ -153,6 +154,7 @@ namespace AST
 		AST_MODPORT,
 		AST_MODPORTMEMBER,
 		AST_PACKAGE,
+		AST_IMPORT,
 
 		AST_WIRETYPE,
 		AST_TYPEDEF,
@@ -162,12 +164,7 @@ namespace AST
 		AST_BIND
 	};
 
-	struct AstSrcLocType {
-		unsigned int first_line, last_line;
-		unsigned int first_column, last_column;
-		AstSrcLocType() : first_line(0), last_line(0), first_column(0), last_column(0) {}
-		AstSrcLocType(int _first_line, int _first_column, int _last_line, int _last_column) : first_line(_first_line), last_line(_last_line), first_column(_first_column), last_column(_last_column) {}
-	};
+	using AstSrcLocType = Location;
 
 	// convert an node type to a string (e.g. for debug output)
 	std::string type2str(AstNodeType type);
@@ -183,10 +180,10 @@ namespace AST
 		AstNodeType type;
 
 		// the list of child nodes for this node
-		std::vector<AstNode*> children;
+		std::vector<std::unique_ptr<AstNode>> children;
 
 		// the list of attributes assigned to this node
-		std::map<RTLIL::IdString, AstNode*> attributes;
+		std::map<RTLIL::IdString, std::unique_ptr<AstNode>> attributes;
 		bool get_bool_attribute(RTLIL::IdString id);
 
 		// node content - most of it is unused in most node types
@@ -212,7 +209,7 @@ namespace AST
 		int unpacked_dimensions;
 
 		// this is set by simplify and used during RTLIL generation
-		AstNode *id2ast;
+		AstNode* id2ast;
 
 		// this is used by simplify to detect if basic analysis has been performed already on the node
 		bool basic_prep;
@@ -223,7 +220,6 @@ namespace AST
 		// this is the original sourcecode location that resulted in this AST node
 		// it is automatically set by the constructor using AST::current_filename and
 		// the AST::get_line_num() callback function.
-		std::string filename;
 		AstSrcLocType location;
 
 		// are we embedded in an lvalue, param?
@@ -234,9 +230,9 @@ namespace AST
 		bool in_param_from_above;
 
 		// creating and deleting nodes
-		AstNode(AstNodeType type = AST_NONE, AstNode *child1 = nullptr, AstNode *child2 = nullptr, AstNode *child3 = nullptr, AstNode *child4 = nullptr);
-		AstNode *clone() const;
-		void cloneInto(AstNode *other) const;
+		AstNode(AstSrcLocType loc, AstNodeType type = AST_NONE, std::unique_ptr<AstNode> child1 = nullptr, std::unique_ptr<AstNode> child2 = nullptr, std::unique_ptr<AstNode> child3 = nullptr, std::unique_ptr<AstNode> child4 = nullptr);
+		std::unique_ptr<AstNode> clone() const;
+		void cloneInto(AstNode &other) const;
 		void delete_children();
 		~AstNode();
 
@@ -265,14 +261,14 @@ namespace AST
 		// it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()
 		bool simplify(bool const_fold, int stage, int width_hint, bool sign_hint);
 		void replace_result_wire_name_in_function(const std::string &from, const std::string &to);
-		AstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init);
+		std::unique_ptr<AstNode> readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init);
 		void expand_genblock(const std::string &prefix);
 		void label_genblks(std::set<std::string>& existing, int &counter);
 		void mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg_places,
 				dict<AstNode*, uint32_t> &mem2reg_flags, dict<AstNode*, uint32_t> &proc_flags, uint32_t &status_flags);
-		bool mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block, AstNode *&async_block);
+		bool mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block, AstNode* async_block);
 		bool mem2reg_check(pool<AstNode*> &mem2reg_set);
-		void mem2reg_remove(pool<AstNode*> &mem2reg_set, vector<AstNode*> &delnodes);
+		void mem2reg_remove(pool<AstNode*> &mem2reg_set);
 		void meminfo(int &mem_width, int &mem_size, int &addr_bits);
 		bool detect_latch(const std::string &var);
 		const RTLIL::Module* lookup_cell_module();
@@ -288,7 +284,7 @@ namespace AST
 		};
 		bool has_const_only_constructs();
 		bool replace_variables(std::map<std::string, varinfo_t> &variables, AstNode *fcall, bool must_succeed);
-		AstNode *eval_const_function(AstNode *fcall, bool must_succeed);
+		std::unique_ptr<AstNode> eval_const_function(AstNode *fcall, bool must_succeed);
 		bool is_simple_const_expr();
 
 		// helper for parsing format strings
@@ -305,29 +301,30 @@ namespace AST
 		std::vector<RTLIL::Binding *> genBindings() const;
 
 		// used by genRTLIL() for detecting expression width and sign
-		void detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real = NULL);
-		void detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real = NULL);
+		void detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real = nullptr);
+		void detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real = nullptr);
 
 		// create RTLIL code for this AST node
 		// for expressions the resulting signal vector is returned
 		// all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module
 		RTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false);
-		RTLIL::SigSpec genWidthRTLIL(int width, bool sgn, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL);
+		RTLIL::SigSpec genWidthRTLIL(int width, bool sgn, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = nullptr);
 
 		// compare AST nodes
 		bool operator==(const AstNode &other) const;
 		bool operator!=(const AstNode &other) const;
 		bool contains(const AstNode *other) const;
+		AstNode operator=(AstNode) = delete;
 
 		// helper functions for creating AST nodes for constants
-		static AstNode *mkconst_int(uint32_t v, bool is_signed, int width = 32);
-		static AstNode *mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed, bool is_unsized);
-		static AstNode *mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed);
-		static AstNode *mkconst_str(const std::vector<RTLIL::State> &v);
-		static AstNode *mkconst_str(const std::string &str);
+		static std::unique_ptr<AstNode> mkconst_int(AstSrcLocType loc, uint32_t v, bool is_signed, int width = 32);
+		static std::unique_ptr<AstNode> mkconst_bits(AstSrcLocType loc, const std::vector<RTLIL::State> &v, bool is_signed, bool is_unsized);
+		static std::unique_ptr<AstNode> mkconst_bits(AstSrcLocType loc, const std::vector<RTLIL::State> &v, bool is_signed);
+		static std::unique_ptr<AstNode> mkconst_str(AstSrcLocType loc, const std::vector<RTLIL::State> &v);
+		static std::unique_ptr<AstNode> mkconst_str(AstSrcLocType loc, const std::string &str);
 
 		// helper function to create an AST node for a temporary register
-		AstNode *mktemp_logic(const std::string &name, AstNode *mod, bool nosync, int range_left, int range_right, bool is_signed);
+		std::unique_ptr<AstNode> mktemp_logic(AstSrcLocType loc, const std::string &name, AstNode *mod, bool nosync, int range_left, int range_right, bool is_signed);
 
 		// helper function for creating sign-extended const objects
 		RTLIL::Const bitsAsConst(int width, bool is_signed);
@@ -356,12 +353,12 @@ namespace AST
 
 		// helper to clone the node with some of its subexpressions replaced with zero (this is used
 		// to evaluate widths of dynamic ranges)
-		AstNode *clone_at_zero();
+		std::unique_ptr<AstNode> clone_at_zero();
 
-		void set_attribute(RTLIL::IdString key, AstNode *node)
+		void set_attribute(RTLIL::IdString key, std::unique_ptr<AstNode> node)
 		{
-			attributes[key] = node;
 			node->set_in_param_flag(true);
+			attributes[key] = std::move(node);
 		}
 
 		// helper to set in_lvalue/in_param flags from the hierarchy context (the actual flag
@@ -377,7 +374,7 @@ namespace AST
 		void fixup_hierarchy_flags(bool force_descend = false);
 
 		// helpers for indexing
-		AstNode *make_index_range(AstNode *node, bool unpacked_range = false);
+		std::unique_ptr<AstNode> make_index_range(AstNode *node, bool unpacked_range = false);
 		AstNode *get_struct_member() const;
 
 		// helper to print errors from simplify/genrtlil code
@@ -391,12 +388,11 @@ namespace AST
 	// parametric modules are supported directly by the AST library
 	// therefore we need our own derivate of RTLIL::Module with overloaded virtual functions
 	struct AstModule : RTLIL::Module {
-		AstNode *ast;
+		std::unique_ptr<AstNode> ast;
 		bool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire;
-		~AstModule() override;
 		RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail) override;
 		RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override;
-		std::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, AstNode **new_ast_out, bool quiet = false);
+		std::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, std::unique_ptr<AstNode>* new_ast_out, bool quiet = false);
 		void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;
 		bool reprocess_if_necessary(RTLIL::Design *design) override;
 		RTLIL::Module *clone() const override;
@@ -406,9 +402,9 @@ namespace AST
 	// this must be set by the language frontend before parsing the sources
 	// the AstNode constructor then uses current_filename and get_line_num()
 	// to initialize the filename and linenum properties of new nodes
-	extern std::string current_filename;
-	extern void (*set_line_num)(int);
-	extern int (*get_line_num)();
+	// extern std::string current_filename;
+	// also set by the language frontend to control some AST processing
+	extern bool sv_mode_but_global_and_used_for_literally_one_condition;
 
 	// for stats
 	unsigned long long astnode_count();
@@ -418,7 +414,7 @@ namespace AST
 	void use_internal_line_num();
 
 	// call a DPI function
-	AstNode *dpi_call(const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<AstNode*> &args);
+	std::unique_ptr<AstNode> dpi_call(AstSrcLocType loc, const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<std::unique_ptr<AstNode>> &args);
 
 	// Helper functions related to handling SystemVerilog interfaces
 	std::pair<std::string,std::string> split_modport_from_type(std::string name_type);
@@ -464,7 +460,7 @@ namespace AST_INTERNAL
 	process_and_replace_module(RTLIL::Design *design,
 	                           RTLIL::Module *old_module,
 	                           AST::AstNode *new_ast,
-	                           AST::AstNode *original_ast = nullptr);
+	                           std::unique_ptr<AST::AstNode> original_ast = nullptr);
 }
 
 YOSYS_NAMESPACE_END

yowasp_yosys/share/include/kernel/celltypes.h

@@ -334,6 +334,7 @@ struct CellTypes
 		return v;
 	}
 
+	// Consider using the ConstEval struct instead if you need named ports and/or multiple outputs
 	static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr)
 	{
 		if (type == ID($sshr) && !signed1)
@@ -416,6 +417,7 @@ struct CellTypes
 		log_abort();
 	}
 
+	// Consider using the ConstEval struct instead if you need named ports and/or multiple outputs
 	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)
 	{
 		if (cell->type == ID($slice)) {
@@ -503,10 +505,13 @@ struct CellTypes
 		return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);
 	}
 
+	// Consider using the ConstEval struct instead if you need named ports and/or multiple outputs
 	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr)
 	{
 		if (cell->type.in(ID($mux), ID($_MUX_)))
 			return const_mux(arg1, arg2, arg3);
+		if (cell->type == ID($_NMUX_))
+			return eval_not(const_mux(arg1, arg2, arg3));
 		if (cell->type == ID($bwmux))
 			return const_bwmux(arg1, arg2, arg3);
 		if (cell->type == ID($pmux))
@@ -520,6 +525,7 @@ struct CellTypes
 		return eval(cell, arg1, arg2, errp);
 	}
 
+	// Consider using the ConstEval struct instead if you need named ports and/or multiple outputs
 	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr)
 	{
 		if (cell->type == ID($_AOI4_))

yowasp_yosys/share/include/kernel/consteval.h

@@ -349,7 +349,11 @@ struct ConstEval
 				return false;
 
 			bool eval_err = false;
-			RTLIL::Const eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_c.as_const(), sig_d.as_const(), &eval_err);
+			RTLIL::Const eval_ret;
+			if (sig_s.size() > 0 && eval(sig_s, undef, cell)) {
+				eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_s.as_const(), &eval_err);
+			} else
+				eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_c.as_const(), sig_d.as_const(), &eval_err);
 
 			if (eval_err)
 				return false;

yowasp_yosys/share/include/kernel/ffinit.h

@@ -27,10 +27,10 @@ YOSYS_NAMESPACE_BEGIN
 
 struct FfInitVals
 {
-	const SigMap *sigmap;
+	const SigMapView *sigmap;
 	dict<SigBit, std::pair<State,SigBit>> initbits;
 
-	void set(const SigMap *sigmap_, RTLIL::Module *module)
+	void set(const SigMapView *sigmap_, RTLIL::Module *module)
 	{
 		sigmap = sigmap_;
 		initbits.clear();
@@ -126,7 +126,7 @@ struct FfInitVals
 		initbits.clear();
 	}
 
-	FfInitVals (const SigMap *sigmap, RTLIL::Module *module)
+	FfInitVals (const SigMapView *sigmap, RTLIL::Module *module)
 	{
 		set(sigmap, module);
 	}

yowasp_yosys/share/include/kernel/ffmerge.h

@@ -58,7 +58,7 @@ YOSYS_NAMESPACE_BEGIN
 
 struct FfMergeHelper
 {
-	const SigMap *sigmap;
+	const SigMapView *sigmap;
 	RTLIL::Module *module;
 	FfInitVals *initvals;
 

yowasp_yosys/share/include/kernel/hashlib.h

@@ -451,16 +451,21 @@ class dict {
 		return 1;
 	}
 
-	int do_lookup(const K &key, Hasher::hash_t &hash) const
+	int do_lookup(const K &key, Hasher::hash_t &hash)
 	{
 		if (hashtable.empty())
 			return -1;
 
 		if (entries.size() * hashtable_size_trigger > hashtable.size()) {
-			((dict*)this)->do_rehash();
+			do_rehash();
 			hash = do_hash(key);
 		}
 
+		return do_lookup_internal(key, hash);
+	}
+
+	int do_lookup_internal(const K &key, Hasher::hash_t hash) const
+	{
 		int index = hashtable[hash];
 
 		while (index >= 0 && !ops.cmp(entries[index].udata.first, key)) {
@@ -471,6 +476,14 @@ class dict {
 		return index;
 	}
 
+	int do_lookup_no_rehash(const K &key, Hasher::hash_t hash) const
+	{
+		if (hashtable.empty())
+			return -1;
+
+		return do_lookup_internal(key, hash);
+	}
+
 	int do_insert(const K &key, Hasher::hash_t &hash)
 	{
 		if (hashtable.empty()) {
@@ -694,14 +707,14 @@ public:
 	int count(const K &key) const
 	{
 		Hasher::hash_t hash = do_hash(key);
-		int i = do_lookup(key, hash);
+		int i = do_lookup_no_rehash(key, hash);
 		return i < 0 ? 0 : 1;
 	}
 
 	int count(const K &key, const_iterator it) const
 	{
 		Hasher::hash_t hash = do_hash(key);
-		int i = do_lookup(key, hash);
+		int i = do_lookup_no_rehash(key, hash);
 		return i < 0 || i > it.index ? 0 : 1;
 	}
 
@@ -717,7 +730,7 @@ public:
 	const_iterator find(const K &key) const
 	{
 		Hasher::hash_t hash = do_hash(key);
-		int i = do_lookup(key, hash);
+		int i = do_lookup_no_rehash(key, hash);
 		if (i < 0)
 			return end();
 		return const_iterator(this, i);
@@ -735,7 +748,7 @@ public:
 	const T& at(const K &key) const
 	{
 		Hasher::hash_t hash = do_hash(key);
-		int i = do_lookup(key, hash);
+		int i = do_lookup_no_rehash(key, hash);
 		if (i < 0)
 			throw std::out_of_range("dict::at()");
 		return entries[i].udata.second;
@@ -744,7 +757,7 @@ public:
 	const T& at(const K &key, const T &defval) const
 	{
 		Hasher::hash_t hash = do_hash(key);
-		int i = do_lookup(key, hash);
+		int i = do_lookup_no_rehash(key, hash);
 		if (i < 0)
 			return defval;
 		return entries[i].udata.second;
@@ -906,16 +919,21 @@ protected:
 		return 1;
 	}
 
-	int do_lookup(const K &key, Hasher::hash_t &hash) const
+	int do_lookup(const K &key, Hasher::hash_t &hash)
 	{
 		if (hashtable.empty())
 			return -1;
 
 		if (entries.size() * hashtable_size_trigger > hashtable.size()) {
-			((pool*)this)->do_rehash();
+			do_rehash();
 			hash = do_hash(key);
 		}
 
+		return do_lookup_internal(key, hash);
+	}
+
+	int do_lookup_internal(const K &key, Hasher::hash_t hash) const
+	{
 		int index = hashtable[hash];
 
 		while (index >= 0 && !ops.cmp(entries[index].udata, key)) {
@@ -926,6 +944,14 @@ protected:
 		return index;
 	}
 
+	int do_lookup_no_rehash(const K &key, Hasher::hash_t hash) const
+	{
+		if (hashtable.empty())
+			return -1;
+
+		return do_lookup_internal(key, hash);
+	}
+
 	int do_insert(const K &value, Hasher::hash_t &hash)
 	{
 		if (hashtable.empty()) {
@@ -1087,14 +1113,14 @@ public:
 	int count(const K &key) const
 	{
 		Hasher::hash_t hash = do_hash(key);
-		int i = do_lookup(key, hash);
+		int i = do_lookup_no_rehash(key, hash);
 		return i < 0 ? 0 : 1;
 	}
 
 	int count(const K &key, const_iterator it) const
 	{
 		Hasher::hash_t hash = do_hash(key);
-		int i = do_lookup(key, hash);
+		int i = do_lookup_no_rehash(key, hash);
 		return i < 0 || i > it.index ? 0 : 1;
 	}
 
@@ -1110,7 +1136,7 @@ public:
 	const_iterator find(const K &key) const
 	{
 		Hasher::hash_t hash = do_hash(key);
-		int i = do_lookup(key, hash);
+		int i = do_lookup_no_rehash(key, hash);
 		if (i < 0)
 			return end();
 		return const_iterator(this, i);
@@ -1222,7 +1248,7 @@ public:
 	int at(const K &key) const
 	{
 		Hasher::hash_t hash = database.do_hash(key);
-		int i = database.do_lookup(key, hash);
+		int i = database.do_lookup_no_rehash(key, hash);
 		if (i < 0)
 			throw std::out_of_range("idict::at()");
 		return i + offset;
@@ -1231,7 +1257,7 @@ public:
 	int at(const K &key, int defval) const
 	{
 		Hasher::hash_t hash = database.do_hash(key);
-		int i = database.do_lookup(key, hash);
+		int i = database.do_lookup_no_rehash(key, hash);
 		if (i < 0)
 			return defval;
 		return i + offset;
@@ -1240,7 +1266,7 @@ public:
 	int count(const K &key) const
 	{
 		Hasher::hash_t hash = database.do_hash(key);
-		int i = database.do_lookup(key, hash);
+		int i = database.do_lookup_no_rehash(key, hash);
 		return i < 0 ? 0 : 1;
 	}
 
@@ -1327,7 +1353,8 @@ public:
 		return p;
 	}
 
-	// Merge sets if the given indices belong to different sets
+	// Merge sets if the given indices belong to different sets.
+	// Makes ifind(j) the root of the merged set.
 	void imerge(int i, int j)
 	{
 		i = ifind(i);

yowasp_yosys/share/include/kernel/log.h

@@ -201,6 +201,7 @@ struct LogExpectedItem
 };
 
 extern dict<std::string, LogExpectedItem> log_expect_log, log_expect_warning, log_expect_error;
+extern dict<std::string, LogExpectedItem> log_expect_prefix_log, log_expect_prefix_warning, log_expect_prefix_error;
 void log_check_expected();
 
 const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true);

yowasp_yosys/share/include/kernel/rtlil.h

@@ -1334,7 +1334,7 @@ struct RTLIL::Design
 	dict<RTLIL::IdString, RTLIL::Module*> modules_;
 	std::vector<RTLIL::Binding*> bindings_;
 
-	std::vector<AST::AstNode*> verilog_packages, verilog_globals;
+	std::vector<std::unique_ptr<AST::AstNode>> verilog_packages, verilog_globals;
 	std::unique_ptr<define_map_t> verilog_defines;
 
 	std::vector<RTLIL::Selection> selection_stack;

yowasp_yosys/share/include/kernel/satgen.h

@@ -64,7 +64,7 @@ struct ezSatPtr : public std::unique_ptr<ezSAT> {
 struct SatGen
 {
 	ezSAT *ez;
-	SigMap *sigmap;
+	const SigMap *sigmap;
 	std::string prefix;
 	SigPool initial_state;
 	std::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en;
@@ -75,12 +75,12 @@ struct SatGen
 	bool model_undef;
 	bool def_formal = false;
 
-	SatGen(ezSAT *ez, SigMap *sigmap, std::string prefix = std::string()) :
+	SatGen(ezSAT *ez, const SigMap *sigmap, std::string prefix = std::string()) :
 			ez(ez), sigmap(sigmap), prefix(prefix), ignore_div_by_zero(false), model_undef(false)
 	{
 	}
 
-	void setContext(SigMap *sigmap, std::string prefix = std::string())
+	void setContext(const SigMap *sigmap, std::string prefix = std::string())
 	{
 		this->sigmap = sigmap;
 		this->prefix = prefix;

yowasp_yosys/share/include/kernel/sigtools.h

@@ -237,6 +237,42 @@ using sort_by_name_id_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell
 template<typename T>
 class SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name_id<typename std::remove_pointer<T>::type>> {};
 
+struct SigMapView
+{
+	mfp<SigBit> database;
+
+	// Modify bit to its representative
+	void apply(RTLIL::SigBit &bit) const
+	{
+		bit = database.find(bit);
+	}
+
+	void apply(RTLIL::SigSpec &sig) const
+	{
+		for (auto &bit : sig)
+			apply(bit);
+	}
+
+	RTLIL::SigBit operator()(RTLIL::SigBit bit) const
+	{
+		apply(bit);
+		return bit;
+	}
+
+	RTLIL::SigSpec operator()(RTLIL::SigSpec sig) const
+	{
+		apply(sig);
+		return sig;
+	}
+
+	RTLIL::SigSpec operator()(RTLIL::Wire *wire) const
+	{
+		SigSpec sig(wire);
+		apply(sig);
+		return sig;
+	}
+};
+
 /**
  * SigMap wraps a union-find "database"
  * to map SigBits of a module to canonical representative SigBits.
@@ -244,10 +280,8 @@ class SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name
  * If a SigBit has a const state (impl: bit.wire is nullptr),
  * it's promoted to a representative.
  */
-struct SigMap
+struct SigMap final : public SigMapView
 {
-	mfp<SigBit> database;
-
 	SigMap(RTLIL::Module *module = NULL)
 	{
 		if (module != NULL)
@@ -320,45 +354,115 @@ struct SigMap
 
 	inline void add(Wire *wire) { return add(RTLIL::SigSpec(wire)); }
 
-	// Modify bit to its representative
-	void apply(RTLIL::SigBit &bit) const
+	// All non-const bits
+	RTLIL::SigSpec allbits() const
 	{
-		bit = database.find(bit);
+		RTLIL::SigSpec sig;
+		for (const auto &bit : database)
+			if (bit.wire != nullptr)
+				sig.append(bit);
+		return sig;
 	}
+};
 
-	void apply(RTLIL::SigSpec &sig) const
+/**
+ * SiValgMap wraps a union-find "database" to map SigBits of a module to
+ * canonical representative SigBits plus some optional Val value associated with the bits.
+ * Val has a commutative, associative, idempotent operator|=, a default constructor
+ * which constructs an identity element, and a copy constructor.
+ * SigBits that are connected share a set in the underlying database;
+ * the associated value is the "sum" of all the values associated with the contributing bits.
+ * If any of the SigBits in a set are a constant, the canonical SigBit is a constant.
+ */
+template <class Val>
+struct SigValMap final : public SigMapView
+{
+	dict<SigBit, Val> values;
+
+	void swap(SigValMap<Val> &other)
 	{
-		for (auto &bit : sig)
-			apply(bit);
+		database.swap(other.database);
+		values.swap(other.values);
 	}
 
-	RTLIL::SigBit operator()(RTLIL::SigBit bit) const
+	void clear()
 	{
-		apply(bit);
-		return bit;
+		database.clear();
+		values.clear();
 	}
 
-	RTLIL::SigSpec operator()(RTLIL::SigSpec sig) const
+	// Rebuild SigMap for all connections in module
+	void set(RTLIL::Module *module)
 	{
-		apply(sig);
-		return sig;
+		int bitcount = 0;
+		for (auto &it : module->connections())
+			bitcount += it.first.size();
+
+		database.clear();
+		values.clear();
+		database.reserve(bitcount);
+
+		for (auto &it : module->connections())
+			add(it.first, it.second);
 	}
 
-	RTLIL::SigSpec operator()(RTLIL::Wire *wire) const
+	// Add connections from "from" to "to", bit-by-bit.
+	void add(const RTLIL::SigSpec& from, const RTLIL::SigSpec& to)
 	{
-		SigSpec sig(wire);
-		apply(sig);
-		return sig;
+		log_assert(GetSize(from) == GetSize(to));
+
+		for (int i = 0; i < GetSize(from); i++)
+		{
+			int bfi = database.lookup(from[i]);
+			int bti = database.lookup(to[i]);
+			if (bfi == bti) {
+				continue;
+			}
+
+			const RTLIL::SigBit &bf = database[bfi];
+			const RTLIL::SigBit &bt = database[bti];
+			if (bf.wire == nullptr) {
+				// bf is constant so make it the canonical representative.
+				database.imerge(bti, bfi);
+				merge_value(bt, bf);
+			} else {
+				// Make bt the canonical representative.
+				database.imerge(bfi, bti);
+				merge_value(bf, bt);
+			}
+		}
 	}
 
-	// All non-const bits
-	RTLIL::SigSpec allbits() const
+	void addVal(const RTLIL::SigBit &bit, const Val &val)
 	{
-		RTLIL::SigSpec sig;
-		for (const auto &bit : database)
-			if (bit.wire != nullptr)
-				sig.append(bit);
-		return sig;
+		values[database.find(bit)] |= val;
+	}
+
+	void addVal(const RTLIL::SigSpec &sig, const Val &val)
+	{
+		for (const auto &bit : sig)
+			addVal(bit, val);
+	}
+
+	Val apply_and_get_value(RTLIL::SigBit &bit) const
+	{
+		bit = database.find(bit);
+		auto it = values.find(bit);
+		return it == values.end() ? Val() : it->second;
+	}
+
+private:
+	void merge_value(const RTLIL::SigBit &from, const RTLIL::SigBit &to)
+	{
+		auto it = values.find(from);
+		if (it == values.end()) {
+			return;
+		}
+		// values[to] could resize the underlying `entries` so
+		// finish using `it` first.
+		Val v = it->second;
+		values.erase(it);
+		values[to] |= v;
 	}
 };
 

{yowasp_yosys-0.56.0.0.post964.dist-info → yowasp_yosys-0.56.0.141.post974.dev0.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: yowasp-yosys
-Version: 0.56.0.0.post964
+Version: 0.56.0.141.post974.dev0
 Summary: Yosys Open SYnthesis Suite
 Author-email: Catherine <whitequark@whitequark.org>
 License-Expression: ISC

{yowasp_yosys-0.56.0.0.post964.dist-info → yowasp_yosys-0.56.0.141.post974.dev0.dist-info}/RECORD

@@ -2,7 +2,7 @@ yowasp_yosys/__init__.py,sha256=cxu6bMlZ6zRpCzKp2wdFs7LNt5-btnJD6ghvdkDs6Y0,1189
 yowasp_yosys/sby.py,sha256=BZwSqLk064cKvGITogDi3OqlQtRJJ-8J4_KG5Z7ktoc,19736
 yowasp_yosys/smtbmc.py,sha256=yiI93tHys5c8aXfCdk2dNtw2mwukRXqeT8YGx5Th8eg,74231
 yowasp_yosys/witness.py,sha256=m3iV2Nydm0p4G79VRaaX3lGul-nGnuxeKnx20MCJgi0,17279
-yowasp_yosys/yosys.wasm,sha256=g5VDCRlmu6vbH2ewagXlh-hz6w2saUFj5_RWVPhCySM,37878780
+yowasp_yosys/yosys.wasm,sha256=5vKVdIYg6gv3qPrsjNRngy3DZjLFzlXhKcFFphQ1cB4,38066495
 yowasp_yosys/share/abc9_map.v,sha256=uWDqMpBQTeeadH1BlHVwkCy2StKF892xbgBgMKLK5-w,923
 yowasp_yosys/share/abc9_model.v,sha256=IfMyEGOEUBdZyiVule0wMhrVYVYQpmSIcxygbgtHItI,653
 yowasp_yosys/share/abc9_unmap.v,sha256=w107Y3iJjMU6D_6_aYLf2NziXTnAhpa5_CFAwaYO1iU,638
@@ -115,37 +115,37 @@ yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h,sha
 yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc,sha256=5A6IK46tg8BWgs_vzS183p9HMZfWP7FZfJzCjnB3vW8,2815
 yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h,sha256=P6KBEs-76IK4LwKBhXbju9nwkH3rmmqUm4uSuiaS88M,4286
 yowasp_yosys/share/include/backends/rtlil/rtlil_backend.h,sha256=h-kkdWtAosSZDzvAW511jAHao-dDUm3fyTJhfMXsZDk,2407
-yowasp_yosys/share/include/frontends/ast/ast.h,sha256=rjvkPnIrXBsH3TosMTsuoKpgKyUBUmiWw8rxBgDhuxg,16930
+yowasp_yosys/share/include/frontends/ast/ast.h,sha256=p_nm0-fYc1xyPngvCtvzKFH5rWgydpNq5Q9XPBzokcc,17216
 yowasp_yosys/share/include/frontends/ast/ast_binding.h,sha256=NdII3-d38NWB_87m9AOzqQLjkkYaYToz3xHTsHNelU0,1756
 yowasp_yosys/share/include/frontends/blif/blifparse.h,sha256=GGceOEm-flPK0QdPIVDZ6ZGpkTphT14oTxJhAYIb2RY,1139
 yowasp_yosys/share/include/kernel/binding.h,sha256=BKfMhNf_HflihwCXEqyZuB1zp9xzVi0NRKe-5MvIidM,1947
 yowasp_yosys/share/include/kernel/bitpattern.h,sha256=V_gds0rvxcrRMTFhIm8Zv4PRFowNspJldfURho00lqo,3900
 yowasp_yosys/share/include/kernel/cellaigs.h,sha256=CdYos67IpmAgLvBbJ8EC3hWg6WhBIBy9jmhdoZ36HVE,1391
 yowasp_yosys/share/include/kernel/celledges.h,sha256=fF_sHJOpN_qQ1P0x8KKoJE9ulDMusfjkF0dBpTMs19E,2216
-yowasp_yosys/share/include/kernel/celltypes.h,sha256=W44T0u789-fy_tj7fGRTNI7s1jshewrPwmS3_-Oz6-A,18561
-yowasp_yosys/share/include/kernel/consteval.h,sha256=oEPSKbbgqvNmlLqYFSozZX2cjFQA5IM-d69HmyuZiGo,10864
+yowasp_yosys/share/include/kernel/celltypes.h,sha256=sDqHEa3XqKD-0l-w5bvle5TI-wVABEpF6W1-ThvO7Eg,19027
+yowasp_yosys/share/include/kernel/consteval.h,sha256=nYMALfx9WfaEr4c5VagL0lJta2QT_YdB0MdfXgEO0lU,11046
 yowasp_yosys/share/include/kernel/constids.inc,sha256=lW_aOEkMMVFonK8BAhc6JgmP95X9Q2yBJWg-xfhCc5c,3745
 yowasp_yosys/share/include/kernel/cost.h,sha256=TRW3KGPVLv5MxAmNbSh1mnzwTc-QHvZXSh9Wfc6mw3U,2921
 yowasp_yosys/share/include/kernel/drivertools.h,sha256=jHGOmnyVCjfvUvoBfQvD9O-Tu6pfs4WVbPbQZv1Mhd4,33537
 yowasp_yosys/share/include/kernel/ff.h,sha256=vVJqxmyfJ1z9qnnUA3CAoX5NavU33_J4U1Sd7TgPp5M,7631
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-yowasp_yosys/share/include/kernel/ffmerge.h,sha256=I3mXyytzRyP92T9XhSQTlv7EN2G31nJhspBxlLYiMEY,6305
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 yowasp_yosys/share/include/kernel/fmt.h,sha256=0UT-aDVX7_KnzlaNyK3iMsSzoICa4Q0HhqsFIrwHBMw,2790
 yowasp_yosys/share/include/kernel/gzip.h,sha256=wpAZ9hA13HEpWgZnth46JHvVLSA_qdS-JZB5gh83-QA,1847
-yowasp_yosys/share/include/kernel/hashlib.h,sha256=LgN2dYAg8r0YZnOd1r8DFI0qy7nyWO--SMghZaD7P9k,35719
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 yowasp_yosys/share/include/kernel/json.h,sha256=i2wmIMZ2SCE5zc6IIIVLx4XZ2-HQiZEFJ0ao_cMInK0,2849
-yowasp_yosys/share/include/kernel/log.h,sha256=NZNJPBf-F_sISwfmJ_GQPm1Z9UzUCYQD6jHiWnsVorY,15380
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 yowasp_yosys/share/include/kernel/macc.h,sha256=LHm507daCT57lGCNNwia1LJVk3pkBB5ZteCZihxD5Qw,8926
 yowasp_yosys/share/include/kernel/mem.h,sha256=xKz0HxXap_PTdzpK-NUcbxybF3YisRc2JoCv17TXOc4,15505
 yowasp_yosys/share/include/kernel/modtools.h,sha256=mRnzc5TIsdIbHlFSTk2Yc0y85ttknhK-dAlti3neSI8,14388
 yowasp_yosys/share/include/kernel/qcsat.h,sha256=ibhpJRu0youjDXPllXrDJi851VpwW1kbJ_y94_X6JhU,2804
 yowasp_yosys/share/include/kernel/register.h,sha256=jc3S7uED5yT-60fY_DhfrgRoy3Q_h8kVFaF_lc5JZyY,6789
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-yowasp_yosys/share/include/kernel/satgen.h,sha256=O7h0qkcsaX5g4XsUiLumlj8RAg63fxkFCLgZds5xgL8,10525
+yowasp_yosys/share/include/kernel/rtlil.h,sha256=mnok7FWmr4jh7auCipSXV8HfcPhNyfOKb-Hy-N0XtSk,99528
+yowasp_yosys/share/include/kernel/satgen.h,sha256=IPl4fWKQMyRFalyxwGJEJQt9MXIOKi3BKmqfkDbm7m4,10543
 yowasp_yosys/share/include/kernel/scopeinfo.h,sha256=EAU3vSTIwH1RrbSC7HVoTWh4SLfHMSIoidQPvT1Mo7g,11797
 yowasp_yosys/share/include/kernel/sexpr.h,sha256=CUDKFehVoGmakYBYLpEKUtlM0Dd3oI6TNW_cKz-qe0g,4720
-yowasp_yosys/share/include/kernel/sigtools.h,sha256=Tb1hUOLJD-AV4ojLVcjx0Dc00QSy6nGJyTwNMa4eqw0,8074
+yowasp_yosys/share/include/kernel/sigtools.h,sha256=5s1qkeGjV2pbwrWRNaNgay8qHfKzk7TgK1jQM-C2Dco,10652
 yowasp_yosys/share/include/kernel/timinginfo.h,sha256=JNRktUWp7ow_wn4P5BxlOkv7hNS7qKbws7Gjs6VSUx8,7367
 yowasp_yosys/share/include/kernel/utils.h,sha256=5bJFi7SNf18SL7icrEQEDDYnqT9TrjBMlPZGHbinFK8,7315
 yowasp_yosys/share/include/kernel/yosys.h,sha256=bx9lTnEhsorxUoLhz2hu0__pSvVAyrthvGjoqaOL6oQ,3438
@@ -336,8 +336,8 @@ yowasp_yosys/share/xilinx/xc5v_dsp_map.v,sha256=I4lg0RQ54fBBba_7NNvUgwS4tQ1yLIsU
 yowasp_yosys/share/xilinx/xc6s_dsp_map.v,sha256=gTxHocB-Dn5G4BplWgri_tLhT6DIO2S0X-yu4iBKYyk,562
 yowasp_yosys/share/xilinx/xc7_dsp_map.v,sha256=zrzreQi7mElrAMtrayxtiO_Bw00S6zsjSjSVcjmJPH0,884
 yowasp_yosys/share/xilinx/xcu_dsp_map.v,sha256=gzCgl1emrHGcigVmU0nP0pW7dlhQ01SaWwXzHHcqt-o,882
-yowasp_yosys-0.56.0.0.post964.dist-info/METADATA,sha256=WszNwKNEceAy9MIYakwpaWAXaGqefifrcEkle7IX8tQ,2522
-yowasp_yosys-0.56.0.0.post964.dist-info/WHEEL,sha256=lTU6B6eIfYoiQJTZNc-fyaR6BpL6ehTzU3xGYxn2n8k,91
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-yowasp_yosys-0.56.0.0.post964.dist-info/top_level.txt,sha256=_yiNT8kLYkcD1TEuUCzQ_MkON1c3xuIRV59zXds4zd4,13
-yowasp_yosys-0.56.0.0.post964.dist-info/RECORD,,
+yowasp_yosys-0.56.0.141.post974.dev0.dist-info/METADATA,sha256=vLNx6yFAEnaSbM_DLFuCTdNyU_E2qCCrs6vuGrF7o28,2529
+yowasp_yosys-0.56.0.141.post974.dev0.dist-info/WHEEL,sha256=lTU6B6eIfYoiQJTZNc-fyaR6BpL6ehTzU3xGYxn2n8k,91
+yowasp_yosys-0.56.0.141.post974.dev0.dist-info/entry_points.txt,sha256=p_9sIVi2ZqsqgYYo14PywYkwHYTa76fMEq3LxweXJpc,220
+yowasp_yosys-0.56.0.141.post974.dev0.dist-info/top_level.txt,sha256=_yiNT8kLYkcD1TEuUCzQ_MkON1c3xuIRV59zXds4zd4,13
+yowasp_yosys-0.56.0.141.post974.dev0.dist-info/RECORD,,