yowasp-yosys 0.53.0.0.post912__py3-none-any.whl → 0.55.0.0.post944__py3-none-any.whl

yowasp_yosys/share/gatemate/brams_map.v

@@ -115,15 +115,15 @@ generate
 			.A_CLK(PORT_A_CLK),
 			.A_EN(PORT_A_CLK_EN),
 			.A_WE(PORT_A_WR_EN),
-			.A_BM(PORT_A_WR_BE),
-			.A_DI(PORT_A_WR_DATA),
+			.A_BM({{(20-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}),
+			.A_DI({{(20-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}),
 			.A_ADDR({PORT_A_ADDR[13:5], 1'b0, PORT_A_ADDR[4:0], 1'b0}),
 			.A_DO(PORT_A_RD_DATA),
 			.B_CLK(PORT_B_CLK),
 			.B_EN(PORT_B_CLK_EN),
 			.B_WE(PORT_B_WR_EN),
-			.B_BM(PORT_B_WR_BE),
-			.B_DI(PORT_B_WR_DATA),
+			.B_BM({{(20-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}),
+			.B_DI({{(20-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}),
 			.B_ADDR({PORT_B_ADDR[13:5], 1'b0, PORT_B_ADDR[4:0], 1'b0}),
 			.B_DO(PORT_B_RD_DATA),
 		);
@@ -270,15 +270,15 @@ generate
 			.A_CLK(PORT_A_CLK),
 			.A_EN(PORT_A_CLK_EN),
 			.A_WE(PORT_A_WR_EN),
-			.A_BM(PORT_A_WR_BE),
-			.A_DI(PORT_A_WR_DATA),
+			.A_BM({{(40-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}),
+			.A_DI({{(40-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}),
 			.A_ADDR({PORT_A_ADDR[14:0], 1'b0}),
 			.A_DO(PORT_A_RD_DATA),
 			.B_CLK(PORT_B_CLK),
 			.B_EN(PORT_B_CLK_EN),
 			.B_WE(PORT_B_WR_EN),
-			.B_BM(PORT_B_WR_BE),
-			.B_DI(PORT_B_WR_DATA),
+			.B_BM({{(40-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}),
+			.B_DI({{(40-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}),
 			.B_ADDR({PORT_B_ADDR[14:0], 1'b0}),
 			.B_DO(PORT_B_RD_DATA),
 		);
@@ -429,14 +429,14 @@ generate
 			.A_CLK(PORT_A_CLK),
 			.A_EN(PORT_A_CLK_EN),
 			.A_WE(PORT_A_WR_EN),
-			.A_BM(PORT_A_WR_BE),
-			.A_DI(PORT_A_WR_DATA),
+			.A_BM({{(40-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}),
+			.A_DI({{(40-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}),
 			.A_ADDR({PORT_A_ADDR[14:0], PORT_A_ADDR[15]}),
 			.B_CLK(PORT_B_CLK),
 			.B_EN(PORT_B_CLK_EN),
 			.B_WE(PORT_B_WR_EN),
-			.B_BM(PORT_B_WR_BE),
-			.B_DI(PORT_B_WR_DATA),
+			.B_BM({{(40-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}),
+			.B_DI({{(40-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}),
 			.B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}),
 		);
 		CC_BRAM_40K #(
@@ -584,15 +584,15 @@ generate
 			.A_CLK(PORT_A_CLK),
 			.A_EN(PORT_A_CLK_EN),
 			.A_WE(PORT_A_WR_EN),
-			.A_BM(PORT_A_WR_BE),
-			.A_DI(PORT_A_WR_DATA),
+			.A_BM({{(40-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}),
+			.A_DI({{(40-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}),
 			.A_DO(PORT_A_RD_DATA),
 			.A_ADDR({PORT_A_ADDR[14:0], PORT_A_ADDR[15]}),
 			.B_CLK(PORT_B_CLK),
 			.B_EN(PORT_B_CLK_EN),
 			.B_WE(PORT_B_WR_EN),
-			.B_BM(PORT_B_WR_BE),
-			.B_DI(PORT_B_WR_DATA),
+			.B_BM({{(40-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}),
+			.B_DI({{(40-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}),
 			.B_DO(PORT_B_RD_DATA),
 			.B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}),
 		);
@@ -710,9 +710,9 @@ generate
 			.A_EN(PORT_W_CLK_EN),
 			.A_WE(PORT_W_WR_EN),
 			.A_BM(PORT_W_WR_BE[19:0]),
-			.B_BM(PORT_W_WR_BE[39:20]),
+			.B_BM({{(40-PORT_W_WIDTH){1'bx}}, PORT_W_WR_BE[39:20]}),
 			.A_DI(PORT_W_WR_DATA[19:0]),
-			.B_DI(PORT_W_WR_DATA[39:20]),
+			.B_DI({{(40-PORT_W_WIDTH){1'bx}}, PORT_W_WR_DATA[39:20]}),
 			.A_ADDR({PORT_W_ADDR[13:5], 1'b0, PORT_W_ADDR[4:0], 1'b0}),
 			.B_CLK(PORT_R_CLK),
 			.B_EN(PORT_R_CLK_EN),
@@ -865,9 +865,9 @@ generate
 			.A_EN(PORT_W_CLK_EN),
 			.A_WE(PORT_W_WR_EN),
 			.A_BM(PORT_W_WR_BE[39:0]),
-			.B_BM(PORT_W_WR_BE[79:40]),
+			.B_BM({{(80-PORT_W_WIDTH){1'bx}}, PORT_W_WR_BE[79:40]}),
 			.A_DI(PORT_W_WR_DATA[39:0]),
-			.B_DI(PORT_W_WR_DATA[79:40]),
+			.B_DI({{(80-PORT_W_WIDTH){1'bx}}, PORT_W_WR_DATA[79:40]}),
 			.A_ADDR({PORT_W_ADDR[14:0], 1'b0}),
 			.B_CLK(PORT_R_CLK),
 			.B_EN(PORT_R_CLK_EN),

yowasp_yosys/share/gowin/cells_xtra_gw5a.v

@@ -80,19 +80,8 @@ endmodule
 module MIPI_OBUF_A (...);
 output O, OB;
 input  I, IB, IL, MODESEL;
-endmodule
-
-module IBUF_R (...);
-input  I;
-input RTEN;
-output O;
-endmodule
-
-module IOBUF_R (...);
-input I,OEN;
-input RTEN;
-output O;
-inout IO;
+inout IO, IOB;
+input OEN, OENB;
 endmodule
 
 module ELVDS_IOBUF_R (...);
@@ -113,6 +102,21 @@ input I, IB;
 input ADCEN;
 endmodule
 
+module MIPI_CPHY_IBUF (...);
+output OH0, OL0, OB0, OH1, OL1, OB1, OH2, OL2, OB2;
+inout IO0, IOB0, IO1, IOB1, IO2, IOB2;
+input  I0, IB0, I1, IB1, I2, IB2;
+input OEN, OENB;
+input HSEN;
+endmodule
+
+module MIPI_CPHY_OBUF (...);
+output O0, OB0, O1, OB1, O2, OB2;
+input  I0, IB0, IL0, I1, IB1, IL1, I2, IB2, IL2;
+inout IO0, IOB0, IO1, IOB1, IO2, IOB2;
+input OEN, OENB, MODESEL, VCOME;
+endmodule
+
 module SDPB (...);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH_0 = 32; 
@@ -598,8 +602,8 @@ endmodule
 
 
 module SDP36KE (...);
-parameter ECC_WRITE_EN="FALSE"; 
-parameter ECC_READ_EN="FALSE"; 
+parameter ECC_WRITE_EN="TRUE"; 
+parameter ECC_READ_EN="TRUE"; 
 parameter READ_MODE = 1'b0; 
 parameter BLK_SEL_A = 3'b000;
 parameter BLK_SEL_B = 3'b000;
@@ -764,6 +768,14 @@ output [7:0] ECCP;
 endmodule
 
 
+module SDP136K (...);
+input CLKA, CLKB;
+input WE, RE;
+input [10:0] ADA, ADB;
+input [67:0] DI;
+output [67:0] DO;
+endmodule
+
 module MULTADDALU12X12 (...);
 parameter A0REG_CLK = "BYPASS"; 
 parameter A0REG_CE = "CE0"; 
@@ -980,6 +992,24 @@ input  PSEL;
 input  PADDSUB;
 endmodule
 
+module MULTACC (...);
+output  [23:0] DATAO, CASO;
+input CE, CLK;
+input [5:0] COFFIN0, COFFIN1, COFFIN2;
+input [9:0] DATAIN0, DATAIN1;
+input [9:0] DATAIN2;
+input RSTN;
+input [23:0] CASI;
+parameter COFFIN_WIDTH = 4; 
+parameter DATAIN_WIDTH = 8; 
+parameter IREG = 1'b0; 
+parameter OREG = 1'b0; 
+parameter PREG = 1'b0; 
+parameter ACC_EN = "FALSE";  
+parameter CASI_EN = "FALSE"; 
+parameter CASO_EN = "FALSE"; 
+endmodule
+
 module IDDR_MEM (...);
 input D, ICLK, PCLK;
 input [2:0] WADDR;
@@ -1048,6 +1078,12 @@ output  Q0,  Q1;
 endmodule
 
 
+module OSER14 (...);
+input D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13;
+input PCLK, FCLK, RESET;
+output  Q;
+endmodule
+
 module IODELAY (...);
 parameter C_STATIC_DLY = 0; 
 parameter DYN_DLY_EN = "FALSE";
@@ -1066,13 +1102,39 @@ output [31:0] Q;
 input D;
 input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN;
 input RESET;
-output DF;
-input  SDTAP;
-input  VALUE;
-input  [7:0] DLYSTEP;
-parameter C_STATIC_DLY = 0; 
-parameter DYN_DLY_EN = "FALSE";
-parameter ADAPT_EN = "FALSE";
+output DF0, DF1;
+input  SDTAP0, SDTAP1;
+input  VALUE0,VALUE1;
+input  [7:0] DLYSTEP0,DLYSTEP1;
+parameter C_STATIC_DLY_0 = 0; 
+parameter DYN_DLY_EN_0 = "FALSE";
+parameter ADAPT_EN_0 = "FALSE";
+parameter C_STATIC_DLY_1 = 0; 
+parameter DYN_DLY_EN_1 = "FALSE";
+parameter ADAPT_EN_1 = "FALSE";
+endmodule
+
+module OSIDES64 (...);
+output [63:0] Q;
+input D;
+input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN;
+input RESET;
+output DF0, DF1, DF2, DF3;
+input  SDTAP0, SDTAP1, SDTAP2, SDTAP3;
+input  VALUE0, VALUE1, VALUE2, VALUE3;
+input  [7:0] DLYSTEP0, DLYSTEP1, DLYSTEP2, DLYSTEP3;
+parameter C_STATIC_DLY_0 = 0; 
+parameter DYN_DLY_EN_0 = "FALSE";
+parameter ADAPT_EN_0 = "FALSE";
+parameter C_STATIC_DLY_1 = 0; 
+parameter DYN_DLY_EN_1 = "FALSE";
+parameter ADAPT_EN_1 = "FALSE";
+parameter C_STATIC_DLY_2 = 0; 
+parameter DYN_DLY_EN_2 = "FALSE";
+parameter ADAPT_EN_2 = "FALSE";
+parameter C_STATIC_DLY_3 = 0; 
+parameter DYN_DLY_EN_3 = "FALSE";
+parameter ADAPT_EN_3 = "FALSE";
 endmodule
 
 module DCE (...);
@@ -1132,6 +1194,17 @@ output OSCOUT;
 input OSCEN;
 endmodule
 
+module OSCB (...);
+parameter FREQ_MODE = "25"; 
+parameter FREQ_DIV = 10; 
+parameter DYN_TRIM_EN = "FALSE"; 
+output OSCOUT;
+output OSCREF;
+input OSCEN, FMODE;
+input [7:0] RTRIM;
+input [5:0] RTCTRIM; 
+endmodule
+
 module PLL (...);
 input CLKIN;
 input CLKFB;
@@ -1571,8 +1644,8 @@ input ADWSEL;
 endmodule
 
 module OTP (...);
-parameter MODE = 1'b0; 
-input READ, SHIFT;
+parameter MODE = 2'b01; 
+input CLK, READ, SHIFT;
 output DOUT;
 endmodule
 
@@ -1615,6 +1688,31 @@ input ERR0INJECT,ERR1INJECT;
 input [6:0] ERRINJ0LOC,ERRINJ1LOC;
 endmodule
 
+module CMSERB (...);
+output RUNNING;
+output CRCERR;
+output CRCDONE;
+output ECCCORR;
+output ECCUNCORR; 
+output [12:0] ERRLOC;
+output ECCDEC;
+output DSRRD;
+output DSRWR; 
+output ASRRESET;
+output ASRINC;
+output REFCLK;
+input CLK;
+input [2:0] SEREN;
+input ERR0INJECT,ERR1INJECT;
+input [6:0] ERRINJ0LOC,ERRINJ1LOC;
+endmodule
+
+module SAMBA (...);
+parameter MODE = 2'b00; 
+input SPIAD;
+input LOAD;
+endmodule
+
 module ADCLRC (...);
 endmodule
 
@@ -1624,6 +1722,12 @@ endmodule
 module ADC (...);
 endmodule
 
+module ADC_SAR (...);
+endmodule
+
+module LICD (...);
+endmodule
+
 module MIPI_DPHY (...);
 output RX_CLK_O, TX_CLK_O;
 output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;
@@ -1632,6 +1736,7 @@ input  D0LN_HSRX_DREN, D1LN_HSRX_DREN,  D2LN_HSRX_DREN,  D3LN_HSRX_DREN;
 output  DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N,  DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P;
 inout  CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P;
 input HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK,
+     LPTXEN_LN0, LPTXEN_LN1, LPTXEN_LN2, LPTXEN_LN3, LPTXEN_LNCK;
 input PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X;
 input TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN;
 input [15:0]  CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD;
@@ -1639,6 +1744,8 @@ input HSTXD_VLD;
 input CK0, CK90, CK180, CK270;
 input DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P;
 input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, 
+     HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK,
+     LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3; 
 input RX_DRST_N, TX_DRST_N, WALIGN_DVLD;
 output [7:0] MRDATA;
 input MA_INC, MCLK;
@@ -1714,7 +1821,7 @@ parameter        RX_RD_START_DEPTH              = 5'b00001;
 parameter        RX_SYNC_MODE                   = 1'b0 ; 
 parameter        RX_WORD_ALIGN_BYPASS           = 1'b0 ; 
 parameter        RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; 
-parameter        RX_WORD_LITTLE_ENDIAN          = 1'b0 ; 
+parameter        RX_WORD_LITTLE_ENDIAN          = 1'b1 ; 
 parameter        TX_BYPASS_MODE                 = 1'b0 ; 
 parameter        TX_BYTECLK_SYNC_MODE           = 1'b0 ; 
 parameter        TX_OCLK_USE_CIBCLK             = 1'b0 ; 
@@ -1917,6 +2024,437 @@ parameter        TEST_P_IMP_LN3                 = 1'b0 ;
 parameter        TEST_P_IMP_LNCK                = 1'b0 ;   
 endmodule
 
+module MIPI_DPHYA (...);
+output RX_CLK_O, TX_CLK_O;
+output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;
+output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;
+input  D0LN_HSRX_DREN, D1LN_HSRX_DREN,  D2LN_HSRX_DREN,  D3LN_HSRX_DREN;
+output  DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N,  DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P;
+inout  CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P;
+input HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK,
+     LPTXEN_LN0, LPTXEN_LN1, LPTXEN_LN2, LPTXEN_LN3, LPTXEN_LNCK;
+input PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X;
+input TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN;
+input [15:0]  CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD;
+input HSTXD_VLD;
+input CK0, CK90, CK180, CK270;
+input DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P;
+input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, 
+     HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK,
+     LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3; 
+input RX_DRST_N, TX_DRST_N, WALIGN_DVLD;
+output [7:0] MRDATA;
+input MA_INC, MCLK;
+input [1:0] MOPCODE;
+input [7:0] MWDATA;
+input SPLL_CKN, SPLL_CKP;
+output  ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3, ALPEDO_LANECK;
+output D1LN_DESKEW_DONE,D2LN_DESKEW_DONE,D3LN_DESKEW_DONE,D0LN_DESKEW_DONE;
+output D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR;
+input D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ;
+input HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK;
+input HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK;
+input HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1,  HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK;
+input  ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK;
+parameter        TX_PLLCLK = "NONE"; 
+parameter        RX_ALIGN_BYTE                  = 8'b10111000 ; 
+parameter        RX_HS_8BIT_MODE                = 1'b0 ; 
+parameter        RX_LANE_ALIGN_EN               = 1'b0 ; 
+parameter        TX_HS_8BIT_MODE                = 1'b0 ; 
+parameter        HSREG_EN_LN0                   = 1'b0;  
+parameter        HSREG_EN_LN1                   = 1'b0;  
+parameter        HSREG_EN_LN2                   = 1'b0;  
+parameter        HSREG_EN_LN3                   = 1'b0;  
+parameter        HSREG_EN_LNCK                  = 1'b0;  
+parameter        LANE_DIV_SEL                   = 2'b00;  
+parameter        HSRX_EN                        = 1'b1 ;  
+parameter        HSRX_LANESEL                   = 4'b1111 ;   
+parameter        HSRX_LANESEL_CK                = 1'b1 ;   
+parameter        HSTX_EN_LN0                    = 1'b0 ;   
+parameter        HSTX_EN_LN1                    = 1'b0 ;   
+parameter        HSTX_EN_LN2                    = 1'b0 ;   
+parameter        HSTX_EN_LN3                    = 1'b0 ;   
+parameter        HSTX_EN_LNCK                   = 1'b0 ;   
+parameter        LPTX_EN_LN0                    = 1'b1 ;   
+parameter        LPTX_EN_LN1                    = 1'b1 ;   
+parameter        LPTX_EN_LN2                    = 1'b1 ;   
+parameter        LPTX_EN_LN3                    = 1'b1 ;   
+parameter        LPTX_EN_LNCK                   = 1'b1 ;   
+parameter        TXDP_EN_LN0                    = 1'b0 ;  
+parameter        TXDP_EN_LN1                    = 1'b0 ;   
+parameter        TXDP_EN_LN2                    = 1'b0 ;   
+parameter        TXDP_EN_LN3                    = 1'b0 ;   
+parameter        TXDP_EN_LNCK                   = 1'b0 ;
+parameter        SPLL_DIV_SEL                   = 2'b00;
+parameter        DPHY_CK_SEL                    = 2'b01;
+parameter        CKLN_DELAY_EN                  = 1'b0;  
+parameter        CKLN_DELAY_OVR_VAL             = 7'b0000000; 
+parameter        D0LN_DELAY_EN                  = 1'b0;  
+parameter        D0LN_DELAY_OVR_VAL             = 7'b0000000; 
+parameter        D0LN_DESKEW_BYPASS             = 1'b0;  
+parameter        D1LN_DELAY_EN                  = 1'b0;  
+parameter        D1LN_DELAY_OVR_VAL             = 7'b0000000; 
+parameter        D1LN_DESKEW_BYPASS             = 1'b0;  
+parameter        D2LN_DELAY_EN                  = 1'b0;  
+parameter        D2LN_DELAY_OVR_VAL             = 7'b0000000; 
+parameter        D2LN_DESKEW_BYPASS             = 1'b0;  
+parameter        D3LN_DELAY_EN                  = 1'b0;  
+parameter        D3LN_DELAY_OVR_VAL             = 7'b0000000; 
+parameter        D3LN_DESKEW_BYPASS             = 1'b0;  
+parameter        DESKEW_EN_LOW_DELAY            = 1'b0;  
+parameter        DESKEW_EN_ONE_EDGE             = 1'b0;  
+parameter        DESKEW_FAST_LOOP_TIME          = 4'b0000;  
+parameter        DESKEW_FAST_MODE               = 1'b0;  
+parameter        DESKEW_HALF_OPENING            = 6'b010110; 
+parameter        DESKEW_LSB_MODE                = 2'b00;  
+parameter        DESKEW_M                       = 3'b011;  
+parameter        DESKEW_M_TH                    = 13'b0000110100110; 
+parameter        DESKEW_MAX_SETTING           = 7'b0100001; 
+parameter        DESKEW_ONE_CLK_EDGE_EN       = 1'b0 ; 
+parameter        DESKEW_RST_BYPASS              = 1'b0 ; 
+parameter        RX_BYTE_LITTLE_ENDIAN          = 1'b1 ; 
+parameter        RX_CLK_1X_SYNC_SEL             = 1'b0 ; 
+parameter        RX_INVERT                      = 1'b0 ; 
+parameter        RX_ONE_BYTE0_MATCH             = 1'b0 ; 
+parameter        RX_RD_START_DEPTH              = 5'b00001; 
+parameter        RX_SYNC_MODE                   = 1'b0 ; 
+parameter        RX_WORD_ALIGN_BYPASS           = 1'b0 ; 
+parameter        RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; 
+parameter        RX_WORD_LITTLE_ENDIAN          = 1'b1 ; 
+parameter        TX_BYPASS_MODE                 = 1'b0 ; 
+parameter        TX_BYTECLK_SYNC_MODE           = 1'b0 ; 
+parameter        TX_OCLK_USE_CIBCLK             = 1'b0 ; 
+parameter        TX_RD_START_DEPTH              = 5'b00001; 
+parameter        TX_SYNC_MODE                   = 1'b0 ; 
+parameter        TX_WORD_LITTLE_ENDIAN          = 1'b1 ; 
+parameter        EQ_CS_LANE0                    = 3'b100;  
+parameter        EQ_CS_LANE1                    = 3'b100;  
+parameter        EQ_CS_LANE2                    = 3'b100;  
+parameter        EQ_CS_LANE3                    = 3'b100;  
+parameter        EQ_CS_LANECK                   = 3'b100;  
+parameter        EQ_RS_LANE0                    = 3'b100;  
+parameter        EQ_RS_LANE1                    = 3'b100;  
+parameter        EQ_RS_LANE2                    = 3'b100;  
+parameter        EQ_RS_LANE3                    = 3'b100;  
+parameter        EQ_RS_LANECK                   = 3'b100;  
+parameter        HSCLK_LANE_LN0                 = 1'b0;  
+parameter        HSCLK_LANE_LN1                 = 1'b0;  
+parameter        HSCLK_LANE_LN2                 = 1'b0;  
+parameter        HSCLK_LANE_LN3                 = 1'b0;  
+parameter        HSCLK_LANE_LNCK                = 1'b1;  
+parameter        ALP_ED_EN_LANE0                = 1'b1 ; 
+parameter        ALP_ED_EN_LANE1                = 1'b1 ;  
+parameter        ALP_ED_EN_LANE2                = 1'b1 ;  
+parameter        ALP_ED_EN_LANE3                = 1'b1 ;  
+parameter        ALP_ED_EN_LANECK               = 1'b1 ; 
+parameter        ALP_ED_TST_LANE0               = 1'b0 ;  
+parameter        ALP_ED_TST_LANE1               = 1'b0 ;  
+parameter        ALP_ED_TST_LANE2               = 1'b0 ;  
+parameter        ALP_ED_TST_LANE3               = 1'b0 ;  
+parameter        ALP_ED_TST_LANECK              = 1'b0 ;  
+parameter        ALP_EN_LN0                     = 1'b0 ; 
+parameter        ALP_EN_LN1                     = 1'b0 ;  
+parameter        ALP_EN_LN2                     = 1'b0 ;  
+parameter        ALP_EN_LN3                     = 1'b0 ; 
+parameter        ALP_EN_LNCK                    = 1'b0 ; 
+parameter        ALP_HYS_EN_LANE0               = 1'b1 ;  
+parameter        ALP_HYS_EN_LANE1               = 1'b1 ;  
+parameter        ALP_HYS_EN_LANE2               = 1'b1 ;  
+parameter        ALP_HYS_EN_LANE3               = 1'b1 ;  
+parameter        ALP_HYS_EN_LANECK              = 1'b1 ;  
+parameter        ALP_TH_LANE0                   = 4'b1000 ;   
+parameter        ALP_TH_LANE1                   = 4'b1000 ;   
+parameter        ALP_TH_LANE2                   = 4'b1000 ;   
+parameter        ALP_TH_LANE3                   = 4'b1000 ;   
+parameter        ALP_TH_LANECK                  = 4'b1000 ;   
+parameter        ANA_BYTECLK_PH                 = 2'b00 ;  
+parameter        BIT_REVERSE_LN0                = 1'b0 ;  
+parameter        BIT_REVERSE_LN1                = 1'b0 ;  
+parameter        BIT_REVERSE_LN2                = 1'b0 ;  
+parameter        BIT_REVERSE_LN3                = 1'b0 ;  
+parameter        BIT_REVERSE_LNCK               = 1'b0 ;  
+parameter        BYPASS_TXHCLKEN                = 1'b1 ;  
+parameter        BYPASS_TXHCLKEN_SYNC           = 1'b0 ;  
+parameter        BYTE_CLK_POLAR                 = 1'b0 ;  
+parameter        BYTE_REVERSE_LN0               = 1'b0 ;  
+parameter        BYTE_REVERSE_LN1               = 1'b0 ;  
+parameter        BYTE_REVERSE_LN2               = 1'b0 ;  
+parameter        BYTE_REVERSE_LN3               = 1'b0 ;  
+parameter        BYTE_REVERSE_LNCK              = 1'b0 ;  
+parameter        EN_CLKB1X                      = 1'b1 ;  
+parameter        EQ_PBIAS_LANE0                 = 4'b1000 ;   
+parameter        EQ_PBIAS_LANE1                 = 4'b1000 ;   
+parameter        EQ_PBIAS_LANE2                 = 4'b1000 ;   
+parameter        EQ_PBIAS_LANE3                 = 4'b1000 ;   
+parameter        EQ_PBIAS_LANECK                = 4'b1000 ;   
+parameter        EQ_ZLD_LANE0                   = 4'b1000 ;   
+parameter        EQ_ZLD_LANE1                   = 4'b1000 ;   
+parameter        EQ_ZLD_LANE2                   = 4'b1000 ;   
+parameter        EQ_ZLD_LANE3                   = 4'b1000 ;   
+parameter        EQ_ZLD_LANECK                  = 4'b1000 ;   
+parameter        HIGH_BW_LANE0                  = 1'b1 ;   
+parameter        HIGH_BW_LANE1                  = 1'b1 ;   
+parameter        HIGH_BW_LANE2                  = 1'b1 ;   
+parameter        HIGH_BW_LANE3                  = 1'b1 ;   
+parameter        HIGH_BW_LANECK                 = 1'b1 ;   
+parameter        HSREG_VREF_CTL                 = 3'b100 ;   
+parameter        HSREG_VREF_EN                  = 1'b1 ;  
+parameter        HSRX_DLY_CTL_CK                = 7'b0000000 ;   
+parameter        HSRX_DLY_CTL_LANE0             = 7'b0000000 ;   
+parameter        HSRX_DLY_CTL_LANE1             = 7'b0000000 ;   
+parameter        HSRX_DLY_CTL_LANE2             = 7'b0000000 ;   
+parameter        HSRX_DLY_CTL_LANE3             = 7'b0000000 ;   
+parameter        HSRX_DLY_SEL_LANE0             = 1'b0 ;  
+parameter        HSRX_DLY_SEL_LANE1             = 1'b0 ;   
+parameter        HSRX_DLY_SEL_LANE2             = 1'b0 ;   
+parameter        HSRX_DLY_SEL_LANE3             = 1'b0 ;   
+parameter        HSRX_DLY_SEL_LANECK            = 1'b0 ;   
+parameter        HSRX_DUTY_LANE0                = 4'b1000 ;  
+parameter        HSRX_DUTY_LANE1                = 4'b1000 ;  
+parameter        HSRX_DUTY_LANE2                = 4'b1000 ;  
+parameter        HSRX_DUTY_LANE3                = 4'b1000 ;  
+parameter        HSRX_DUTY_LANECK               = 4'b1000 ;  
+parameter        HSRX_EQ_EN_LANE0               = 1'b1 ;  
+parameter        HSRX_EQ_EN_LANE1               = 1'b1 ;  
+parameter        HSRX_EQ_EN_LANE2               = 1'b1 ;  
+parameter        HSRX_EQ_EN_LANE3               = 1'b1 ;  
+parameter        HSRX_EQ_EN_LANECK              = 1'b1 ;  
+parameter        HSRX_IBIAS                     = 4'b0011 ;   
+parameter        HSRX_IBIAS_TEST_EN             = 1'b0 ;   
+parameter        HSRX_IMARG_EN                  = 1'b0 ;   
+parameter        HSRX_ODT_EN                    = 1'b1 ;   
+parameter        HSRX_ODT_TST                   = 4'b0000 ;   
+parameter        HSRX_ODT_TST_CK                = 1'b0 ;   
+parameter        HSRX_SEL                       = 4'b0000 ;   
+parameter        HSRX_STOP_EN                   = 1'b0 ; 
+parameter        HSRX_TST                       = 4'b0000 ;   
+parameter        HSRX_TST_CK                    = 1'b0 ;   
+parameter        HSRX_WAIT4EDGE                 = 1'b1 ;   
+parameter        HYST_NCTL                      = 2'b01 ;  
+parameter        HYST_PCTL                      = 2'b01 ;  
+parameter        IBIAS_TEST_EN                  = 1'b0 ;   
+parameter        LB_CH_SEL                      = 1'b0 ;   
+parameter        LB_EN_LN0                      = 1'b0 ;   
+parameter        LB_EN_LN1                      = 1'b0 ;   
+parameter        LB_EN_LN2                      = 1'b0 ;   
+parameter        LB_EN_LN3                      = 1'b0 ;   
+parameter        LB_EN_LNCK                     = 1'b0 ;   
+parameter        LB_POLAR_LN0                   = 1'b0 ;   
+parameter        LB_POLAR_LN1                   = 1'b0 ;   
+parameter        LB_POLAR_LN2                   = 1'b0 ;   
+parameter        LB_POLAR_LN3                   = 1'b0 ;   
+parameter        LB_POLAR_LNCK                  = 1'b0 ;   
+parameter        LOW_LPRX_VTH                   = 1'b0 ;   
+parameter        LPBK_DATA2TO1                  = 4'b0000;  
+parameter        LPBK_DATA2TO1_CK               = 1'b0 ;   
+parameter        LPBK_EN                        = 1'b0 ;   
+parameter        LPBK_SEL                       = 4'b0000;  
+parameter        LPBKTST_EN                     = 4'b0000;  
+parameter        LPBKTST_EN_CK                  = 1'b0 ;   
+parameter        LPRX_EN                        = 1'b1 ;   
+parameter        LPRX_TST                       = 4'b0000;  
+parameter        LPRX_TST_CK                    = 1'b0 ;   
+parameter        LPTX_DAT_POLAR_LN0             = 1'b0 ;   
+parameter        LPTX_DAT_POLAR_LN1             = 1'b0 ;   
+parameter        LPTX_DAT_POLAR_LN2             = 1'b0 ;   
+parameter        LPTX_DAT_POLAR_LN3             = 1'b0 ;   
+parameter        LPTX_DAT_POLAR_LNCK            = 1'b0 ;   
+parameter        LPTX_NIMP_LN0                  = 3'b100 ; 
+parameter        LPTX_NIMP_LN1                  = 3'b100 ; 
+parameter        LPTX_NIMP_LN2                  = 3'b100 ; 
+parameter        LPTX_NIMP_LN3                  = 3'b100 ; 
+parameter        LPTX_NIMP_LNCK                 = 3'b100 ; 
+parameter        LPTX_PIMP_LN0                  = 3'b100 ; 
+parameter        LPTX_PIMP_LN1                  = 3'b100 ; 
+parameter        LPTX_PIMP_LN2                  = 3'b100 ; 
+parameter        LPTX_PIMP_LN3                  = 3'b100 ; 
+parameter        LPTX_PIMP_LNCK                 = 3'b100 ; 
+parameter        MIPI_PMA_DIS_N                 = 1'b1 ;   
+parameter        PGA_BIAS_LANE0                 = 4'b1000 ;   
+parameter        PGA_BIAS_LANE1                 = 4'b1000 ;   
+parameter        PGA_BIAS_LANE2                 = 4'b1000 ;   
+parameter        PGA_BIAS_LANE3                 = 4'b1000 ;   
+parameter        PGA_BIAS_LANECK                = 4'b1000 ;   
+parameter        PGA_GAIN_LANE0                 = 4'b1000 ;   
+parameter        PGA_GAIN_LANE1                 = 4'b1000 ;   
+parameter        PGA_GAIN_LANE2                 = 4'b1000 ;   
+parameter        PGA_GAIN_LANE3                 = 4'b1000 ;   
+parameter        PGA_GAIN_LANECK                = 4'b1000 ;   
+parameter        RX_ODT_TRIM_LANE0              = 4'b1000 ;   
+parameter        RX_ODT_TRIM_LANE1              = 4'b1000 ;   
+parameter        RX_ODT_TRIM_LANE2              = 4'b1000 ;   
+parameter        RX_ODT_TRIM_LANE3              = 4'b1000 ;   
+parameter        RX_ODT_TRIM_LANECK             = 4'b1000 ;   
+parameter        SLEWN_CTL_LN0                  = 4'b1111 ;  
+parameter        SLEWN_CTL_LN1                  = 4'b1111 ;   
+parameter        SLEWN_CTL_LN2                  = 4'b1111 ;   
+parameter        SLEWN_CTL_LN3                  = 4'b1111 ;   
+parameter        SLEWN_CTL_LNCK                 = 4'b1111 ;   
+parameter        SLEWP_CTL_LN0                  = 4'b1111 ;   
+parameter        SLEWP_CTL_LN1                  = 4'b1111 ;   
+parameter        SLEWP_CTL_LN2                  = 4'b1111 ;   
+parameter        SLEWP_CTL_LN3                  = 4'b1111 ;   
+parameter        SLEWP_CTL_LNCK                 = 4'b1111 ;   
+parameter        STP_UNIT                       = 2'b01 ;  
+parameter        TERMN_CTL_LN0                  = 4'b1000 ;   
+parameter        TERMN_CTL_LN1                  = 4'b1000 ;   
+parameter        TERMN_CTL_LN2                  = 4'b1000 ;   
+parameter        TERMN_CTL_LN3                  = 4'b1000 ;   
+parameter        TERMN_CTL_LNCK                 = 4'b1000 ;   
+parameter        TERMP_CTL_LN0                  = 4'b1000 ;   
+parameter        TERMP_CTL_LN1                  = 4'b1000 ;   
+parameter        TERMP_CTL_LN2                  = 4'b1000 ;   
+parameter        TERMP_CTL_LN3                  = 4'b1000 ;   
+parameter        TERMP_CTL_LNCK                 = 4'b1000 ;   
+parameter        TEST_EN_LN0                    = 1'b0 ;   
+parameter        TEST_EN_LN1                    = 1'b0 ;   
+parameter        TEST_EN_LN2                    = 1'b0 ;   
+parameter        TEST_EN_LN3                    = 1'b0 ;   
+parameter        TEST_EN_LNCK                   = 1'b0 ;   
+parameter        TEST_N_IMP_LN0                 = 1'b0 ;   
+parameter        TEST_N_IMP_LN1                 = 1'b0 ;   
+parameter        TEST_N_IMP_LN2                 = 1'b0 ;   
+parameter        TEST_N_IMP_LN3                 = 1'b0 ;   
+parameter        TEST_N_IMP_LNCK                = 1'b0 ;   
+parameter        TEST_P_IMP_LN0                 = 1'b0 ;   
+parameter        TEST_P_IMP_LN1                 = 1'b0 ;   
+parameter        TEST_P_IMP_LN2                 = 1'b0 ;   
+parameter        TEST_P_IMP_LN3                 = 1'b0 ;   
+parameter        TEST_P_IMP_LNCK                = 1'b0 ;   
+endmodule
+
+module MIPI_CPHY (...);
+output [41:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD;
+output D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD;
+output [1:0] D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD;
+output D0LN_HSRX_FIFO_RDE_ERR, D0LN_HSRX_FIFO_WRF_ERR, D1LN_HSRX_FIFO_RDE_ERR, D1LN_HSRX_FIFO_WRF_ERR, D2LN_HSRX_FIFO_RDE_ERR, D2LN_HSRX_FIFO_WRF_ERR;
+output [1:0] D0LN_HSRX_WA, D1LN_HSRX_WA, D2LN_HSRX_WA;
+output D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O;   
+output HSTX_FIFO_AE, HSTX_FIFO_AF;
+output HSTX_FIFO_RDE_ERR, HSTX_FIFO_WRF_ERR;
+output RX_CLK_MUXED;
+output TX_CLK_1X_O;
+output DI_LPRX0_A, DI_LPRX0_B, DI_LPRX0_C, DI_LPRX1_A, DI_LPRX1_B, DI_LPRX1_C, DI_LPRX2_A, DI_LPRX2_B, DI_LPRX2_C;
+output [7:0] MDRP_RDATA; 
+inout  D0A, D0B, D0C, D1A, D1B, D1C, D2A, D2B, D2C;
+input  D0LN_HSRX_EN, D0LN_HSTX_EN, D1LN_HSRX_EN, D1LN_HSTX_EN, D2LN_HSRX_EN, D2LN_HSTX_EN;
+input  [41:0] D0LN_HSTX_DATA,D1LN_HSTX_DATA, D2LN_HSTX_DATA;
+input  D0LN_HSTX_DATA_VLD, D1LN_HSTX_DATA_VLD, D2LN_HSTX_DATA_VLD;
+input  [1:0] D0LN_HSTX_MAP_DIS, D1LN_HSTX_MAP_DIS, D2LN_HSTX_MAP_DIS;
+input  D0LN_RX_CLK_1X_I,D1LN_RX_CLK_1X_I, D2LN_RX_CLK_1X_I;
+input  D0LN_RX_DRST_N, D0LN_TX_DRST_N, D1LN_RX_DRST_N, D1LN_TX_DRST_N, D2LN_RX_DRST_N, D2LN_TX_DRST_N;
+input  HSTX_ENLN0, HSTX_ENLN1, HSTX_ENLN2, LPTX_ENLN0, LPTX_ENLN1, LPTX_ENLN2;
+input  [7:0] MDRP_A_D_I;
+input  MDRP_A_INC_I;
+input  MDRP_CLK_I;
+input  [1:0] MDRP_OPCODE_I;
+input  PWRON_RX_LN0, PWRON_RX_LN1, PWRON_RX_LN2, PWRON_TX;
+input  ARST_RXLN0, ARST_RXLN1, ARST_RXLN2; 
+input  ARSTN_TX;
+input  RX_CLK_EN_LN0, RX_CLK_EN_LN1, RX_CLK_EN_LN2; 
+input  TX_CLK_1X_I;
+input  TXDP_ENLN0, TXDP_ENLN1, TXDP_ENLN2; 
+input  TXHCLK_EN; 
+input  DO_LPTX_A_LN0, DO_LPTX_A_LN1, DO_LPTX_A_LN2, DO_LPTX_B_LN0, DO_LPTX_B_LN1, DO_LPTX_B_LN2, DO_LPTX_C_LN0, DO_LPTX_C_LN1, DO_LPTX_C_LN2;
+input  GPLL_CK0,GPLL_CK90, GPLL_CK180, GPLL_CK270;
+input  HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2; 
+input  HSRX_ODT_EN_D0, HSRX_ODT_EN_D1, HSRX_ODT_EN_D2;
+input  LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2; 
+input  SPLL0_CKN, SPLL0_CKP, SPLL1_CKN, SPLL1_CKP;
+parameter TX_PLLCLK = "NONE"; 
+parameter D0LN_HS_TX_EN = 1'b1; 
+parameter D1LN_HS_TX_EN = 1'b1;
+parameter D2LN_HS_TX_EN = 1'b1;
+parameter D0LN_HS_RX_EN = 1'b1; 
+parameter D1LN_HS_RX_EN = 1'b1;
+parameter D2LN_HS_RX_EN = 1'b1;
+parameter TX_HS_21BIT_MODE = 1'b0; 
+parameter RX_OUTCLK_SEL = 2'b00; 
+parameter TX_W_LENDIAN = 1'b1; 
+parameter CLK_SEL = 2'b00; 
+parameter LNDIV_RATIO = 4'b0000; 
+parameter LNDIV_EN = 1'b0; 
+parameter D0LN_TX_REASGN_A = 2'b00; 
+parameter D0LN_TX_REASGN_B = 2'b01; 
+parameter D0LN_TX_REASGN_C = 2'b10; 
+parameter D0LN_RX_HS_21BIT_MODE = 1'b0; 
+parameter D0LN_RX_WA_SYNC_PAT0_EN = 1'b1;  
+parameter D0LN_RX_WA_SYNC_PAT0_H = 7'b1001001;  
+parameter D0LN_RX_WA_SYNC_PAT0_L = 8'b00100100;  
+parameter D0LN_RX_WA_SYNC_PAT1_EN = 1'b1;  
+parameter D0LN_RX_WA_SYNC_PAT1_H = 7'b0101001;  
+parameter D0LN_RX_WA_SYNC_PAT1_L = 8'b00100100;  
+parameter D0LN_RX_WA_SYNC_PAT2_EN = 1'b1;  
+parameter D0LN_RX_WA_SYNC_PAT2_H = 7'b0011001;  
+parameter D0LN_RX_WA_SYNC_PAT2_L = 8'b00100100;  
+parameter D0LN_RX_WA_SYNC_PAT3_EN = 1'b0;  
+parameter D0LN_RX_WA_SYNC_PAT3_H = 7'b0001001;  
+parameter D0LN_RX_WA_SYNC_PAT3_L = 8'b00100100;  
+parameter D0LN_RX_W_LENDIAN = 1'b1;  
+parameter D0LN_RX_REASGN_A = 2'b00; 
+parameter D0LN_RX_REASGN_B = 2'b01; 
+parameter D0LN_RX_REASGN_C = 2'b10; 
+parameter HSRX_LNSEL = 3'b111; 
+parameter EQ_RS_LN0 = 3'b001; 
+parameter EQ_CS_LN0 = 3'b101; 
+parameter PGA_GAIN_LN0 = 4'b0110; 
+parameter PGA_BIAS_LN0 = 4'b1000; 
+parameter EQ_PBIAS_LN0 = 4'b0100; 
+parameter EQ_ZLD_LN0 = 4'b1000; 
+parameter D1LN_TX_REASGN_A = 2'b00; 
+parameter D1LN_TX_REASGN_B = 2'b01; 
+parameter D1LN_TX_REASGN_C = 2'b10; 
+parameter D1LN_RX_HS_21BIT_MODE = 1'b0; 
+parameter D1LN_RX_WA_SYNC_PAT0_EN = 1'b1;  
+parameter D1LN_RX_WA_SYNC_PAT0_H = 7'b1001001;  
+parameter D1LN_RX_WA_SYNC_PAT0_L = 8'b00100100;  
+parameter D1LN_RX_WA_SYNC_PAT1_EN = 1'b1;  
+parameter D1LN_RX_WA_SYNC_PAT1_H = 7'b0101001;  
+parameter D1LN_RX_WA_SYNC_PAT1_L = 8'b00100100;  
+parameter D1LN_RX_WA_SYNC_PAT2_EN = 1'b1;  
+parameter D1LN_RX_WA_SYNC_PAT2_H = 7'b0011001;  
+parameter D1LN_RX_WA_SYNC_PAT2_L = 8'b00100100;  
+parameter D1LN_RX_WA_SYNC_PAT3_EN = 1'b0;  
+parameter D1LN_RX_WA_SYNC_PAT3_H = 7'b0001001;  
+parameter D1LN_RX_WA_SYNC_PAT3_L = 8'b00100100;  
+parameter D1LN_RX_W_LENDIAN = 1'b1;  
+parameter D1LN_RX_REASGN_A = 2'b00; 
+parameter D1LN_RX_REASGN_B = 2'b01; 
+parameter D1LN_RX_REASGN_C = 2'b10; 
+parameter EQ_RS_LN1 = 3'b001; 
+parameter EQ_CS_LN1 = 3'b101; 
+parameter PGA_GAIN_LN1 = 4'b0110; 
+parameter PGA_BIAS_LN1 = 4'b1000; 
+parameter EQ_PBIAS_LN1 = 4'b0100; 
+parameter EQ_ZLD_LN1 = 4'b1000; 
+parameter D2LN_TX_REASGN_A = 2'b00; 
+parameter D2LN_TX_REASGN_B = 2'b01; 
+parameter D2LN_TX_REASGN_C = 2'b10; 
+parameter D2LN_RX_HS_21BIT_MODE = 1'b0; 
+parameter D2LN_RX_WA_SYNC_PAT0_EN = 1'b1;  
+parameter D2LN_RX_WA_SYNC_PAT0_H = 7'b1001001;  
+parameter D2LN_RX_WA_SYNC_PAT0_L = 8'b00100100;  
+parameter D2LN_RX_WA_SYNC_PAT1_EN = 1'b1;  
+parameter D2LN_RX_WA_SYNC_PAT1_H = 7'b0101001;  
+parameter D2LN_RX_WA_SYNC_PAT1_L = 8'b00100100;  
+parameter D2LN_RX_WA_SYNC_PAT2_EN = 1'b1;  
+parameter D2LN_RX_WA_SYNC_PAT2_H = 7'b0011001;  
+parameter D2LN_RX_WA_SYNC_PAT2_L = 8'b00100100;  
+parameter D2LN_RX_WA_SYNC_PAT3_EN = 1'b0;  
+parameter D2LN_RX_WA_SYNC_PAT3_H = 7'b0001001;  
+parameter D2LN_RX_WA_SYNC_PAT3_L = 8'b00100100;  
+parameter D2LN_RX_W_LENDIAN = 1'b1;  
+parameter D2LN_RX_REASGN_A = 2'b00; 
+parameter D2LN_RX_REASGN_B = 2'b01; 
+parameter D2LN_RX_REASGN_C = 2'b10; 
+parameter EQ_RS_LN2 = 3'b001; 
+parameter EQ_CS_LN2 = 3'b101; 
+parameter PGA_GAIN_LN2 = 4'b0110; 
+parameter PGA_BIAS_LN2 = 4'b1000; 
+parameter EQ_PBIAS_LN2 = 4'b0100; 
+parameter EQ_ZLD_LN2 = 4'b1000; 
+endmodule
+
 module GTR12_QUAD (...);
 endmodule
 
@@ -1926,6 +2464,18 @@ endmodule
 module GTR12_PMAC (...);
 endmodule
 
+module GTR12_QUADA (...);
+endmodule
+
+module GTR12_UPARA (...);
+endmodule
+
+module GTR12_PMACA (...);
+endmodule
+
+module GTR12_QUADB (...);
+endmodule
+
 module DQS (...);
 input DQSIN,PCLK,FCLK,RESET;
 input [3:0] READ;
@@ -1941,4 +2491,3 @@ parameter RD_PNTR = 3'b000;
 parameter DQS_MODE = "X1"; 
 parameter HWL = "false";   
 endmodule
-

yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h

@@ -200,6 +200,10 @@ enum cxxrtl_flag {
 	// node, such as inputs and dangling wires.
 	CXXRTL_UNDRIVEN = 1 << 4,
 
+	// Generated correspond to netlist nodes that correspond to state with an internal name, that
+	// need to be saved, but wouldn't otherwise have a debug item generated.
+	CXXRTL_GENERATED = 1 << 5,
+
 	// More object flags may be added in the future, but the existing ones will never change.
 };
 

yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h

@@ -1294,6 +1294,7 @@ struct debug_item : ::cxxrtl_object {
 		DRIVEN_SYNC = CXXRTL_DRIVEN_SYNC,
 		DRIVEN_COMB = CXXRTL_DRIVEN_COMB,
 		UNDRIVEN    = CXXRTL_UNDRIVEN,
+		GENERATED = CXXRTL_GENERATED,
 	};
 
 	debug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {}

yowasp_yosys/share/include/kernel/constids.inc

@@ -153,6 +153,7 @@ X(parameter)
 X(PORTID)
 X(PRIORITY)
 X(PRIORITY_MASK)
+X(promoted_if)
 X(Q)
 X(R)
 X(ram_block)
@@ -184,6 +185,7 @@ X(romstyle)
 X(S)
 X(SET)
 X(SET_POLARITY)
+X(single_bit_vector)
 X(SIZE)
 X(SRC)
 X(src)

yowasp_yosys/share/include/kernel/hashlib.h

@@ -14,6 +14,7 @@
 
 #include <stdexcept>
 #include <algorithm>
+#include <optional>
 #include <string>
 #include <variant>
 #include <vector>

yowasp_yosys/share/include/kernel/io.h

@@ -64,6 +64,23 @@ inline std::string stringf(const char *fmt, ...)
 	return string;
 }
 
+int readsome(std::istream &f, char *s, int n);
+std::string next_token(std::string &text, const char *sep = " \t\r\n", bool long_strings = false);
+std::vector<std::string> split_tokens(const std::string &text, const char *sep = " \t\r\n");
+bool patmatch(const char *pattern, const char *string);
+#if !defined(YOSYS_DISABLE_SPAWN)
+int run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());
+#endif
+std::string get_base_tmpdir();
+std::string make_temp_file(std::string template_str = get_base_tmpdir() + "/yosys_XXXXXX");
+std::string make_temp_dir(std::string template_str = get_base_tmpdir() + "/yosys_XXXXXX");
+bool check_file_exists(const std::string& filename, bool is_exec = false);
+bool check_directory_exists(const std::string& dirname, bool is_exec = false);
+bool is_absolute_path(std::string filename);
+void remove_directory(std::string dirname);
+bool create_directory(const std::string& dirname);
+std::string escape_filename_spaces(const std::string& filename);
+
 YOSYS_NAMESPACE_END
 
 #endif // YOSYS_IO_H

yowasp_yosys/share/include/kernel/register.h

@@ -29,6 +29,7 @@ struct Pass
 {
 	std::string pass_name, short_help;
 	Pass(std::string name, std::string short_help = "** document me **");
+	// Prefer overriding 'Pass::on_shutdown()' if possible
 	virtual ~Pass();
 
 	virtual void help();

yowasp_yosys/share/include/kernel/rtlil.h

@@ -753,7 +753,26 @@ public:
 
 	std::vector<RTLIL::State>& bits();
 	bool as_bool() const;
+
+	// Convert the constant value to a C++ int.
+	// NOTE: If the constant is too wide to fit in int (32 bits) this will
+	// truncate any higher bits, potentially over/underflowing. Consider using
+	// try_as_int, as_int_saturating, or guarding behind convertible_to_int
+	// instead.
 	int as_int(bool is_signed = false) const;
+
+	// Returns true iff the constant can be converted to an int without
+	// over/underflow.
+	bool convertible_to_int(bool is_signed = false) const;
+
+	// Returns the constant's value as an int if it can be represented without
+	// over/underflow, or std::nullopt otherwise.
+	std::optional<int> try_as_int(bool is_signed = false) const;
+
+	// Returns the constant's value as an int if it can be represented without
+	// over/underflow, otherwise the max/min value for int depending on the sign.
+	int as_int_saturating(bool is_signed = false) const;
+
 	std::string as_string(const char* any = "-") const;
 	static Const from_string(const std::string &str);
 	std::vector<RTLIL::State> to_bits() const;
@@ -1130,7 +1149,27 @@ public:
 	bool is_onehot(int *pos = nullptr) const;
 
 	bool as_bool() const;
+
+	// Convert the SigSpec to a C++ int, assuming all bits are constant.
+	// NOTE: If the value is too wide to fit in int (32 bits) this will
+	// truncate any higher bits, potentially over/underflowing. Consider using
+	// try_as_int, as_int_saturating, or guarding behind convertible_to_int
+	// instead.
 	int as_int(bool is_signed = false) const;
+
+	// Returns true iff the SigSpec is constant and can be converted to an int
+	// without over/underflow.
+	bool convertible_to_int(bool is_signed = false) const;
+
+	// Returns the SigSpec's value as an int if it is a constant and can be
+	// represented without over/underflow, or std::nullopt otherwise.
+	std::optional<int> try_as_int(bool is_signed = false) const;
+
+	// Returns an all constant SigSpec's value as an int if it can be represented
+	// without over/underflow, otherwise the max/min value for int depending on
+	// the sign.
+	int as_int_saturating(bool is_signed = false) const;
+
 	std::string as_string() const;
 	RTLIL::Const as_const() const;
 	RTLIL::Wire *as_wire() const;
@@ -1182,7 +1221,7 @@ struct RTLIL::Selection
 		bool boxes = false,
 		// the design to select from
 		RTLIL::Design *design = nullptr
-	) : 
+	) :
 		selects_boxes(boxes), complete_selection(full && boxes), full_selection(full && !boxes), current_design(design) { }
 
 	// checks if the given module exists in the current design and is a

yowasp_yosys/share/include/kernel/yosys.h

@@ -81,6 +81,7 @@ extern std::set<std::string> yosys_input_files, yosys_output_files;
 
 // from kernel/version_*.o (cc source generated from Makefile)
 extern const char *yosys_version_str;
+const char* yosys_maybe_version();
 
 // from passes/cmds/design.cc
 extern std::map<std::string, RTLIL::Design*> saved_designs;

yowasp_yosys/share/include/kernel/yosys_common.h

@@ -252,28 +252,12 @@ inline void memhasher() { if (memhasher_active) memhasher_do(); }
 void yosys_banner();
 int ceil_log2(int x) YS_ATTRIBUTE(const);
 
-int readsome(std::istream &f, char *s, int n);
-std::string next_token(std::string &text, const char *sep = " \t\r\n", bool long_strings = false);
-std::vector<std::string> split_tokens(const std::string &text, const char *sep = " \t\r\n");
-bool patmatch(const char *pattern, const char *string);
-#if !defined(YOSYS_DISABLE_SPAWN)
-int run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());
-#endif
-std::string get_base_tmpdir();
-std::string make_temp_file(std::string template_str = get_base_tmpdir() + "/yosys_XXXXXX");
-std::string make_temp_dir(std::string template_str = get_base_tmpdir() + "/yosys_XXXXXX");
-bool check_file_exists(std::string filename, bool is_exec = false);
-bool check_directory_exists(const std::string& dirname);
-bool is_absolute_path(std::string filename);
-void remove_directory(std::string dirname);
-bool create_directory(const std::string& dirname);
-std::string escape_filename_spaces(const std::string& filename);
-
 template<typename T> int GetSize(const T &obj) { return obj.size(); }
 inline int GetSize(RTLIL::Wire *wire);
 
 extern int autoidx;
 extern int yosys_xtrace;
+extern bool yosys_write_versions;
 
 RTLIL::IdString new_id(std::string file, int line, std::string func);
 RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix);

yowasp_yosys/share/python3/sby_status.py

@@ -68,8 +68,8 @@ class SbyStatusDb:
 
         self.db = sqlite3.connect(path, isolation_level=None, timeout=timeout)
         self.db.row_factory = sqlite3.Row
-        self.db.execute("PRAGMA journal_mode=WAL")
-        self.db.execute("PRAGMA synchronous=0")
+        self.db.execute("PRAGMA journal_mode=WAL").fetchone()
+        self.db.execute("PRAGMA synchronous=0").fetchone()
 
         if setup:
             self._setup()

yowasp_yosys/share/xilinx/urams.txt

@@ -35,3 +35,25 @@ ram huge $__XILINX_URAM_ {
 		wrbe_separate;
 	}
 }
+
+ram huge $__XILINX_URAM_SP_ {
+	abits 11;
+	width 144;
+	cost 1024;
+	option "BYTEWIDTH" 8 byte 8;
+	option "BYTEWIDTH" 9 byte 9;
+	init zero;
+	port srsw "A" {
+		clock anyedge "C";
+		clken;
+		rdwr no_change;
+		rdinit zero;
+		portoption "RST_MODE" "SYNC" {
+			rdsrst zero ungated;
+		}
+		portoption "RST_MODE" "ASYNC" {
+			rdarst zero;
+		}
+		wrbe_separate;
+	}
+}

yowasp_yosys/share/xilinx/urams_map.v

@@ -150,3 +150,141 @@ module $__XILINX_URAM_ (...);
 		.SLEEP(1'b0)
 	);
 endmodule
+
+module $__XILINX_URAM_SP_ (...);
+	parameter OPTION_BYTEWIDTH = 8;
+	localparam WR_BE_WIDTH = 144 / OPTION_BYTEWIDTH;
+
+	parameter CLK_C_POL = 1;
+	parameter PORT_A_CLK_POL = 1;
+	parameter PORT_A_OPTION_RST_MODE = "SYNC";
+
+	input CLK_C;
+
+	input PORT_A_CLK;
+	input PORT_A_CLK_EN;
+	input PORT_A_RD_SRST;
+	input PORT_A_RD_ARST;
+	input PORT_A_WR_EN;
+	input [WR_BE_WIDTH-1:0] PORT_A_WR_BE;
+	input [10:0] PORT_A_ADDR;
+	input [143:0] PORT_A_WR_DATA;
+	output [143:0] PORT_A_RD_DATA;
+
+	wire [71:0] DIN_A, DIN_B, DOUT_A, DOUT_B;
+
+	generate
+		if (OPTION_BYTEWIDTH == 8) begin
+			assign DIN_A = PORT_A_WR_DATA[71:0];
+			assign DIN_B = PORT_A_WR_DATA[143:72];
+			assign PORT_A_RD_DATA = {DOUT_B, DOUT_A};
+		end else begin
+			assign DIN_A = {
+				PORT_A_WR_DATA[71],
+				PORT_A_WR_DATA[62],
+				PORT_A_WR_DATA[53],
+				PORT_A_WR_DATA[44],
+				PORT_A_WR_DATA[35],
+				PORT_A_WR_DATA[26],
+				PORT_A_WR_DATA[17],
+				PORT_A_WR_DATA[8],
+				PORT_A_WR_DATA[70:63],
+				PORT_A_WR_DATA[61:54],
+				PORT_A_WR_DATA[52:45],
+				PORT_A_WR_DATA[43:36],
+				PORT_A_WR_DATA[34:27],
+				PORT_A_WR_DATA[25:18],
+				PORT_A_WR_DATA[16:9],
+				PORT_A_WR_DATA[7:0]
+			};
+			assign DIN_B = {
+				PORT_A_WR_DATA[72+71],
+				PORT_A_WR_DATA[72+62],
+				PORT_A_WR_DATA[72+53],
+				PORT_A_WR_DATA[72+44],
+				PORT_A_WR_DATA[72+35],
+				PORT_A_WR_DATA[72+26],
+				PORT_A_WR_DATA[72+17],
+				PORT_A_WR_DATA[72+8],
+				PORT_A_WR_DATA[72+70:72+63],
+				PORT_A_WR_DATA[72+61:72+54],
+				PORT_A_WR_DATA[72+52:72+45],
+				PORT_A_WR_DATA[72+43:72+36],
+				PORT_A_WR_DATA[72+34:72+27],
+				PORT_A_WR_DATA[72+25:72+18],
+				PORT_A_WR_DATA[72+16:72+ 9],
+				PORT_A_WR_DATA[72+ 7:72+ 0]
+			};
+			assign PORT_A_RD_DATA = {
+				DOUT_B[71],
+				DOUT_B[63:56],
+				DOUT_B[70],
+				DOUT_B[55:48],
+				DOUT_B[69],
+				DOUT_B[47:40],
+				DOUT_B[68],
+				DOUT_B[39:32],
+				DOUT_B[67],
+				DOUT_B[31:24],
+				DOUT_B[66],
+				DOUT_B[23:16],
+				DOUT_B[65],
+				DOUT_B[15:8],
+				DOUT_B[64],
+				DOUT_B[7:0],
+				DOUT_A[71],
+				DOUT_A[63:56],
+				DOUT_A[70],
+				DOUT_A[55:48],
+				DOUT_A[69],
+				DOUT_A[47:40],
+				DOUT_A[68],
+				DOUT_A[39:32],
+				DOUT_A[67],
+				DOUT_A[31:24],
+				DOUT_A[66],
+				DOUT_A[23:16],
+				DOUT_A[65],
+				DOUT_A[15:8],
+				DOUT_A[64],
+				DOUT_A[7:0]
+			};
+		end
+	endgenerate
+
+	URAM288 #(
+		.BWE_MODE_A(OPTION_BYTEWIDTH == 8 ? "PARITY_INDEPENDENT" : "PARITY_INTERLEAVED"),
+		.BWE_MODE_B(OPTION_BYTEWIDTH == 8 ? "PARITY_INDEPENDENT" : "PARITY_INTERLEAVED"),
+		.EN_AUTO_SLEEP_MODE("FALSE"),
+		.IREG_PRE_A("FALSE"),
+		.IREG_PRE_B("FALSE"),
+		.IS_CLK_INVERTED(!CLK_C_POL),
+		.OREG_A("FALSE"),
+		.OREG_B("FALSE"),
+		.RST_MODE_A(PORT_A_OPTION_RST_MODE),
+		.RST_MODE_B(PORT_A_OPTION_RST_MODE),
+	) _TECHMAP_REPLACE_ (
+		.ADDR_A({11'b0, PORT_A_ADDR, 1'b0}),
+		.BWE_A(PORT_A_WR_BE[WR_BE_WIDTH/2-1:0]),
+		.EN_A(PORT_A_CLK_EN),
+		.RDB_WR_A(PORT_A_WR_EN),
+		.INJECT_DBITERR_A(1'b0),
+		.INJECT_SBITERR_A(1'b0),
+		.RST_A(PORT_A_OPTION_RST_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
+		.DIN_A(DIN_A),
+		.DOUT_A(DOUT_A),
+
+		.ADDR_B({11'b0, PORT_A_ADDR, 1'b1}),
+		.BWE_B(PORT_A_WR_BE[WR_BE_WIDTH-1:WR_BE_WIDTH/2]),
+		.EN_B(PORT_A_CLK_EN),
+		.RDB_WR_B(PORT_A_WR_EN),
+		.INJECT_DBITERR_B(1'b0),
+		.INJECT_SBITERR_B(1'b0),
+		.RST_B(PORT_A_OPTION_RST_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
+		.DIN_B(DIN_B),
+		.DOUT_B(DOUT_B),
+
+		.CLK(CLK_C),
+		.SLEEP(1'b0)
+	);
+endmodule

{yowasp_yosys-0.53.0.0.post912.dist-info → yowasp_yosys-0.55.0.0.post944.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: yowasp-yosys
-Version: 0.53.0.0.post912
+Version: 0.55.0.0.post944
 Summary: Yosys Open SYnthesis Suite
 Author-email: Catherine <whitequark@whitequark.org>
 License-Expression: ISC

{yowasp_yosys-0.53.0.0.post912.dist-info → yowasp_yosys-0.55.0.0.post944.dist-info}/RECORD

@@ -2,7 +2,7 @@ yowasp_yosys/__init__.py,sha256=x--xPTzLWZNoX6H0B2E3a1HMZMk3di10gVnWVLJ92xc,1325
 yowasp_yosys/sby.py,sha256=at4UB7rmju4xhmFP6b31T7duU2Hx5aSOgGUiExKz7Xc,18496
 yowasp_yosys/smtbmc.py,sha256=yiI93tHys5c8aXfCdk2dNtw2mwukRXqeT8YGx5Th8eg,74231
 yowasp_yosys/witness.py,sha256=m3iV2Nydm0p4G79VRaaX3lGul-nGnuxeKnx20MCJgi0,17279
-yowasp_yosys/yosys.wasm,sha256=kJpC9cgE7pspygVw_FWEGdtV301egX_bAtvYCMvaL60,30800114
+yowasp_yosys/yosys.wasm,sha256=ZRlaPsw7y5wf-yOoaeC5oonVdRP2q7ZjKzJUKIEYdUk,30830300
 yowasp_yosys/share/abc9_map.v,sha256=uWDqMpBQTeeadH1BlHVwkCy2StKF892xbgBgMKLK5-w,923
 yowasp_yosys/share/abc9_model.v,sha256=IfMyEGOEUBdZyiVule0wMhrVYVYQpmSIcxygbgtHItI,653
 yowasp_yosys/share/abc9_unmap.v,sha256=w107Y3iJjMU6D_6_aYLf2NziXTnAhpa5_CFAwaYO1iU,638
@@ -67,7 +67,7 @@ yowasp_yosys/share/gatemate/arith_map.v,sha256=U8Lz8wj0WpUh9YP89MVQfkgYcw4xYE0XW
 yowasp_yosys/share/gatemate/brams.txt,sha256=mtysGrMGltlSw98eOHSSrN38xzQmkxVbfgTivQrZ5qk,1210
 yowasp_yosys/share/gatemate/brams_init_20.vh,sha256=PKYSRZOL_i6Fmjy1dB-lF0eSlV8BFLjGvDqrw6zhLpw,4480
 yowasp_yosys/share/gatemate/brams_init_40.vh,sha256=yK50gQK1Kc59RxbbV9xjeWohhInkyZ3g6N5WmtpqMug,17970
-yowasp_yosys/share/gatemate/brams_map.v,sha256=dUtJmsUqxezzJfuFeJq8xxCC_MeVlECYagxsXhGEJHA,29326
+yowasp_yosys/share/gatemate/brams_map.v,sha256=dZlYuJQUzZ6bBNx41Lwyg3pvhDqMeAO7fqR0LACP1XM,29978
 yowasp_yosys/share/gatemate/cells_bb.v,sha256=cc9cOL12VXqvKf6JV4r3XD2dSx4O_2Q8L0yWMlTog3A,11964
 yowasp_yosys/share/gatemate/cells_sim.v,sha256=WRAD7MrD6K_aNQE8AM4yCldphCksCImFKnguMLj9bd4,65936
 yowasp_yosys/share/gatemate/inv_map.v,sha256=UpmZftbrZGv7K8od1rjId099dTuqQyaP7z4z-V3hQgI,180
@@ -84,7 +84,7 @@ yowasp_yosys/share/gowin/cells_map.v,sha256=Zmq2VlZOFBHhUN65j3DOWdgKpKBMoSTiqgYB
 yowasp_yosys/share/gowin/cells_sim.v,sha256=bsBmaeVUgBxZdvrI1E0hw9hJSdbrf6lO5UIk-UwXiSc,47486
 yowasp_yosys/share/gowin/cells_xtra_gw1n.v,sha256=vu8hc6n0qtQks9tIbdmPLy9GclaElg44VxJLcv4kHcg,63302
 yowasp_yosys/share/gowin/cells_xtra_gw2a.v,sha256=MLcDrVMnxzL7oyybb6i9-0L-35i2vtmG7kfRG6nQiRg,63048
-yowasp_yosys/share/gowin/cells_xtra_gw5a.v,sha256=OZ8f-kKe2mSXC8f0Fy57h2MG5O4UH-7UMtLEF9lgBGs,96450
+yowasp_yosys/share/gowin/cells_xtra_gw5a.v,sha256=qPT8WMcF0ypIKpet84Om0x_qgcjK7ty9uclG19Ah2d0,123052
 yowasp_yosys/share/gowin/lutrams.txt,sha256=ib7Q_pLoKeD3PDdKtqZ3VjVSrHpYpScFHsZPE9lCpiI,160
 yowasp_yosys/share/gowin/lutrams_map.v,sha256=UfbLt-u17rTnpWW-_LPadPN702eL6bRADjaUKJgW9eY,1122
 yowasp_yosys/share/greenpak4/cells_blackbox.v,sha256=cjWerikdsGdIxw12UrNZMCRLXDcciOgdFvYyiYi2BQA,365
@@ -106,12 +106,12 @@ yowasp_yosys/share/ice40/ff_map.v,sha256=0ikq-i1_UVT6xuFLMj2Zfilwu6wz8oibMdtPegZ
 yowasp_yosys/share/ice40/latches_map.v,sha256=V5NwBaIML68eOlhDaUJUs8W-ggRePjPsDtUn3mnSpao,258
 yowasp_yosys/share/ice40/spram.txt,sha256=dCRV0flfJunvnvKV0Q5Kq5NBrhh_PkZGXvUt675aiIk,153
 yowasp_yosys/share/ice40/spram_map.v,sha256=O8fRkVuH1dgAXEAtYJgh8wTHnZEK75fPAMBI-PgYVqs,475
-yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h,sha256=MN2K_SZTGGeq0yQjcR2rd6XQvEL8ewc7GDymzZUg7zY,72493
+yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h,sha256=8ngxTSDlfd24wEl05RP_K_9BflHxxATY-oZMfNaQO5E,72525
 yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h,sha256=3bFAy3nYtaH4MsLI9Kvf88K6BYOkML8plDMxmPtPdss,30008
 yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h,sha256=6zIxuXG7bXy5UWe7WuA_KQHiwV7VWvcsNecwOPAL_bU,6174
 yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h,sha256=L4VOOx7c9rGkxTFi8VjhhNGEbuzxf_j6P5D0_0n0WjA,8637
 yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc,sha256=4WH8B0B7Y7GY43BXZX0-6PGFPYcbOcavJseI0wM_VJQ,4559
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 yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc,sha256=5A6IK46tg8BWgs_vzS183p9HMZfWP7FZfJzCjnB3vW8,2815
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 yowasp_yosys/share/include/kernel/drivertools.h,sha256=jHGOmnyVCjfvUvoBfQvD9O-Tu6pfs4WVbPbQZv1Mhd4,33537
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 yowasp_yosys/share/include/kernel/yw.h,sha256=Gr5zqBNUSKXOKhdw7tl9-KcCiZg3xFcK9Msj7LMawdI,5470
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 yowasp_yosys/share/python3/sby_mode_live.py,sha256=jpINzeD4tEZDhsVORbfg3tIXZbA5z-bGr-L2HHi83K0,1491
 yowasp_yosys/share/python3/sby_mode_prove.py,sha256=igQAoaxEfO6SSXNm8PeIYV1qWLC9os96V1m7FHAJVKo,1941
 yowasp_yosys/share/python3/sby_sim.py,sha256=HWSLhMOv1RrNXVrmgsibBTf3lHUHUNaAhfnBF2Wx9Bc,4403
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 yowasp_yosys/share/python3/smtio.py,sha256=iaKRFczPE2ml5MpEpvJPcKY9KF_bwyUDuYtOh8v0VGo,48785
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 yowasp_yosys/share/quicklogic/common/cells_sim.v,sha256=XjVURrz_kgf2n32Mq9KKUXAbmKJsazqS87PiznC75Ew,366
@@ -326,8 +326,8 @@ yowasp_yosys/share/xilinx/lutrams_xcu.txt,sha256=gKp15nl9HxZ8zeT0MyKwn1KKx2YTO7i
 yowasp_yosys/share/xilinx/lutrams_xcv.txt,sha256=sfG2qwrRHiFUMAA3JeASE0O_O8SQpxxP75BuQFEXs4c,797
 yowasp_yosys/share/xilinx/lutrams_xcv_map.v,sha256=0l0HfZWulWO0SwehX_NlOh8WU5zkli2yQ8ycR8ud-qg,3209
 yowasp_yosys/share/xilinx/mux_map.v,sha256=HxnY4T58qJMVEzkyIJDmmVxuB3wO9qpMm-vQgfaB_aY,2498
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+yowasp_yosys/share/xilinx/urams.txt,sha256=mhw-IbAw4ahqUbGDYY97D1udmNdDH9h8VnMw4zvgWC4,972
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@@ -335,8 +335,8 @@ yowasp_yosys/share/xilinx/xc5v_dsp_map.v,sha256=I4lg0RQ54fBBba_7NNvUgwS4tQ1yLIsU
 yowasp_yosys/share/xilinx/xc6s_dsp_map.v,sha256=gTxHocB-Dn5G4BplWgri_tLhT6DIO2S0X-yu4iBKYyk,562
 yowasp_yosys/share/xilinx/xc7_dsp_map.v,sha256=zrzreQi7mElrAMtrayxtiO_Bw00S6zsjSjSVcjmJPH0,884
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