yowasp-yosys 0.53.0.0.post912__py3-none-any.whl → 0.54.0.0.post930__py3-none-any.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- yowasp_yosys/share/gatemate/brams_map.v +20 -20
- yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h +4 -0
- yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +1 -0
- yowasp_yosys/share/include/kernel/constids.inc +2 -0
- yowasp_yosys/share/include/kernel/hashlib.h +1 -0
- yowasp_yosys/share/include/kernel/io.h +17 -0
- yowasp_yosys/share/include/kernel/register.h +1 -0
- yowasp_yosys/share/include/kernel/rtlil.h +40 -1
- yowasp_yosys/share/include/kernel/yosys.h +1 -0
- yowasp_yosys/share/include/kernel/yosys_common.h +1 -17
- yowasp_yosys/share/python3/sby_status.py +2 -2
- yowasp_yosys/share/xilinx/urams.txt +22 -0
- yowasp_yosys/share/xilinx/urams_map.v +138 -0
- yowasp_yosys/yosys.wasm +0 -0
- {yowasp_yosys-0.53.0.0.post912.dist-info → yowasp_yosys-0.54.0.0.post930.dist-info}/METADATA +1 -1
- {yowasp_yosys-0.53.0.0.post912.dist-info → yowasp_yosys-0.54.0.0.post930.dist-info}/RECORD +19 -19
- {yowasp_yosys-0.53.0.0.post912.dist-info → yowasp_yosys-0.54.0.0.post930.dist-info}/WHEEL +0 -0
- {yowasp_yosys-0.53.0.0.post912.dist-info → yowasp_yosys-0.54.0.0.post930.dist-info}/entry_points.txt +0 -0
- {yowasp_yosys-0.53.0.0.post912.dist-info → yowasp_yosys-0.54.0.0.post930.dist-info}/top_level.txt +0 -0
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@@ -115,15 +115,15 @@ generate
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.A_CLK(PORT_A_CLK),
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.A_EN(PORT_A_CLK_EN),
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.A_WE(PORT_A_WR_EN),
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-
.A_BM(PORT_A_WR_BE),
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-
.A_DI(PORT_A_WR_DATA),
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+
.A_BM({{(20-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}),
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+
.A_DI({{(20-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}),
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.A_ADDR({PORT_A_ADDR[13:5], 1'b0, PORT_A_ADDR[4:0], 1'b0}),
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.A_DO(PORT_A_RD_DATA),
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.B_CLK(PORT_B_CLK),
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.B_EN(PORT_B_CLK_EN),
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.B_WE(PORT_B_WR_EN),
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-
.B_BM(PORT_B_WR_BE),
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-
.B_DI(PORT_B_WR_DATA),
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+
.B_BM({{(20-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}),
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.B_DI({{(20-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}),
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.B_ADDR({PORT_B_ADDR[13:5], 1'b0, PORT_B_ADDR[4:0], 1'b0}),
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.B_DO(PORT_B_RD_DATA),
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);
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@@ -270,15 +270,15 @@ generate
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.A_CLK(PORT_A_CLK),
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.A_EN(PORT_A_CLK_EN),
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.A_WE(PORT_A_WR_EN),
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-
.A_BM(PORT_A_WR_BE),
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-
.A_DI(PORT_A_WR_DATA),
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.A_BM({{(40-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}),
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.A_DI({{(40-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}),
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.A_ADDR({PORT_A_ADDR[14:0], 1'b0}),
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.A_DO(PORT_A_RD_DATA),
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.B_CLK(PORT_B_CLK),
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.B_EN(PORT_B_CLK_EN),
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.B_WE(PORT_B_WR_EN),
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-
.B_BM(PORT_B_WR_BE),
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.B_DI(PORT_B_WR_DATA),
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.B_BM({{(40-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}),
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.B_DI({{(40-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}),
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.B_ADDR({PORT_B_ADDR[14:0], 1'b0}),
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.B_DO(PORT_B_RD_DATA),
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);
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@@ -429,14 +429,14 @@ generate
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.A_CLK(PORT_A_CLK),
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.A_EN(PORT_A_CLK_EN),
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.A_WE(PORT_A_WR_EN),
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-
.A_BM(PORT_A_WR_BE),
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.A_DI(PORT_A_WR_DATA),
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.A_BM({{(40-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}),
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.A_DI({{(40-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}),
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.A_ADDR({PORT_A_ADDR[14:0], PORT_A_ADDR[15]}),
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.B_CLK(PORT_B_CLK),
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.B_EN(PORT_B_CLK_EN),
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.B_WE(PORT_B_WR_EN),
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.B_BM(PORT_B_WR_BE),
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.B_DI(PORT_B_WR_DATA),
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.B_BM({{(40-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}),
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.B_DI({{(40-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}),
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.B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}),
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);
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CC_BRAM_40K #(
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@@ -584,15 +584,15 @@ generate
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.A_CLK(PORT_A_CLK),
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.A_EN(PORT_A_CLK_EN),
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.A_WE(PORT_A_WR_EN),
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.A_BM(PORT_A_WR_BE),
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.A_DI(PORT_A_WR_DATA),
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.A_BM({{(40-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}),
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.A_DI({{(40-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}),
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.A_DO(PORT_A_RD_DATA),
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.A_ADDR({PORT_A_ADDR[14:0], PORT_A_ADDR[15]}),
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.B_CLK(PORT_B_CLK),
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.B_EN(PORT_B_CLK_EN),
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.B_WE(PORT_B_WR_EN),
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-
.B_BM(PORT_B_WR_BE),
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-
.B_DI(PORT_B_WR_DATA),
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.B_BM({{(40-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}),
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.B_DI({{(40-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}),
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.B_DO(PORT_B_RD_DATA),
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.B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}),
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);
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@@ -710,9 +710,9 @@ generate
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.A_EN(PORT_W_CLK_EN),
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.A_WE(PORT_W_WR_EN),
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.A_BM(PORT_W_WR_BE[19:0]),
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-
.B_BM(PORT_W_WR_BE[39:20]),
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.B_BM({{(40-PORT_W_WIDTH){1'bx}}, PORT_W_WR_BE[39:20]}),
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.A_DI(PORT_W_WR_DATA[19:0]),
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.B_DI(PORT_W_WR_DATA[39:20]),
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.B_DI({{(40-PORT_W_WIDTH){1'bx}}, PORT_W_WR_DATA[39:20]}),
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.A_ADDR({PORT_W_ADDR[13:5], 1'b0, PORT_W_ADDR[4:0], 1'b0}),
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.B_CLK(PORT_R_CLK),
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.B_EN(PORT_R_CLK_EN),
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@@ -865,9 +865,9 @@ generate
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.A_EN(PORT_W_CLK_EN),
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.A_WE(PORT_W_WR_EN),
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.A_BM(PORT_W_WR_BE[39:0]),
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.B_BM(PORT_W_WR_BE[79:40]),
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.B_BM({{(80-PORT_W_WIDTH){1'bx}}, PORT_W_WR_BE[79:40]}),
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.A_DI(PORT_W_WR_DATA[39:0]),
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.B_DI(PORT_W_WR_DATA[79:40]),
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.B_DI({{(80-PORT_W_WIDTH){1'bx}}, PORT_W_WR_DATA[79:40]}),
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.A_ADDR({PORT_W_ADDR[14:0], 1'b0}),
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.B_CLK(PORT_R_CLK),
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.B_EN(PORT_R_CLK_EN),
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@@ -200,6 +200,10 @@ enum cxxrtl_flag {
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// node, such as inputs and dangling wires.
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CXXRTL_UNDRIVEN = 1 << 4,
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// Generated correspond to netlist nodes that correspond to state with an internal name, that
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// need to be saved, but wouldn't otherwise have a debug item generated.
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CXXRTL_GENERATED = 1 << 5,
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// More object flags may be added in the future, but the existing ones will never change.
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};
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@@ -1294,6 +1294,7 @@ struct debug_item : ::cxxrtl_object {
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DRIVEN_SYNC = CXXRTL_DRIVEN_SYNC,
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DRIVEN_COMB = CXXRTL_DRIVEN_COMB,
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UNDRIVEN = CXXRTL_UNDRIVEN,
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GENERATED = CXXRTL_GENERATED,
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};
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debug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {}
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@@ -153,6 +153,7 @@ X(parameter)
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X(PORTID)
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X(PRIORITY)
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X(PRIORITY_MASK)
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X(promoted_if)
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X(Q)
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X(R)
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X(ram_block)
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@@ -184,6 +185,7 @@ X(romstyle)
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X(S)
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X(SET)
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X(SET_POLARITY)
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X(single_bit_vector)
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X(SIZE)
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X(SRC)
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X(src)
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@@ -64,6 +64,23 @@ inline std::string stringf(const char *fmt, ...)
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return string;
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}
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int readsome(std::istream &f, char *s, int n);
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std::string next_token(std::string &text, const char *sep = " \t\r\n", bool long_strings = false);
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std::vector<std::string> split_tokens(const std::string &text, const char *sep = " \t\r\n");
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bool patmatch(const char *pattern, const char *string);
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#if !defined(YOSYS_DISABLE_SPAWN)
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int run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());
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#endif
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std::string get_base_tmpdir();
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std::string make_temp_file(std::string template_str = get_base_tmpdir() + "/yosys_XXXXXX");
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std::string make_temp_dir(std::string template_str = get_base_tmpdir() + "/yosys_XXXXXX");
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bool check_file_exists(const std::string& filename, bool is_exec = false);
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bool check_directory_exists(const std::string& dirname, bool is_exec = false);
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bool is_absolute_path(std::string filename);
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void remove_directory(std::string dirname);
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bool create_directory(const std::string& dirname);
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std::string escape_filename_spaces(const std::string& filename);
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YOSYS_NAMESPACE_END
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#endif // YOSYS_IO_H
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@@ -753,7 +753,26 @@ public:
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std::vector<RTLIL::State>& bits();
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bool as_bool() const;
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// Convert the constant value to a C++ int.
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// NOTE: If the constant is too wide to fit in int (32 bits) this will
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// truncate any higher bits, potentially over/underflowing. Consider using
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// try_as_int, as_int_saturating, or guarding behind convertible_to_int
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// instead.
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int as_int(bool is_signed = false) const;
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// Returns true iff the constant can be converted to an int without
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// over/underflow.
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bool convertible_to_int(bool is_signed = false) const;
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// Returns the constant's value as an int if it can be represented without
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// over/underflow, or std::nullopt otherwise.
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std::optional<int> try_as_int(bool is_signed = false) const;
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// Returns the constant's value as an int if it can be represented without
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// over/underflow, otherwise the max/min value for int depending on the sign.
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int as_int_saturating(bool is_signed = false) const;
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std::string as_string(const char* any = "-") const;
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static Const from_string(const std::string &str);
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std::vector<RTLIL::State> to_bits() const;
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@@ -1130,7 +1149,27 @@ public:
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bool is_onehot(int *pos = nullptr) const;
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bool as_bool() const;
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// Convert the SigSpec to a C++ int, assuming all bits are constant.
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// NOTE: If the value is too wide to fit in int (32 bits) this will
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// truncate any higher bits, potentially over/underflowing. Consider using
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// try_as_int, as_int_saturating, or guarding behind convertible_to_int
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// instead.
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int as_int(bool is_signed = false) const;
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// Returns true iff the SigSpec is constant and can be converted to an int
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// without over/underflow.
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bool convertible_to_int(bool is_signed = false) const;
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// Returns the SigSpec's value as an int if it is a constant and can be
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// represented without over/underflow, or std::nullopt otherwise.
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std::optional<int> try_as_int(bool is_signed = false) const;
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// Returns an all constant SigSpec's value as an int if it can be represented
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// without over/underflow, otherwise the max/min value for int depending on
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// the sign.
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int as_int_saturating(bool is_signed = false) const;
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std::string as_string() const;
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RTLIL::Const as_const() const;
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RTLIL::Wire *as_wire() const;
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@@ -1182,7 +1221,7 @@ struct RTLIL::Selection
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bool boxes = false,
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// the design to select from
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RTLIL::Design *design = nullptr
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-
) :
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) :
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selects_boxes(boxes), complete_selection(full && boxes), full_selection(full && !boxes), current_design(design) { }
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// checks if the given module exists in the current design and is a
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@@ -81,6 +81,7 @@ extern std::set<std::string> yosys_input_files, yosys_output_files;
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// from kernel/version_*.o (cc source generated from Makefile)
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extern const char *yosys_version_str;
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const char* yosys_maybe_version();
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// from passes/cmds/design.cc
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extern std::map<std::string, RTLIL::Design*> saved_designs;
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@@ -252,28 +252,12 @@ inline void memhasher() { if (memhasher_active) memhasher_do(); }
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void yosys_banner();
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int ceil_log2(int x) YS_ATTRIBUTE(const);
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int readsome(std::istream &f, char *s, int n);
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std::string next_token(std::string &text, const char *sep = " \t\r\n", bool long_strings = false);
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-
std::vector<std::string> split_tokens(const std::string &text, const char *sep = " \t\r\n");
|
|
258
|
-
bool patmatch(const char *pattern, const char *string);
|
|
259
|
-
#if !defined(YOSYS_DISABLE_SPAWN)
|
|
260
|
-
int run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());
|
|
261
|
-
#endif
|
|
262
|
-
std::string get_base_tmpdir();
|
|
263
|
-
std::string make_temp_file(std::string template_str = get_base_tmpdir() + "/yosys_XXXXXX");
|
|
264
|
-
std::string make_temp_dir(std::string template_str = get_base_tmpdir() + "/yosys_XXXXXX");
|
|
265
|
-
bool check_file_exists(std::string filename, bool is_exec = false);
|
|
266
|
-
bool check_directory_exists(const std::string& dirname);
|
|
267
|
-
bool is_absolute_path(std::string filename);
|
|
268
|
-
void remove_directory(std::string dirname);
|
|
269
|
-
bool create_directory(const std::string& dirname);
|
|
270
|
-
std::string escape_filename_spaces(const std::string& filename);
|
|
271
|
-
|
|
272
255
|
template<typename T> int GetSize(const T &obj) { return obj.size(); }
|
|
273
256
|
inline int GetSize(RTLIL::Wire *wire);
|
|
274
257
|
|
|
275
258
|
extern int autoidx;
|
|
276
259
|
extern int yosys_xtrace;
|
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260
|
+
extern bool yosys_write_versions;
|
|
277
261
|
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|
278
262
|
RTLIL::IdString new_id(std::string file, int line, std::string func);
|
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279
263
|
RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix);
|
|
@@ -68,8 +68,8 @@ class SbyStatusDb:
|
|
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68
68
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|
|
69
69
|
self.db = sqlite3.connect(path, isolation_level=None, timeout=timeout)
|
|
70
70
|
self.db.row_factory = sqlite3.Row
|
|
71
|
-
self.db.execute("PRAGMA journal_mode=WAL")
|
|
72
|
-
self.db.execute("PRAGMA synchronous=0")
|
|
71
|
+
self.db.execute("PRAGMA journal_mode=WAL").fetchone()
|
|
72
|
+
self.db.execute("PRAGMA synchronous=0").fetchone()
|
|
73
73
|
|
|
74
74
|
if setup:
|
|
75
75
|
self._setup()
|
|
@@ -35,3 +35,25 @@ ram huge $__XILINX_URAM_ {
|
|
|
35
35
|
wrbe_separate;
|
|
36
36
|
}
|
|
37
37
|
}
|
|
38
|
+
|
|
39
|
+
ram huge $__XILINX_URAM_SP_ {
|
|
40
|
+
abits 11;
|
|
41
|
+
width 144;
|
|
42
|
+
cost 1024;
|
|
43
|
+
option "BYTEWIDTH" 8 byte 8;
|
|
44
|
+
option "BYTEWIDTH" 9 byte 9;
|
|
45
|
+
init zero;
|
|
46
|
+
port srsw "A" {
|
|
47
|
+
clock anyedge "C";
|
|
48
|
+
clken;
|
|
49
|
+
rdwr no_change;
|
|
50
|
+
rdinit zero;
|
|
51
|
+
portoption "RST_MODE" "SYNC" {
|
|
52
|
+
rdsrst zero ungated;
|
|
53
|
+
}
|
|
54
|
+
portoption "RST_MODE" "ASYNC" {
|
|
55
|
+
rdarst zero;
|
|
56
|
+
}
|
|
57
|
+
wrbe_separate;
|
|
58
|
+
}
|
|
59
|
+
}
|
|
@@ -150,3 +150,141 @@ module $__XILINX_URAM_ (...);
|
|
|
150
150
|
.SLEEP(1'b0)
|
|
151
151
|
);
|
|
152
152
|
endmodule
|
|
153
|
+
|
|
154
|
+
module $__XILINX_URAM_SP_ (...);
|
|
155
|
+
parameter OPTION_BYTEWIDTH = 8;
|
|
156
|
+
localparam WR_BE_WIDTH = 144 / OPTION_BYTEWIDTH;
|
|
157
|
+
|
|
158
|
+
parameter CLK_C_POL = 1;
|
|
159
|
+
parameter PORT_A_CLK_POL = 1;
|
|
160
|
+
parameter PORT_A_OPTION_RST_MODE = "SYNC";
|
|
161
|
+
|
|
162
|
+
input CLK_C;
|
|
163
|
+
|
|
164
|
+
input PORT_A_CLK;
|
|
165
|
+
input PORT_A_CLK_EN;
|
|
166
|
+
input PORT_A_RD_SRST;
|
|
167
|
+
input PORT_A_RD_ARST;
|
|
168
|
+
input PORT_A_WR_EN;
|
|
169
|
+
input [WR_BE_WIDTH-1:0] PORT_A_WR_BE;
|
|
170
|
+
input [10:0] PORT_A_ADDR;
|
|
171
|
+
input [143:0] PORT_A_WR_DATA;
|
|
172
|
+
output [143:0] PORT_A_RD_DATA;
|
|
173
|
+
|
|
174
|
+
wire [71:0] DIN_A, DIN_B, DOUT_A, DOUT_B;
|
|
175
|
+
|
|
176
|
+
generate
|
|
177
|
+
if (OPTION_BYTEWIDTH == 8) begin
|
|
178
|
+
assign DIN_A = PORT_A_WR_DATA[71:0];
|
|
179
|
+
assign DIN_B = PORT_A_WR_DATA[143:72];
|
|
180
|
+
assign PORT_A_RD_DATA = {DOUT_B, DOUT_A};
|
|
181
|
+
end else begin
|
|
182
|
+
assign DIN_A = {
|
|
183
|
+
PORT_A_WR_DATA[71],
|
|
184
|
+
PORT_A_WR_DATA[62],
|
|
185
|
+
PORT_A_WR_DATA[53],
|
|
186
|
+
PORT_A_WR_DATA[44],
|
|
187
|
+
PORT_A_WR_DATA[35],
|
|
188
|
+
PORT_A_WR_DATA[26],
|
|
189
|
+
PORT_A_WR_DATA[17],
|
|
190
|
+
PORT_A_WR_DATA[8],
|
|
191
|
+
PORT_A_WR_DATA[70:63],
|
|
192
|
+
PORT_A_WR_DATA[61:54],
|
|
193
|
+
PORT_A_WR_DATA[52:45],
|
|
194
|
+
PORT_A_WR_DATA[43:36],
|
|
195
|
+
PORT_A_WR_DATA[34:27],
|
|
196
|
+
PORT_A_WR_DATA[25:18],
|
|
197
|
+
PORT_A_WR_DATA[16:9],
|
|
198
|
+
PORT_A_WR_DATA[7:0]
|
|
199
|
+
};
|
|
200
|
+
assign DIN_B = {
|
|
201
|
+
PORT_A_WR_DATA[72+71],
|
|
202
|
+
PORT_A_WR_DATA[72+62],
|
|
203
|
+
PORT_A_WR_DATA[72+53],
|
|
204
|
+
PORT_A_WR_DATA[72+44],
|
|
205
|
+
PORT_A_WR_DATA[72+35],
|
|
206
|
+
PORT_A_WR_DATA[72+26],
|
|
207
|
+
PORT_A_WR_DATA[72+17],
|
|
208
|
+
PORT_A_WR_DATA[72+8],
|
|
209
|
+
PORT_A_WR_DATA[72+70:72+63],
|
|
210
|
+
PORT_A_WR_DATA[72+61:72+54],
|
|
211
|
+
PORT_A_WR_DATA[72+52:72+45],
|
|
212
|
+
PORT_A_WR_DATA[72+43:72+36],
|
|
213
|
+
PORT_A_WR_DATA[72+34:72+27],
|
|
214
|
+
PORT_A_WR_DATA[72+25:72+18],
|
|
215
|
+
PORT_A_WR_DATA[72+16:72+ 9],
|
|
216
|
+
PORT_A_WR_DATA[72+ 7:72+ 0]
|
|
217
|
+
};
|
|
218
|
+
assign PORT_A_RD_DATA = {
|
|
219
|
+
DOUT_B[71],
|
|
220
|
+
DOUT_B[63:56],
|
|
221
|
+
DOUT_B[70],
|
|
222
|
+
DOUT_B[55:48],
|
|
223
|
+
DOUT_B[69],
|
|
224
|
+
DOUT_B[47:40],
|
|
225
|
+
DOUT_B[68],
|
|
226
|
+
DOUT_B[39:32],
|
|
227
|
+
DOUT_B[67],
|
|
228
|
+
DOUT_B[31:24],
|
|
229
|
+
DOUT_B[66],
|
|
230
|
+
DOUT_B[23:16],
|
|
231
|
+
DOUT_B[65],
|
|
232
|
+
DOUT_B[15:8],
|
|
233
|
+
DOUT_B[64],
|
|
234
|
+
DOUT_B[7:0],
|
|
235
|
+
DOUT_A[71],
|
|
236
|
+
DOUT_A[63:56],
|
|
237
|
+
DOUT_A[70],
|
|
238
|
+
DOUT_A[55:48],
|
|
239
|
+
DOUT_A[69],
|
|
240
|
+
DOUT_A[47:40],
|
|
241
|
+
DOUT_A[68],
|
|
242
|
+
DOUT_A[39:32],
|
|
243
|
+
DOUT_A[67],
|
|
244
|
+
DOUT_A[31:24],
|
|
245
|
+
DOUT_A[66],
|
|
246
|
+
DOUT_A[23:16],
|
|
247
|
+
DOUT_A[65],
|
|
248
|
+
DOUT_A[15:8],
|
|
249
|
+
DOUT_A[64],
|
|
250
|
+
DOUT_A[7:0]
|
|
251
|
+
};
|
|
252
|
+
end
|
|
253
|
+
endgenerate
|
|
254
|
+
|
|
255
|
+
URAM288 #(
|
|
256
|
+
.BWE_MODE_A(OPTION_BYTEWIDTH == 8 ? "PARITY_INDEPENDENT" : "PARITY_INTERLEAVED"),
|
|
257
|
+
.BWE_MODE_B(OPTION_BYTEWIDTH == 8 ? "PARITY_INDEPENDENT" : "PARITY_INTERLEAVED"),
|
|
258
|
+
.EN_AUTO_SLEEP_MODE("FALSE"),
|
|
259
|
+
.IREG_PRE_A("FALSE"),
|
|
260
|
+
.IREG_PRE_B("FALSE"),
|
|
261
|
+
.IS_CLK_INVERTED(!CLK_C_POL),
|
|
262
|
+
.OREG_A("FALSE"),
|
|
263
|
+
.OREG_B("FALSE"),
|
|
264
|
+
.RST_MODE_A(PORT_A_OPTION_RST_MODE),
|
|
265
|
+
.RST_MODE_B(PORT_A_OPTION_RST_MODE),
|
|
266
|
+
) _TECHMAP_REPLACE_ (
|
|
267
|
+
.ADDR_A({11'b0, PORT_A_ADDR, 1'b0}),
|
|
268
|
+
.BWE_A(PORT_A_WR_BE[WR_BE_WIDTH/2-1:0]),
|
|
269
|
+
.EN_A(PORT_A_CLK_EN),
|
|
270
|
+
.RDB_WR_A(PORT_A_WR_EN),
|
|
271
|
+
.INJECT_DBITERR_A(1'b0),
|
|
272
|
+
.INJECT_SBITERR_A(1'b0),
|
|
273
|
+
.RST_A(PORT_A_OPTION_RST_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
|
|
274
|
+
.DIN_A(DIN_A),
|
|
275
|
+
.DOUT_A(DOUT_A),
|
|
276
|
+
|
|
277
|
+
.ADDR_B({11'b0, PORT_A_ADDR, 1'b1}),
|
|
278
|
+
.BWE_B(PORT_A_WR_BE[WR_BE_WIDTH-1:WR_BE_WIDTH/2]),
|
|
279
|
+
.EN_B(PORT_A_CLK_EN),
|
|
280
|
+
.RDB_WR_B(PORT_A_WR_EN),
|
|
281
|
+
.INJECT_DBITERR_B(1'b0),
|
|
282
|
+
.INJECT_SBITERR_B(1'b0),
|
|
283
|
+
.RST_B(PORT_A_OPTION_RST_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
|
|
284
|
+
.DIN_B(DIN_B),
|
|
285
|
+
.DOUT_B(DOUT_B),
|
|
286
|
+
|
|
287
|
+
.CLK(CLK_C),
|
|
288
|
+
.SLEEP(1'b0)
|
|
289
|
+
);
|
|
290
|
+
endmodule
|
yowasp_yosys/yosys.wasm
CHANGED
|
Binary file
|
|
@@ -2,7 +2,7 @@ yowasp_yosys/__init__.py,sha256=x--xPTzLWZNoX6H0B2E3a1HMZMk3di10gVnWVLJ92xc,1325
|
|
|
2
2
|
yowasp_yosys/sby.py,sha256=at4UB7rmju4xhmFP6b31T7duU2Hx5aSOgGUiExKz7Xc,18496
|
|
3
3
|
yowasp_yosys/smtbmc.py,sha256=yiI93tHys5c8aXfCdk2dNtw2mwukRXqeT8YGx5Th8eg,74231
|
|
4
4
|
yowasp_yosys/witness.py,sha256=m3iV2Nydm0p4G79VRaaX3lGul-nGnuxeKnx20MCJgi0,17279
|
|
5
|
-
yowasp_yosys/yosys.wasm,sha256=
|
|
5
|
+
yowasp_yosys/yosys.wasm,sha256=nsK36QxHJaabNlfIVNUjx_Kf0G0H-4Aqjh-2xe3boMY,30828960
|
|
6
6
|
yowasp_yosys/share/abc9_map.v,sha256=uWDqMpBQTeeadH1BlHVwkCy2StKF892xbgBgMKLK5-w,923
|
|
7
7
|
yowasp_yosys/share/abc9_model.v,sha256=IfMyEGOEUBdZyiVule0wMhrVYVYQpmSIcxygbgtHItI,653
|
|
8
8
|
yowasp_yosys/share/abc9_unmap.v,sha256=w107Y3iJjMU6D_6_aYLf2NziXTnAhpa5_CFAwaYO1iU,638
|
|
@@ -67,7 +67,7 @@ yowasp_yosys/share/gatemate/arith_map.v,sha256=U8Lz8wj0WpUh9YP89MVQfkgYcw4xYE0XW
|
|
|
67
67
|
yowasp_yosys/share/gatemate/brams.txt,sha256=mtysGrMGltlSw98eOHSSrN38xzQmkxVbfgTivQrZ5qk,1210
|
|
68
68
|
yowasp_yosys/share/gatemate/brams_init_20.vh,sha256=PKYSRZOL_i6Fmjy1dB-lF0eSlV8BFLjGvDqrw6zhLpw,4480
|
|
69
69
|
yowasp_yosys/share/gatemate/brams_init_40.vh,sha256=yK50gQK1Kc59RxbbV9xjeWohhInkyZ3g6N5WmtpqMug,17970
|
|
70
|
-
yowasp_yosys/share/gatemate/brams_map.v,sha256=
|
|
70
|
+
yowasp_yosys/share/gatemate/brams_map.v,sha256=dZlYuJQUzZ6bBNx41Lwyg3pvhDqMeAO7fqR0LACP1XM,29978
|
|
71
71
|
yowasp_yosys/share/gatemate/cells_bb.v,sha256=cc9cOL12VXqvKf6JV4r3XD2dSx4O_2Q8L0yWMlTog3A,11964
|
|
72
72
|
yowasp_yosys/share/gatemate/cells_sim.v,sha256=WRAD7MrD6K_aNQE8AM4yCldphCksCImFKnguMLj9bd4,65936
|
|
73
73
|
yowasp_yosys/share/gatemate/inv_map.v,sha256=UpmZftbrZGv7K8od1rjId099dTuqQyaP7z4z-V3hQgI,180
|
|
@@ -106,12 +106,12 @@ yowasp_yosys/share/ice40/ff_map.v,sha256=0ikq-i1_UVT6xuFLMj2Zfilwu6wz8oibMdtPegZ
|
|
|
106
106
|
yowasp_yosys/share/ice40/latches_map.v,sha256=V5NwBaIML68eOlhDaUJUs8W-ggRePjPsDtUn3mnSpao,258
|
|
107
107
|
yowasp_yosys/share/ice40/spram.txt,sha256=dCRV0flfJunvnvKV0Q5Kq5NBrhh_PkZGXvUt675aiIk,153
|
|
108
108
|
yowasp_yosys/share/ice40/spram_map.v,sha256=O8fRkVuH1dgAXEAtYJgh8wTHnZEK75fPAMBI-PgYVqs,475
|
|
109
|
-
yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h,sha256=
|
|
109
|
+
yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h,sha256=8ngxTSDlfd24wEl05RP_K_9BflHxxATY-oZMfNaQO5E,72525
|
|
110
110
|
yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h,sha256=3bFAy3nYtaH4MsLI9Kvf88K6BYOkML8plDMxmPtPdss,30008
|
|
111
111
|
yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h,sha256=6zIxuXG7bXy5UWe7WuA_KQHiwV7VWvcsNecwOPAL_bU,6174
|
|
112
112
|
yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h,sha256=L4VOOx7c9rGkxTFi8VjhhNGEbuzxf_j6P5D0_0n0WjA,8637
|
|
113
113
|
yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc,sha256=4WH8B0B7Y7GY43BXZX0-6PGFPYcbOcavJseI0wM_VJQ,4559
|
|
114
|
-
yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h,sha256=
|
|
114
|
+
yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h,sha256=LlNWnjmxKqUHJeaJOaXT9OMAYq-G0GLgVzQvsYkCb_U,16719
|
|
115
115
|
yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc,sha256=5A6IK46tg8BWgs_vzS183p9HMZfWP7FZfJzCjnB3vW8,2815
|
|
116
116
|
yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h,sha256=P6KBEs-76IK4LwKBhXbju9nwkH3rmmqUm4uSuiaS88M,4286
|
|
117
117
|
yowasp_yosys/share/include/backends/rtlil/rtlil_backend.h,sha256=h-kkdWtAosSZDzvAW511jAHao-dDUm3fyTJhfMXsZDk,2407
|
|
@@ -124,7 +124,7 @@ yowasp_yosys/share/include/kernel/cellaigs.h,sha256=CdYos67IpmAgLvBbJ8EC3hWg6WhB
|
|
|
124
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