yowasp-yosys 0.52.0.0.post894__py3-none-any.whl → 0.53.0.0.post912__py3-none-any.whl

yowasp_yosys/share/ecp5/cells_sim.v

@@ -386,7 +386,7 @@ module TRELLIS_IO(
 );
 	parameter DIR = "INPUT";
 	reg T_pd;
-	always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
+	always @(*) if (T === 1'bz) T_pd = 1'b0; else T_pd = T;
 
 	generate
 		if (DIR == "INPUT") begin

yowasp_yosys/share/gatemate/brams.txt

@@ -34,7 +34,6 @@ ram block $__CC_BRAM_TDP_ {
 		}
 		portoption "WR_MODE" "WRITE_THROUGH" {
 			rdwr new;
-			wrtrans all new;
 		}
 		wrbe_separate;
 		optional_rw;

yowasp_yosys/share/gatemate/cells_sim.v

@@ -292,10 +292,10 @@ module CC_DLT #(
 	always @(*)
 	begin
 		if (sr) begin
-			Q <= SR_VAL;
+			Q = SR_VAL;
 		end
 		else if (en) begin
-			Q <= D;
+			Q = D;
 		end
 	end
 
@@ -407,7 +407,7 @@ module CC_MULT #(
 );
 	always @(*)
 	begin
-		P <= A * B;
+		P = A * B;
 	end
 endmodule
 

yowasp_yosys/share/greenpak4/cells_sim_digital.v

@@ -48,7 +48,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 
 	//Combinatorially output underflow flag whenever we wrap low
 	always @(*) begin
-		OUT <= (count == 14'h0);
+		OUT = (count == 14'h0);
 	end
 
 	//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
@@ -133,10 +133,10 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 	//Combinatorially output underflow flag whenever we wrap low
 	always @(*) begin
 		if(UP)
-			OUT <= (count == 14'h3fff);
+			OUT = (count == 14'h3fff);
 		else
-			OUT <= (count == 14'h0);
-		POUT <= count[7:0];
+			OUT = (count == 14'h0);
+		POUT = count[7:0];
 	end
 
 	//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
@@ -272,10 +272,10 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 	//Combinatorially output underflow flag whenever we wrap low
 	always @(*) begin
 		if(UP)
-			OUT <= (count == 8'hff);
+			OUT = (count == 8'hff);
 		else
-			OUT <= (count == 8'h0);
-		POUT <= count;
+			OUT = (count == 8'h0);
+		POUT = count;
 	end
 
 	//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
@@ -413,8 +413,8 @@ module GP_COUNT8(
 
 	//Combinatorially output underflow flag whenever we wrap low
 	always @(*) begin
-		OUT <= (count == 8'h0);
-		POUT <= count;
+		OUT = (count == 8'h0);
+		POUT = count;
 	end
 
 	//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
@@ -488,23 +488,23 @@ module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2
 	always @(*) begin
 		case(SEL)
 			2'd00: begin
-				OUTA <= IN0;
-				OUTB <= IN3;
+				OUTA = IN0;
+				OUTB = IN3;
 			end
 
 			2'd01: begin
-				OUTA <= IN1;
-				OUTB <= IN2;
+				OUTA = IN1;
+				OUTB = IN2;
 			end
 
 			2'd02: begin
-				OUTA <= IN2;
-				OUTB <= IN1;
+				OUTA = IN2;
+				OUTB = IN1;
 			end
 
 			2'd03: begin
-				OUTA <= IN3;
-				OUTB <= IN0;
+				OUTA = IN3;
+				OUTB = IN0;
 			end
 
 		endcase
@@ -635,7 +635,7 @@ module GP_DLATCH(input D, input nCLK, output reg Q);
 	initial Q = INIT;
 	always @(*) begin
 		if(!nCLK)
-			Q <= D;
+			Q = D;
 	end
 endmodule
 
@@ -644,7 +644,7 @@ module GP_DLATCHI(input D, input nCLK, output reg nQ);
 	initial nQ = INIT;
 	always @(*) begin
 		if(!nCLK)
-			nQ <= ~D;
+			nQ = ~D;
 	end
 endmodule
 
@@ -653,9 +653,9 @@ module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
 	initial Q = INIT;
 	always @(*) begin
 		if(!nRST)
-			Q <= 1'b0;
+			Q = 1'b0;
 		else if(!nCLK)
-			Q <= D;
+			Q = D;
 	end
 endmodule
 
@@ -664,9 +664,9 @@ module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
 	initial nQ = INIT;
 	always @(*) begin
 		if(!nRST)
-			nQ <= 1'b1;
+			nQ = 1'b1;
 		else if(!nCLK)
-			nQ <= ~D;
+			nQ = ~D;
 	end
 endmodule
 
@@ -675,9 +675,9 @@ module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
 	initial Q = INIT;
 	always @(*) begin
 		if(!nSET)
-			Q <= 1'b1;
+			Q = 1'b1;
 		else if(!nCLK)
-			Q <= D;
+			Q = D;
 	end
 endmodule
 
@@ -686,9 +686,9 @@ module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
 	initial nQ = INIT;
 	always @(*) begin
 		if(!nSET)
-			nQ <= 1'b0;
+			nQ = 1'b0;
 		else if(!nCLK)
-			nQ <= ~D;
+			nQ = ~D;
 	end
 endmodule
 
@@ -698,9 +698,9 @@ module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
 	initial Q = INIT;
 	always @(*) begin
 		if(!nSR)
-			Q <= SRMODE;
+			Q = SRMODE;
 		else if(!nCLK)
-			Q <= D;
+			Q = D;
 	end
 endmodule
 
@@ -710,9 +710,9 @@ module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
 	initial nQ = INIT;
 	always @(*) begin
 		if(!nSR)
-			nQ <= ~SRMODE;
+			nQ = ~SRMODE;
 		else if(!nCLK)
-			nQ <= ~D;
+			nQ = ~D;
 	end
 endmodule
 

yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h

@@ -498,6 +498,11 @@ struct value : public expr_base<value<Bits>> {
 		return result;
 	}
 
+	CXXRTL_ALWAYS_INLINE
+	value<Bits> bwmux(const value<Bits> &b, const value<Bits> &s) const {
+		return (bit_and(s.bit_not())).bit_or(b.bit_and(s));
+	}
+
 	template<size_t ResultBits, size_t SelBits>
 	value<ResultBits> demux(const value<SelBits> &sel) const {
 		static_assert(Bits << SelBits == ResultBits, "invalid sizes used in demux()");
@@ -1764,7 +1769,7 @@ value<BitsY> shr_uu(const value<BitsA> &a, const value<BitsB> &b) {
 template<size_t BitsY, size_t BitsA, size_t BitsB>
 CXXRTL_ALWAYS_INLINE
 value<BitsY> shr_su(const value<BitsA> &a, const value<BitsB> &b) {
-	return a.shr(b).template scast<BitsY>();
+	return a.template scast<BitsY>().shr(b);
 }
 
 template<size_t BitsY, size_t BitsA, size_t BitsB>
@@ -2005,7 +2010,7 @@ std::pair<value<BitsY>, value<BitsY>> divmod_uu(const value<BitsA> &a, const val
 	value<Bits> quotient;
 	value<Bits> remainder;
 	value<Bits> dividend = a.template zext<Bits>();
-	value<Bits> divisor = b.template zext<Bits>();
+	value<Bits> divisor  = b.template trunc<BitsB>().template zext<Bits>();
 	std::tie(quotient, remainder) = dividend.udivmod(divisor);
 	return {quotient.template trunc<BitsY>(), remainder.template trunc<BitsY>()};
 }

yowasp_yosys/share/include/kernel/consteval.h

@@ -315,7 +315,7 @@ struct ConstEval
 			Macc macc;
 			macc.from_cell(cell);
 
-			for (auto &port : macc.ports) {
+			for (auto &port : macc.terms) {
 				if (!eval(port.in_a, undef, cell))
 					return false;
 				if (!eval(port.in_b, undef, cell))

yowasp_yosys/share/include/kernel/macc.h

@@ -26,18 +26,18 @@ YOSYS_NAMESPACE_BEGIN
 
 struct Macc
 {
-	struct port_t {
+	struct term_t {
 		RTLIL::SigSpec in_a, in_b;
 		bool is_signed, do_subtract;
 	};
-	std::vector<port_t> ports;
+	std::vector<term_t> terms;
 
 	void optimize(int width)
 	{
-		std::vector<port_t> new_ports;
+		std::vector<term_t> new_terms;
 		RTLIL::Const off(0, width);
 
-		for (auto &port : ports)
+		for (auto &port : terms)
 		{
 			if (GetSize(port.in_a) == 0 && GetSize(port.in_b) == 0)
 				continue;
@@ -68,25 +68,25 @@ struct Macc
 					port.in_b.remove(GetSize(port.in_b)-1);
 			}
 
-			new_ports.push_back(port);
+			new_terms.push_back(port);
 		}
 
 		if (off.as_bool()) {
-			port_t port;
+			term_t port;
 			port.in_a = off;
 			port.is_signed = false;
 			port.do_subtract = false;
-			new_ports.push_back(port);
+			new_terms.push_back(port);
 		}
 
-		new_ports.swap(ports);
+		new_terms.swap(terms);
 	}
 
 	void from_cell_v1(RTLIL::Cell *cell)
 	{
 		RTLIL::SigSpec port_a = cell->getPort(ID::A);
 
-		ports.clear();
+		terms.clear();
 
 		auto config_bits = cell->getParam(ID::CONFIG);
 		int config_cursor = 0;
@@ -105,7 +105,7 @@ struct Macc
 		{
 			log_assert(config_cursor + 2 + 2*num_bits <= config_width);
 
-			port_t this_port;
+			term_t this_port;
 			this_port.is_signed = config_bits[config_cursor++] == State::S1;
 			this_port.do_subtract = config_bits[config_cursor++] == State::S1;
 
@@ -126,11 +126,11 @@ struct Macc
 			port_a_cursor += size_b;
 
 			if (size_a || size_b)
-				ports.push_back(this_port);
+				terms.push_back(this_port);
 		}
 
 		for (auto bit : cell->getPort(ID::B))
-			ports.push_back(port_t{{bit}, {}, false, false});
+			terms.push_back(term_t{{bit}, {}, false, false});
 
 		log_assert(config_cursor == config_width);
 		log_assert(port_a_cursor == GetSize(port_a));
@@ -148,7 +148,7 @@ struct Macc
 		RTLIL::SigSpec port_b = cell->getPort(ID::B);
 		RTLIL::SigSpec port_c = cell->getPort(ID::C);
 
-		ports.clear();
+		terms.clear();
 
 		int nproducts = cell->getParam(ID::NPRODUCTS).as_int();
 		const Const &product_neg = cell->getParam(ID::PRODUCT_NEGATED);
@@ -158,7 +158,7 @@ struct Macc
 		const Const &b_signed = cell->getParam(ID::B_SIGNED);
 		int ai = 0, bi = 0;
 		for (int i = 0; i < nproducts; i++) {
-			port_t term;
+			term_t term;
 
 			log_assert(a_signed[i] == b_signed[i]);
 			term.is_signed = (a_signed[i] == State::S1);
@@ -171,7 +171,7 @@ struct Macc
 			bi += b_width;
 			term.do_subtract = (product_neg[i] == State::S1);
 
-			ports.push_back(term);
+			terms.push_back(term);
 		}
 		log_assert(port_a.size() == ai);
 		log_assert(port_b.size() == bi);
@@ -182,7 +182,7 @@ struct Macc
 		const Const &c_signed = cell->getParam(ID::C_SIGNED);
 		int ci = 0;
 		for (int i = 0; i < naddends; i++) {
-			port_t term;
+			term_t term;
 
 			term.is_signed = (c_signed[i] == State::S1);
 			int c_width = c_widths.extract(16 * i, 16).as_int(false);
@@ -191,7 +191,7 @@ struct Macc
 			ci += c_width;
 			term.do_subtract = (addend_neg[i] == State::S1);
 
-			ports.push_back(term);
+			terms.push_back(term);
 		}
 		log_assert(port_c.size() == ci);
 	}
@@ -205,23 +205,23 @@ struct Macc
 		Const c_signed, c_widths, addend_negated;
 		SigSpec a, b, c;
 
-		for (int i = 0; i < (int) ports.size(); i++) {
-			SigSpec term_a = ports[i].in_a, term_b = ports[i].in_b;
+		for (int i = 0; i < (int) terms.size(); i++) {
+			SigSpec term_a = terms[i].in_a, term_b = terms[i].in_b;
 
 			if (term_b.empty()) {
 				// addend
 				c_widths.append(Const(term_a.size(), 16));
-				c_signed.append(ports[i].is_signed ? RTLIL::S1 : RTLIL::S0);
-				addend_negated.append(ports[i].do_subtract ? RTLIL::S1 : RTLIL::S0);
+				c_signed.append(terms[i].is_signed ? RTLIL::S1 : RTLIL::S0);
+				addend_negated.append(terms[i].do_subtract ? RTLIL::S1 : RTLIL::S0);
 				c.append(term_a);
 				naddends++;
 			} else {
 				// product
 				a_widths.append(Const(term_a.size(), 16));
 				b_widths.append(Const(term_b.size(), 16));
-				a_signed.append(ports[i].is_signed ? RTLIL::S1 : RTLIL::S0);
-				b_signed.append(ports[i].is_signed ? RTLIL::S1 : RTLIL::S0);
-				product_negated.append(ports[i].do_subtract ? RTLIL::S1 : RTLIL::S0);
+				a_signed.append(terms[i].is_signed ? RTLIL::S1 : RTLIL::S0);
+				b_signed.append(terms[i].is_signed ? RTLIL::S1 : RTLIL::S0);
+				product_negated.append(terms[i].do_subtract ? RTLIL::S1 : RTLIL::S0);
 				a.append(term_a);
 				b.append(term_b);
 				nproducts++;
@@ -265,7 +265,7 @@ struct Macc
 		for (auto &bit : result.bits())
 			bit = State::S0;
 
-		for (auto &port : ports)
+		for (auto &port : terms)
 		{
 			if (!port.in_a.is_fully_const() || !port.in_b.is_fully_const())
 				return false;
@@ -287,9 +287,9 @@ struct Macc
 
 	bool is_simple_product()
 	{
-		return ports.size() == 1 &&
-				!ports[0].in_b.empty() &&
-				!ports[0].do_subtract;
+		return terms.size() == 1 &&
+				!terms[0].in_b.empty() &&
+				!terms[0].do_subtract;
 	}
 
 	Macc(RTLIL::Cell *cell = nullptr)

yowasp_yosys/share/include/kernel/rtlil.h

@@ -56,8 +56,33 @@ namespace RTLIL
 		CONST_FLAG_REAL   = 4   // only used for parameters
 	};
 
+	enum SelectPartials : unsigned char {
+		SELECT_ALL = 0,          // include partial modules
+		SELECT_WHOLE_ONLY = 1,   // ignore partial modules
+		SELECT_WHOLE_WARN = 2,   // call log_warning on partial module
+		SELECT_WHOLE_ERR = 3,    // call log_error on partial module
+		SELECT_WHOLE_CMDERR = 4  // call log_cmd_error on partial module
+	};
+
+	enum SelectBoxes : unsigned char {
+		SB_ALL = 0,            // include boxed modules
+		SB_WARN = 1,           // helper for log_warning (not for direct use)
+		SB_ERR = 2,            // helper for log_error (not for direct use)
+		SB_CMDERR = 3,         // helper for log_cmd_error (not for direct use)
+		SB_UNBOXED_ONLY = 4,   // ignore boxed modules
+		SB_UNBOXED_WARN = 5,   // call log_warning on boxed module
+		SB_UNBOXED_ERR = 6,    // call log_error on boxed module
+		SB_UNBOXED_CMDERR = 7, // call log_cmd_error on boxed module
+		SB_INCL_WB = 8,        // helper for white boxes (not for direct use)
+		SB_EXCL_BB_ONLY = 12,  // ignore black boxes, but not white boxes
+		SB_EXCL_BB_WARN = 13,  // call log_warning on black boxed module
+		SB_EXCL_BB_ERR = 14,   // call log_error on black boxed module
+		SB_EXCL_BB_CMDERR = 15 // call log_cmd_error on black boxed module
+	};
+
 	struct Const;
 	struct AttrObject;
+	struct NamedObject;
 	struct Selection;
 	struct Monitor;
 	struct Design;
@@ -869,6 +894,11 @@ struct RTLIL::AttrObject
 	vector<int> get_intvec_attribute(const RTLIL::IdString &id) const;
 };
 
+struct RTLIL::NamedObject : public RTLIL::AttrObject
+{
+	RTLIL::IdString name;
+};
+
 struct RTLIL::SigChunk
 {
 	RTLIL::Wire *wire;
@@ -1134,32 +1164,94 @@ public:
 
 struct RTLIL::Selection
 {
+	// selection includes boxed modules
+	bool selects_boxes;
+	// selection covers full design, including boxed modules
+	bool complete_selection;
+	// selection covers full design, not including boxed modules
 	bool full_selection;
 	pool<RTLIL::IdString> selected_modules;
 	dict<RTLIL::IdString, pool<RTLIL::IdString>> selected_members;
-
-	Selection(bool full = true) : full_selection(full) { }
-
+	RTLIL::Design *current_design;
+
+	// create a new selection
+	Selection(
+		// should the selection cover the full design
+		bool full = true,
+		// should the selection include boxed modules
+		bool boxes = false,
+		// the design to select from
+		RTLIL::Design *design = nullptr
+	) : 
+		selects_boxes(boxes), complete_selection(full && boxes), full_selection(full && !boxes), current_design(design) { }
+
+	// checks if the given module exists in the current design and is a
+	// boxed module, warning the user if the current design is not set
+	bool boxed_module(const RTLIL::IdString &mod_name) const;
+
+	// checks if the given module is included in this selection
 	bool selected_module(const RTLIL::IdString &mod_name) const;
+
+	// checks if the given module is wholly included in this selection,
+	// i.e. not partially selected
 	bool selected_whole_module(const RTLIL::IdString &mod_name) const;
+
+	// checks if the given member from the given module is included in this
+	// selection
 	bool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;
+
+	// optimizes this selection for the given design by:
+	// - removing non-existent modules and members, any boxed modules and
+	//   their members (if selection does not include boxes), and any
+	//   partially selected modules with no selected members;
+	// - marking partially selected modules as wholly selected if all
+	//   members of that module are selected; and
+	// - marking selection as a complete_selection if all modules in the
+	//   given design are selected, or a full_selection if it does not
+	//   include boxes.
 	void optimize(RTLIL::Design *design);
 
+	// checks if selection covers full design (may or may not include
+	// boxed-modules)
+	bool selects_all() const {
+		return full_selection || complete_selection;
+	}
+
+	// add whole module to this selection
 	template<typename T1> void select(T1 *module) {
-		if (!full_selection && selected_modules.count(module->name) == 0) {
+		if (!selects_all() && selected_modules.count(module->name) == 0) {
 			selected_modules.insert(module->name);
 			selected_members.erase(module->name);
+			if (module->get_blackbox_attribute())
+				selects_boxes = true;
 		}
 	}
 
+	// add member of module to this selection
 	template<typename T1, typename T2> void select(T1 *module, T2 *member) {
-		if (!full_selection && selected_modules.count(module->name) == 0)
+		if (!selects_all() && selected_modules.count(module->name) == 0) {
 			selected_members[module->name].insert(member->name);
+			if (module->get_blackbox_attribute())
+				selects_boxes = true;
+		}
 	}
 
+	// checks if selection is empty
 	bool empty() const {
-		return !full_selection && selected_modules.empty() && selected_members.empty();
+		return !selects_all() && selected_modules.empty() && selected_members.empty();
 	}
+
+	// clear this selection, leaving it empty
+	void clear();
+
+	// create a new selection which is empty
+	static Selection EmptySelection(RTLIL::Design *design = nullptr) { return Selection(false, false, design); };
+
+	// create a new selection with all non-boxed modules
+	static Selection FullSelection(RTLIL::Design *design = nullptr) { return Selection(true, false, design); };
+
+	// create a new selection with all modules, including boxes
+	static Selection CompleteSelection(RTLIL::Design *design = nullptr) { return Selection(true, true, design); };
 };
 
 struct RTLIL::Monitor
@@ -1213,7 +1305,7 @@ struct RTLIL::Design
 	RTLIL::ObjRange<RTLIL::Module*> modules();
 	RTLIL::Module *module(const RTLIL::IdString &name);
 	const RTLIL::Module *module(const RTLIL::IdString &name) const;
-	RTLIL::Module *top_module();
+	RTLIL::Module *top_module() const;
 
 	bool has(const RTLIL::IdString &id) const {
 		return modules_.count(id) != 0;
@@ -1240,57 +1332,118 @@ struct RTLIL::Design
 	void check();
 	void optimize();
 
+	// checks if the given module is included in the current selection
 	bool selected_module(const RTLIL::IdString &mod_name) const;
+
+	// checks if the given module is wholly included in the current
+	// selection, i.e. not partially selected
 	bool selected_whole_module(const RTLIL::IdString &mod_name) const;
+
+	// checks if the given member from the given module is included in the
+	// current selection
 	bool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;
 
+	// checks if the given module is included in the current selection
 	bool selected_module(RTLIL::Module *mod) const;
+
+	// checks if the given module is wholly included in the current
+	// selection, i.e. not partially selected
 	bool selected_whole_module(RTLIL::Module *mod) const;
 
+	// push the given selection to the selection stack
+	void push_selection(RTLIL::Selection sel);
+	// push a new selection to the selection stack, with nothing selected
+	void push_empty_selection();
+	// push a new selection to the selection stack, with all non-boxed
+	// modules selected
+	void push_full_selection();
+	// push a new selection to the selection stack, with all modules
+	// selected including boxes
+	void push_complete_selection();
+	// pop the current selection from the stack, returning to a full
+	// selection (no boxes) if the stack is empty
+	void pop_selection();
+
+	// get the current selection
 	RTLIL::Selection &selection() {
 		return selection_stack.back();
 	}
 
+	// get the current selection
 	const RTLIL::Selection &selection() const {
 		return selection_stack.back();
 	}
 
+	// is the current selection a full selection (no boxes)
 	bool full_selection() const {
-		return selection_stack.back().full_selection;
+		return selection().full_selection;
 	}
 
+	// is the given module in the current selection
 	template<typename T1> bool selected(T1 *module) const {
 		return selected_module(module->name);
 	}
 
+	// is the given member of the given module in the current selection
 	template<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {
 		return selected_member(module->name, member->name);
 	}
 
+	// add whole module to the current selection
 	template<typename T1> void select(T1 *module) {
-		if (selection_stack.size() > 0) {
-			RTLIL::Selection &sel = selection_stack.back();
-			sel.select(module);
-		}
+		RTLIL::Selection &sel = selection();
+		sel.select(module);
 	}
 
+	// add member of module to the current selection
 	template<typename T1, typename T2> void select(T1 *module, T2 *member) {
-		if (selection_stack.size() > 0) {
-			RTLIL::Selection &sel = selection_stack.back();
-			sel.select(module, member);
-		}
-	}
-
-
-	std::vector<RTLIL::Module*> selected_modules() const;
-	std::vector<RTLIL::Module*> selected_whole_modules() const;
-	std::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;
+		RTLIL::Selection &sel = selection();
+		sel.select(module, member);
+	}
+
+
+	// returns all selected modules
+	std::vector<RTLIL::Module*> selected_modules(
+		// controls if partially selected modules are included
+		RTLIL::SelectPartials partials = SELECT_ALL,
+		// controls if boxed modules are included
+		RTLIL::SelectBoxes boxes = SB_UNBOXED_WARN
+	) const;
+
+	// returns all selected modules, and may include boxes
+	std::vector<RTLIL::Module*> all_selected_modules() const { return selected_modules(SELECT_ALL, SB_ALL); }
+	// returns all selected unboxed modules, silently ignoring any boxed
+	// modules in the selection
+	std::vector<RTLIL::Module*> selected_unboxed_modules() const { return selected_modules(SELECT_ALL, SB_UNBOXED_ONLY); }
+	// returns all selected unboxed modules, warning the user if any boxed
+	// modules have been ignored
+	std::vector<RTLIL::Module*> selected_unboxed_modules_warn() const { return selected_modules(SELECT_ALL, SB_UNBOXED_WARN); }
+
+	[[deprecated("Use select_unboxed_whole_modules() to maintain prior behaviour, or consider one of the other selected whole module helpers.")]]
+	std::vector<RTLIL::Module*> selected_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_UNBOXED_WARN); }
+	// returns all selected whole modules, silently ignoring partially
+	// selected modules, and may include boxes
+	std::vector<RTLIL::Module*> all_selected_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_ALL); }
+	// returns all selected whole modules, warning the user if any partially
+	// selected or boxed modules have been ignored; optionally includes
+	// selected whole modules with the 'whitebox' attribute
+	std::vector<RTLIL::Module*> selected_whole_modules_warn(
+		// should whole modules with the 'whitebox' attribute be
+		// included
+		bool include_wb = false
+	) const { return selected_modules(SELECT_WHOLE_WARN, include_wb ? SB_EXCL_BB_WARN : SB_UNBOXED_WARN); }
+	// returns all selected unboxed whole modules, silently ignoring
+	// partially selected or boxed modules
+	std::vector<RTLIL::Module*> selected_unboxed_whole_modules() const { return selected_modules(SELECT_WHOLE_ONLY, SB_UNBOXED_ONLY); }
+	// returns all selected unboxed whole modules, warning the user if any
+	// partially selected or boxed modules have been ignored
+	std::vector<RTLIL::Module*> selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); }
 #ifdef WITH_PYTHON
 	static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
 #endif
 };
 
-struct RTLIL::Module : public RTLIL::AttrObject
+struct RTLIL::Module : public RTLIL::NamedObject
 {
 	Hasher::hash_t hashidx_;
 	[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
@@ -1313,7 +1466,6 @@ public:
 	std::vector<RTLIL::SigSig>   connections_;
 	std::vector<RTLIL::Binding*> bindings_;
 
-	RTLIL::IdString name;
 	idict<RTLIL::IdString> avail_parameters;
 	dict<RTLIL::IdString, RTLIL::Const> parameter_default_values;
 	dict<RTLIL::IdString, RTLIL::Memory*> memories;
@@ -1358,8 +1510,14 @@ public:
 	bool has_memories_warn() const;
 	bool has_processes_warn() const;
 
+	bool is_selected() const;
+	bool is_selected_whole() const;
+
 	std::vector<RTLIL::Wire*> selected_wires() const;
 	std::vector<RTLIL::Cell*> selected_cells() const;
+	std::vector<RTLIL::Memory*> selected_memories() const;
+	std::vector<RTLIL::Process*> selected_processes() const;
+	std::vector<RTLIL::NamedObject*> selected_members() const;
 
 	template<typename T> bool selected(T *member) const {
 		return design->selected_member(name, member->name);
@@ -1645,7 +1803,7 @@ namespace RTLIL_BACKEND {
 void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);
 }
 
-struct RTLIL::Wire : public RTLIL::AttrObject
+struct RTLIL::Wire : public RTLIL::NamedObject
 {
 	Hasher::hash_t hashidx_;
 	[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
@@ -1668,7 +1826,6 @@ public:
 	void operator=(RTLIL::Wire &other) = delete;
 
 	RTLIL::Module *module;
-	RTLIL::IdString name;
 	int width, start_offset, port_id;
 	bool port_input, port_output, upto, is_signed;
 
@@ -1697,14 +1854,13 @@ inline int GetSize(RTLIL::Wire *wire) {
 	return wire->width;
 }
 
-struct RTLIL::Memory : public RTLIL::AttrObject
+struct RTLIL::Memory : public RTLIL::NamedObject
 {
 	Hasher::hash_t hashidx_;
 	[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
 
 	Memory();
 
-	RTLIL::IdString name;
 	int width, start_offset, size;
 #ifdef WITH_PYTHON
 	~Memory();
@@ -1712,7 +1868,7 @@ struct RTLIL::Memory : public RTLIL::AttrObject
 #endif
 };
 
-struct RTLIL::Cell : public RTLIL::AttrObject
+struct RTLIL::Cell : public RTLIL::NamedObject
 {
 	Hasher::hash_t hashidx_;
 	[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
@@ -1729,7 +1885,6 @@ public:
 	void operator=(RTLIL::Cell &other) = delete;
 
 	RTLIL::Module *module;
-	RTLIL::IdString name;
 	RTLIL::IdString type;
 	dict<RTLIL::IdString, RTLIL::SigSpec> connections_;
 	dict<RTLIL::IdString, RTLIL::Const> parameters;
@@ -1822,7 +1977,7 @@ struct RTLIL::SyncRule
 	RTLIL::SyncRule *clone() const;
 };
 
-struct RTLIL::Process : public RTLIL::AttrObject
+struct RTLIL::Process : public RTLIL::NamedObject
 {
 	Hasher::hash_t hashidx_;
 	[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
@@ -1834,7 +1989,6 @@ protected:
 	~Process();
 
 public:
-	RTLIL::IdString name;
 	RTLIL::Module *module;
 	RTLIL::CaseRule root_case;
 	std::vector<RTLIL::SyncRule*> syncs;

{yowasp_yosys-0.52.0.0.post894.dist-info → yowasp_yosys-0.53.0.0.post912.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: yowasp-yosys
-Version: 0.52.0.0.post894
+Version: 0.53.0.0.post912
 Summary: Yosys Open SYnthesis Suite
 Author-email: Catherine <whitequark@whitequark.org>
 License-Expression: ISC

{yowasp_yosys-0.52.0.0.post894.dist-info → yowasp_yosys-0.53.0.0.post912.dist-info}/RECORD

@@ -2,7 +2,7 @@ yowasp_yosys/__init__.py,sha256=x--xPTzLWZNoX6H0B2E3a1HMZMk3di10gVnWVLJ92xc,1325
 yowasp_yosys/sby.py,sha256=at4UB7rmju4xhmFP6b31T7duU2Hx5aSOgGUiExKz7Xc,18496
 yowasp_yosys/smtbmc.py,sha256=yiI93tHys5c8aXfCdk2dNtw2mwukRXqeT8YGx5Th8eg,74231
 yowasp_yosys/witness.py,sha256=m3iV2Nydm0p4G79VRaaX3lGul-nGnuxeKnx20MCJgi0,17279
-yowasp_yosys/yosys.wasm,sha256=WshLXNhe1EXwyh9Qm2KETtZ2W-9IkeUU0w-baj9hSd0,29776869
+yowasp_yosys/yosys.wasm,sha256=kJpC9cgE7pspygVw_FWEGdtV301egX_bAtvYCMvaL60,30800114
 yowasp_yosys/share/abc9_map.v,sha256=uWDqMpBQTeeadH1BlHVwkCy2StKF892xbgBgMKLK5-w,923
 yowasp_yosys/share/abc9_model.v,sha256=IfMyEGOEUBdZyiVule0wMhrVYVYQpmSIcxygbgtHItI,653
 yowasp_yosys/share/abc9_unmap.v,sha256=w107Y3iJjMU6D_6_aYLf2NziXTnAhpa5_CFAwaYO1iU,638
@@ -44,7 +44,7 @@ yowasp_yosys/share/ecp5/cells_bb.v,sha256=rQ3De-Xkavq7qNaZFXCLU2kZUnofaTmftu1ssv
 yowasp_yosys/share/ecp5/cells_ff.vh,sha256=nTxJ16Rw2HqIiP_vUxIzT1pLlWfXG_-zN4L4ilnClvQ,6129
 yowasp_yosys/share/ecp5/cells_io.vh,sha256=u8e7FAbtDSSaxYjxIWw8OWTrmKgCgWpKIbFHA9ja5is,2055
 yowasp_yosys/share/ecp5/cells_map.v,sha256=6mCMrabmQL9VWvuaUyjf3fI-AxN78eZ7qA0ZXBE9ISY,15010
-yowasp_yosys/share/ecp5/cells_sim.v,sha256=I8HR01tb2bpaB-F899XAf-e2hA4d62wvdGw_QwtM7FQ,22821
+yowasp_yosys/share/ecp5/cells_sim.v,sha256=KeVWFCjbqYl3i9Gve-D2NqtP63RAB4PzxmmZTgVf61o,22819
 yowasp_yosys/share/ecp5/dsp_map.v,sha256=qgXI6m78V91RzfapTSr2_HZ186kzJexcroq8Xtl_K0Q,1436
 yowasp_yosys/share/ecp5/latches_map.v,sha256=V5NwBaIML68eOlhDaUJUs8W-ggRePjPsDtUn3mnSpao,258
 yowasp_yosys/share/ecp5/lutrams.txt,sha256=YLxriG1TI7e6PlRQgoexKdVa-9NKW4T_FaZSIrkncws,145
@@ -64,12 +64,12 @@ yowasp_yosys/share/fabulous/prims.v,sha256=Mf_IYhcgarrlvGG_mXMhxWe-b68wm9riS-Li_
 yowasp_yosys/share/fabulous/ram_regfile.txt,sha256=kegUh_BAs2bMOf0zhNpDMtBxQpRgG5T7mmE_WYUMau0,782
 yowasp_yosys/share/fabulous/regfile_map.v,sha256=Jm0FgJlFFkQUzNgr8BEvRE7yucj0VCO-C_KT48kwV3Q,1431
 yowasp_yosys/share/gatemate/arith_map.v,sha256=U8Lz8wj0WpUh9YP89MVQfkgYcw4xYE0XWEmt-owc_D4,2016
-yowasp_yosys/share/gatemate/brams.txt,sha256=lFwxrzoTQOKnCqO9BWQNa-ymzMBZSf7LxyKbirjxYOQ,1230
+yowasp_yosys/share/gatemate/brams.txt,sha256=mtysGrMGltlSw98eOHSSrN38xzQmkxVbfgTivQrZ5qk,1210
 yowasp_yosys/share/gatemate/brams_init_20.vh,sha256=PKYSRZOL_i6Fmjy1dB-lF0eSlV8BFLjGvDqrw6zhLpw,4480
 yowasp_yosys/share/gatemate/brams_init_40.vh,sha256=yK50gQK1Kc59RxbbV9xjeWohhInkyZ3g6N5WmtpqMug,17970
 yowasp_yosys/share/gatemate/brams_map.v,sha256=dUtJmsUqxezzJfuFeJq8xxCC_MeVlECYagxsXhGEJHA,29326
 yowasp_yosys/share/gatemate/cells_bb.v,sha256=cc9cOL12VXqvKf6JV4r3XD2dSx4O_2Q8L0yWMlTog3A,11964
-yowasp_yosys/share/gatemate/cells_sim.v,sha256=AiHGI4g7VySeRZS9bkG98kosYwrCOnVcnJT_fRHC1Oo,65939
+yowasp_yosys/share/gatemate/cells_sim.v,sha256=WRAD7MrD6K_aNQE8AM4yCldphCksCImFKnguMLj9bd4,65936
 yowasp_yosys/share/gatemate/inv_map.v,sha256=UpmZftbrZGv7K8od1rjId099dTuqQyaP7z4z-V3hQgI,180
 yowasp_yosys/share/gatemate/lut_map.v,sha256=MM36LUh40S7VWKgUa_IUWo9v65B6WJPeB56-on7AT9M,1558
 yowasp_yosys/share/gatemate/lut_tree_cells.genlib,sha256=8ECZaGTnN1WRgXzL8jOB85e3aUwQReXcYu5gC7Eb56s,6422
@@ -92,7 +92,7 @@ yowasp_yosys/share/greenpak4/cells_latch.v,sha256=ianZm8mhYPXOcoqcGBTNnQD56GGBog
 yowasp_yosys/share/greenpak4/cells_map.v,sha256=nz85PESvWrZygvyqISTdbsdrYM4Wl7TTzd02rH3cW9k,5298
 yowasp_yosys/share/greenpak4/cells_sim.v,sha256=Sznl1YhW-E2jZq6bvXhtRhTQtEPsDFduPoreyiK8Nwo,105
 yowasp_yosys/share/greenpak4/cells_sim_ams.v,sha256=6nbD4dyGcJh2lroK7BEyekylTTRB42t5OgEmiiIYU1M,2072
-yowasp_yosys/share/greenpak4/cells_sim_digital.v,sha256=XoDYL72Qub_5P0-qYMwn8h-_MuRfUA0OokdGfcq8bXM,15006
+yowasp_yosys/share/greenpak4/cells_sim_digital.v,sha256=M5_f75yaBgZfwnNEh4vTkdoLgQJE1twWu4ChBBo3TFU,14975
 yowasp_yosys/share/greenpak4/cells_sim_wip.v,sha256=FzUNfMpVzkdPTqkGTS-eIfmkCRBwh5SrCmS0Ega_PH4,2926
 yowasp_yosys/share/greenpak4/gp_dff.lib,sha256=aNe7O8sZhBgxwraXXHVMOqqFxUAHEgn7EPaO3qlvLrY,998
 yowasp_yosys/share/ice40/abc9_model.v,sha256=yb7NHMspXMuKefcIEnOb9LzQv4Rvd_IsJifqgCoxI7o,3612
@@ -106,7 +106,7 @@ yowasp_yosys/share/ice40/ff_map.v,sha256=0ikq-i1_UVT6xuFLMj2Zfilwu6wz8oibMdtPegZ
 yowasp_yosys/share/ice40/latches_map.v,sha256=V5NwBaIML68eOlhDaUJUs8W-ggRePjPsDtUn3mnSpao,258
 yowasp_yosys/share/ice40/spram.txt,sha256=dCRV0flfJunvnvKV0Q5Kq5NBrhh_PkZGXvUt675aiIk,153
 yowasp_yosys/share/ice40/spram_map.v,sha256=O8fRkVuH1dgAXEAtYJgh8wTHnZEK75fPAMBI-PgYVqs,475
-yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h,sha256=5iaAR8JOyCQVFb-kt1S7OC09X0-LRi0iXMBpCrXwApM,72317
+yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h,sha256=MN2K_SZTGGeq0yQjcR2rd6XQvEL8ewc7GDymzZUg7zY,72493
 yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h,sha256=3bFAy3nYtaH4MsLI9Kvf88K6BYOkML8plDMxmPtPdss,30008
 yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h,sha256=6zIxuXG7bXy5UWe7WuA_KQHiwV7VWvcsNecwOPAL_bU,6174
 yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h,sha256=L4VOOx7c9rGkxTFi8VjhhNGEbuzxf_j6P5D0_0n0WjA,8637
@@ -123,7 +123,7 @@ yowasp_yosys/share/include/kernel/bitpattern.h,sha256=V_gds0rvxcrRMTFhIm8Zv4PRFo
 yowasp_yosys/share/include/kernel/cellaigs.h,sha256=CdYos67IpmAgLvBbJ8EC3hWg6WhBIBy9jmhdoZ36HVE,1391
 yowasp_yosys/share/include/kernel/celledges.h,sha256=fF_sHJOpN_qQ1P0x8KKoJE9ulDMusfjkF0dBpTMs19E,2216
 yowasp_yosys/share/include/kernel/celltypes.h,sha256=W44T0u789-fy_tj7fGRTNI7s1jshewrPwmS3_-Oz6-A,18561
-yowasp_yosys/share/include/kernel/consteval.h,sha256=kLEB95uiFL5Gm4u1tjnYK3a0uYkraEJ3wF8x_1RXqcM,10864
+yowasp_yosys/share/include/kernel/consteval.h,sha256=oEPSKbbgqvNmlLqYFSozZX2cjFQA5IM-d69HmyuZiGo,10864
 yowasp_yosys/share/include/kernel/constids.inc,sha256=s4Qb8C2nWUhIXU8txrBzWQia3u2OJ_E6ehifcpPBkYI,3694
 yowasp_yosys/share/include/kernel/cost.h,sha256=TRW3KGPVLv5MxAmNbSh1mnzwTc-QHvZXSh9Wfc6mw3U,2921
 yowasp_yosys/share/include/kernel/drivertools.h,sha256=jHGOmnyVCjfvUvoBfQvD9O-Tu6pfs4WVbPbQZv1Mhd4,33537
@@ -136,12 +136,12 @@ yowasp_yosys/share/include/kernel/hashlib.h,sha256=3skguI0eCyzEfFoWmsxnjKzWd8pQV
 yowasp_yosys/share/include/kernel/io.h,sha256=qfiLTmDMVPV0BuDgIH5BARxW0FhnB1h7BfUQPw_2SVE,1281
 yowasp_yosys/share/include/kernel/json.h,sha256=tE3AgUslbZd5TRFEipj0HptYjWgNfMjzV44l3A5zAu8,2851
 yowasp_yosys/share/include/kernel/log.h,sha256=NZNJPBf-F_sISwfmJ_GQPm1Z9UzUCYQD6jHiWnsVorY,15380
-yowasp_yosys/share/include/kernel/macc.h,sha256=J-HklyfsHuqyDEFf9GXAExfqo69Ed_zdukcoaC2q1wI,8926
+yowasp_yosys/share/include/kernel/macc.h,sha256=LHm507daCT57lGCNNwia1LJVk3pkBB5ZteCZihxD5Qw,8926
 yowasp_yosys/share/include/kernel/mem.h,sha256=xKz0HxXap_PTdzpK-NUcbxybF3YisRc2JoCv17TXOc4,15505
 yowasp_yosys/share/include/kernel/modtools.h,sha256=mRnzc5TIsdIbHlFSTk2Yc0y85ttknhK-dAlti3neSI8,14388
 yowasp_yosys/share/include/kernel/qcsat.h,sha256=ibhpJRu0youjDXPllXrDJi851VpwW1kbJ_y94_X6JhU,2804
 yowasp_yosys/share/include/kernel/register.h,sha256=2xAbUndqoXwACqtqowqmfmRQQFlwEpV82wy2ejSGwUY,5482
-yowasp_yosys/share/include/kernel/rtlil.h,sha256=ABTCNiocrQzN3y7MuNy6dWclHc2cd8TCuPzxi-A12AY,90354
+yowasp_yosys/share/include/kernel/rtlil.h,sha256=Ycfn-zWd66LZ6Kzcb0rtFiU7jBiO_CnLxPi93pKfwdE,97702
 yowasp_yosys/share/include/kernel/satgen.h,sha256=zx8LptIgds0Z9sxXx6HGxNNYuk05dHqQZy1aXFWEXC0,10483
 yowasp_yosys/share/include/kernel/scopeinfo.h,sha256=EAU3vSTIwH1RrbSC7HVoTWh4SLfHMSIoidQPvT1Mo7g,11797
 yowasp_yosys/share/include/kernel/sexpr.h,sha256=CUDKFehVoGmakYBYLpEKUtlM0Dd3oI6TNW_cKz-qe0g,4720
@@ -335,8 +335,8 @@ yowasp_yosys/share/xilinx/xc5v_dsp_map.v,sha256=I4lg0RQ54fBBba_7NNvUgwS4tQ1yLIsU
 yowasp_yosys/share/xilinx/xc6s_dsp_map.v,sha256=gTxHocB-Dn5G4BplWgri_tLhT6DIO2S0X-yu4iBKYyk,562
 yowasp_yosys/share/xilinx/xc7_dsp_map.v,sha256=zrzreQi7mElrAMtrayxtiO_Bw00S6zsjSjSVcjmJPH0,884
 yowasp_yosys/share/xilinx/xcu_dsp_map.v,sha256=gzCgl1emrHGcigVmU0nP0pW7dlhQ01SaWwXzHHcqt-o,882
-yowasp_yosys-0.52.0.0.post894.dist-info/METADATA,sha256=6LPfljDvACTseZncoTpGrjylUYQsdmYpsJYDl09ygbM,2558
-yowasp_yosys-0.52.0.0.post894.dist-info/WHEEL,sha256=CmyFI0kx5cdEMTLiONQRbGQwjIoR1aIYB7eCAQ4KPJ0,91
-yowasp_yosys-0.52.0.0.post894.dist-info/entry_points.txt,sha256=p_9sIVi2ZqsqgYYo14PywYkwHYTa76fMEq3LxweXJpc,220
-yowasp_yosys-0.52.0.0.post894.dist-info/top_level.txt,sha256=_yiNT8kLYkcD1TEuUCzQ_MkON1c3xuIRV59zXds4zd4,13
-yowasp_yosys-0.52.0.0.post894.dist-info/RECORD,,
+yowasp_yosys-0.53.0.0.post912.dist-info/METADATA,sha256=onz8gMX7UBRxs5U4tHUGbFenBTL_o3vHKtXmzVhpNeE,2558
+yowasp_yosys-0.53.0.0.post912.dist-info/WHEEL,sha256=lTU6B6eIfYoiQJTZNc-fyaR6BpL6ehTzU3xGYxn2n8k,91
+yowasp_yosys-0.53.0.0.post912.dist-info/entry_points.txt,sha256=p_9sIVi2ZqsqgYYo14PywYkwHYTa76fMEq3LxweXJpc,220
+yowasp_yosys-0.53.0.0.post912.dist-info/top_level.txt,sha256=_yiNT8kLYkcD1TEuUCzQ_MkON1c3xuIRV59zXds4zd4,13
+yowasp_yosys-0.53.0.0.post912.dist-info/RECORD,,

{yowasp_yosys-0.52.0.0.post894.dist-info → yowasp_yosys-0.53.0.0.post912.dist-info}/WHEEL

@@ -1,5 +1,5 @@
 Wheel-Version: 1.0
-Generator: setuptools (78.1.0)
+Generator: setuptools (78.1.1)
 Root-Is-Purelib: true
 Tag: py3-none-any