yowasp-yosys 0.46.0.0.post790__py3-none-any.whl → 0.48.0.0.post834__py3-none-any.whl

yowasp_yosys/share/choices/han-carlson.v

@@ -0,0 +1,59 @@
+(* techmap_celltype = "$lcu" *)
+module _80_lcu_han_carlson (P, G, CI, CO);
+	parameter WIDTH = 2;
+
+	(* force_downto *)
+	input [WIDTH-1:0] P, G;
+	input CI;
+
+	(* force_downto *)
+	output [WIDTH-1:0] CO;
+
+	integer i, j;
+	(* force_downto *)
+	reg [WIDTH-1:0] p, g;
+
+	wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
+
+	always @* begin
+		i = 0;
+		p = P;
+		g = G;
+
+		// in almost all cases CI will be constant zero
+		g[0] = g[0] | (p[0] & CI);
+		if (i < $clog2(WIDTH)) begin
+
+			// First layer: BK
+			for (j = WIDTH - 1; j >= 0; j = j - 1) begin
+				if (j % 2 == 1) begin
+					g[j] = g[j] | p[j] & g[j - 1];
+					p[j] = p[j] & p[j - 1];
+				end
+			end
+
+			// Inner (log(WIDTH) - 1) layers: KS
+			for (i = 1; i < $clog2(WIDTH); i = i + 1) begin
+				for (j = WIDTH - 1; j >= 2**i; j = j - 1) begin
+					if (j % 2 == 1) begin
+						g[j] = g[j] | p[j] & g[j - 2**i];
+						p[j] = p[j] & p[j - 2**i];
+					end
+				end
+			end
+
+			// Last layer: BK
+			if (i < ($clog2(WIDTH) + 1)) begin
+				for (j = WIDTH - 1; j >= 0; j = j - 1) begin
+					if ((j % 2 == 0) && (j > 0)) begin
+						g[j] = g[j] | p[j] & g[j - 1];
+						p[j] = p[j] & p[j - 1];
+					end
+				end
+			end
+
+		end
+	end
+
+	assign CO = g;
+endmodule

yowasp_yosys/share/choices/sklansky.v

@@ -0,0 +1,37 @@
+(* techmap_celltype = "$lcu" *)
+module _80_lcu_sklansky (P, G, CI, CO);
+	parameter WIDTH = 2;
+
+	(* force_downto *)
+	input [WIDTH-1:0] P, G;
+	input CI;
+
+	(* force_downto *)
+	output [WIDTH-1:0] CO;
+
+	integer i, j;
+	(* force_downto *)
+	reg [WIDTH-1:0] p, g;
+
+	wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
+
+	always @* begin
+		p = P;
+		g = G;
+
+		// in almost all cases CI will be constant zero
+		g[0] = g[0] | (p[0] & CI);
+
+		for (i = 0; i < $clog2(WIDTH); i = i + 1) begin
+			// iterate in reverse so we don't confuse a result from this stage and the previous
+			for (j = WIDTH - 1; j >= 0; j = j - 1) begin
+				if (j & 2**i) begin
+					g[j] = g[j] | p[j] & g[(j & ~(2**i - 1)) - 1];
+					p[j] = p[j] & p[(j & ~(2**i - 1)) - 1];
+				end
+			end
+		end
+	end
+
+	assign CO = g;
+endmodule

yowasp_yosys/share/gowin/{cells_xtra.v → cells_xtra_gw1n.v}

@@ -1465,12 +1465,22 @@ output O, OB;
 input  I, IB, IL, MODESEL;
 endmodule
 
+module ELVDS_IBUF_MIPI (...);
+output OH, OL;
+input  I, IB;
+endmodule
+
 module I3C_IOBUF (...);
 output O;
 inout IO;
 input  I, MODESEL;
 endmodule
 
+module TLVDS_OEN_BK (...);
+input OEN;
+parameter OEN_BANK = "0"; 
+endmodule
+
 module CLKDIV (...);
 input HCLKIN;
 input RESETN;
@@ -1570,117 +1580,6 @@ input CE;
 output CLKOUT;
 endmodule
 
-module FLASH128K (...);
-input [31:0] DIN;
-input [14:0] ADDR;
-input CS,AE,OE;
-input PCLK;
-input PROG, SERA, MASE;
-input NVSTR;
-input IFREN;
-input RESETN;
-output [31:0] DOUT;
-output TBIT;
-parameter IDLE  = 4'd0,
-          READ_S1 = 4'd1,
-          READ_S2 = 4'd2,
-          PROG_S1 = 4'd3,
-          PROG_S2 = 4'd4,
-          PROG_S3 = 4'd5,
-          PROG_S4 = 4'd6,
-          SERA_S1 = 4'd7,
-          SERA_S2 = 4'd8,
-          SERA_S3 = 4'd9,
-          SERA_S4 = 4'd10,
-          MASE_S1 = 4'd11,
-          MASE_S2 = 4'd12,
-          MASE_S3 = 4'd13,
-          MASE_S4 = 4'd14;
-endmodule
-
-module MCU (...);
-endmodule
-
-module USB20_PHY (...);
-parameter DATABUS16_8 = 1'b0;
-parameter ADP_PRBEN = 1'b0;
-parameter TEST_MODE = 5'b00000;
-parameter HSDRV1 = 1'b0; 
-parameter HSDRV0 = 1'b0; 
-parameter CLK_SEL = 1'b0;
-parameter M = 4'b0000; 
-parameter N = 6'b101000; 
-parameter C = 2'b01; 
-parameter FOC_LOCK = 1'b0;
-input   [15:0]  DATAIN;
-input   TXVLD;
-input   TXVLDH;
-input   RESET;
-input   SUSPENDM;
-input   [1:0]   XCVRSEL;
-input   TERMSEL;
-input   [1:0]   OPMODE;
-output  [15:0]  DATAOUT;
-output  TXREADY;
-output  RXACTIVE;
-output  RXVLD;
-output  RXVLDH;
-output  CLK;      
-output  RXERROR;
-inout   DP;
-inout   DM;
-output  [1:0]   LINESTATE;
-input   IDPULLUP;
-input   DPPD;
-input   DMPD;
-input   CHARGVBUS;
-input   DISCHARGVBUS;
-input   TXBITSTUFFEN;
-input   TXBITSTUFFENH;
-input   TXENN;
-input   TXDAT;
-input   TXSE0;
-input   FSLSSERIAL;
-output  HOSTDIS;
-output  IDDIG;
-output  ADPPRB;
-output  ADPSNS;
-output  SESSVLD;
-output  VBUSVLD;
-output  RXDP;
-output  RXDM;
-output  RXRCV;
-output  LBKERR;
-output  CLKRDY;
-input   INTCLK;
-inout   ID;
-inout   VBUS;
-inout   REXT;
-input   XIN;
-inout   XOUT;
-input	TEST;
-output	CLK480PAD;
-input        SCANCLK; 
-input        SCANEN; 
-input        SCANMODE; 
-input        TRESETN; 
-input        SCANIN1; 
-output       SCANOUT1; 
-input        SCANIN2; 
-output       SCANOUT2; 
-input        SCANIN3; 
-output       SCANOUT3; 
-input        SCANIN4; 
-output       SCANOUT4; 
-input        SCANIN5; 
-output       SCANOUT5; 
-input        SCANIN6; 
-output       SCANOUT6; 
-endmodule
-
-module ADC (...);
-endmodule
-
 module CLKDIV2 (...);
 parameter GSREN = "false"; 
 input HCLKIN, RESETN;
@@ -1977,7 +1876,7 @@ parameter MIPI_LANE1_EN = 1'b0;
 parameter MIPI_LANE2_EN = 1'b0;
 parameter MIPI_LANE3_EN = 1'b0;
 parameter MIPI_CK_EN = 1'b1;
-parameter SYNC_CLK_SEL = 1'b1;
+parameter SYNC_CLK_SEL = 1'b0;
 endmodule
 
 module CLKDIVG (...);
@@ -1988,3 +1887,7 @@ output CLKOUT;
 parameter DIV_MODE = "2"; 
 parameter GSREN = "false"; 
 endmodule
+
+module PWRGRD (...);
+input PDEN; 
+endmodule