yowasp-yosys 0.46.0.0.post790__py3-none-any.whl → 0.47.0.0.post805__py3-none-any.whl

yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h

@@ -1127,7 +1127,7 @@ struct fmt_part {
 			}
 
 			case UNICHAR: {
-				uint32_t codepoint = val.template get<uint32_t>();
+				uint32_t codepoint = val.template zcast<32>().template get<uint32_t>();
 				if (codepoint >= 0x10000)
 					buf += (char)(0xf0 |  (codepoint >> 18));
 				else if (codepoint >= 0x800)

yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h

@@ -50,9 +50,13 @@ class vcd_writer {
 
 	void emit_scope(const std::vector<std::string> &scope) {
 		assert(!streaming);
-		while (current_scope.size() > scope.size() ||
-		       (current_scope.size() > 0 &&
-			current_scope[current_scope.size() - 1] != scope[current_scope.size() - 1])) {
+		size_t same_scope_count = 0;
+		while ((same_scope_count < current_scope.size()) &&
+			   (same_scope_count < scope.size()) &&
+			   (current_scope[same_scope_count] == scope[same_scope_count])) {
+			same_scope_count++;
+		}
+		while (current_scope.size() > same_scope_count) {
 			buffer += "$upscope $end\n";
 			current_scope.pop_back();
 		}
@@ -123,6 +127,8 @@ class vcd_writer {
 			bool bit_curr = var.curr[bit / (8 * sizeof(chunk_t))] & (1 << (bit % (8 * sizeof(chunk_t))));
 			buffer += (bit_curr ? '1' : '0');
 		}
+		if (var.width == 0)
+			buffer += '0';
 		buffer += ' ';
 		emit_ident(var.ident);
 		buffer += '\n';

yowasp_yosys/share/include/kernel/bitpattern.h

@@ -80,7 +80,7 @@ struct BitPatternPool
 	bits_t sig2bits(RTLIL::SigSpec sig)
 	{
 		bits_t bits;
-		bits.bitdata = sig.as_const().bits;
+		bits.bitdata = sig.as_const().bits();
 		for (auto &b : bits.bitdata)
 			if (b > RTLIL::State::S1)
 				b = RTLIL::State::Sa;

yowasp_yosys/share/include/kernel/celltypes.h

@@ -29,6 +29,8 @@ struct CellType
 	RTLIL::IdString type;
 	pool<RTLIL::IdString> inputs, outputs;
 	bool is_evaluable;
+	bool is_combinatorial;
+	bool is_synthesizable;
 };
 
 struct CellTypes
@@ -56,9 +58,9 @@ struct CellTypes
 		setup_stdcells_mem();
 	}
 
-	void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false)
+	void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false)
 	{
-		CellType ct = {type, inputs, outputs, is_evaluable};
+		CellType ct = {type, inputs, outputs, is_evaluable, is_combinatorial, is_synthesizable};
 		cell_types[ct.type] = ct;
 	}
 
@@ -325,7 +327,7 @@ struct CellTypes
 
 	static RTLIL::Const eval_not(RTLIL::Const v)
 	{
-		for (auto &bit : v.bits)
+		for (auto &bit : v.bits())
 			if (bit == State::S0) bit = State::S1;
 			else if (bit == State::S1) bit = State::S0;
 		return v;
@@ -419,13 +421,13 @@ struct CellTypes
 			RTLIL::Const ret;
 			int width = cell->parameters.at(ID::Y_WIDTH).as_int();
 			int offset = cell->parameters.at(ID::OFFSET).as_int();
-			ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);
+			ret.bits().insert(ret.bits().end(), arg1.begin()+offset, arg1.begin()+offset+width);
 			return ret;
 		}
 
 		if (cell->type == ID($concat)) {
 			RTLIL::Const ret = arg1;
-			ret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end());
+			ret.bits().insert(ret.bits().end(), arg2.begin(), arg2.end());
 			return ret;
 		}
 
@@ -448,7 +450,7 @@ struct CellTypes
 		{
 			int width = cell->parameters.at(ID::WIDTH).as_int();
 
-			std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits;
+			std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).to_bits();
 			while (GetSize(t) < (1 << width))
 				t.push_back(State::S0);
 			t.resize(1 << width);
@@ -460,7 +462,7 @@ struct CellTypes
 		{
 			int width = cell->parameters.at(ID::WIDTH).as_int();
 			int depth = cell->parameters.at(ID::DEPTH).as_int();
-			std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits;
+			std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).to_bits();
 
 			while (GetSize(t) < width*depth*2)
 				t.push_back(State::S0);
@@ -473,7 +475,7 @@ struct CellTypes
 				bool match_x = true;
 
 				for (int j = 0; j < width; j++) {
-					RTLIL::State a = arg1.bits.at(j);
+					RTLIL::State a = arg1.at(j);
 					if (t.at(2*width*i + 2*j + 0) == State::S1) {
 						if (a == State::S1) match_x = false;
 						if (a != State::S0) match = false;
@@ -513,7 +515,7 @@ struct CellTypes
 		if (cell->type == ID($_OAI3_))
 			return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));
 
-		log_assert(arg3.bits.size() == 0);
+		log_assert(arg3.size() == 0);
 		return eval(cell, arg1, arg2, errp);
 	}
 
@@ -524,7 +526,7 @@ struct CellTypes
 		if (cell->type == ID($_OAI4_))
 			return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));
 
-		log_assert(arg4.bits.size() == 0);
+		log_assert(arg4.size() == 0);
 		return eval(cell, arg1, arg2, arg3, errp);
 	}
 };

yowasp_yosys/share/include/kernel/consteval.h

@@ -76,7 +76,7 @@ struct ConstEval
 #ifndef NDEBUG
 		RTLIL::SigSpec current_val = values_map(sig);
 		for (int i = 0; i < GetSize(current_val); i++)
-			log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);
+			log_assert(current_val[i].wire != NULL || current_val[i] == value[i]);
 #endif
 		values_map.add(sig, RTLIL::SigSpec(value));
 	}
@@ -115,7 +115,7 @@ struct ConstEval
 
 				for (int i = 0; i < GetSize(coval); i++) {
 					carry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry);
-					coval.bits[i] = carry ? State::S1 : State::S0;
+					coval.bits()[i] = carry ? State::S1 : State::S0;
 				}
 
 				set(sig_co, coval);
@@ -153,7 +153,7 @@ struct ConstEval
 
 			for (int i = 0; i < sig_s.size(); i++)
 			{
-				RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0);
+				RTLIL::State s_bit = sig_s.extract(i, 1).as_const().at(0);
 				RTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size());
 
 				if (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)
@@ -180,10 +180,10 @@ struct ConstEval
 
 			if (y_values.size() > 1)
 			{
-				std::vector<RTLIL::State> master_bits = y_values.at(0).bits;
+				std::vector<RTLIL::State> master_bits = y_values.at(0).to_bits();
 
 				for (size_t i = 1; i < y_values.size(); i++) {
-					std::vector<RTLIL::State> &slave_bits = y_values.at(i).bits;
+					std::vector<RTLIL::State> slave_bits = y_values.at(i).to_bits();
 					log_assert(master_bits.size() == slave_bits.size());
 					for (size_t j = 0; j < master_bits.size(); j++)
 						if (master_bits[j] != slave_bits[j])
@@ -248,8 +248,8 @@ struct ConstEval
 			RTLIL::Const val_x = const_or(t2, t3, false, false, width);
 
 			for (int i = 0; i < GetSize(val_y); i++)
-				if (val_y.bits[i] == RTLIL::Sx)
-					val_x.bits[i] = RTLIL::Sx;
+				if (val_y[i] == RTLIL::Sx)
+					val_x.bits()[i] = RTLIL::Sx;
 
 			set(sig_y, val_y);
 			set(sig_x, val_x);

yowasp_yosys/share/include/kernel/constids.inc

@@ -154,7 +154,6 @@ X(PORTID)
 X(PRIORITY)
 X(PRIORITY_MASK)
 X(Q)
-X(qwp_position)
 X(R)
 X(ram_block)
 X(ram_style)

yowasp_yosys/share/include/kernel/ffinit.h

@@ -76,7 +76,7 @@ struct FfInitVals
 	{
 		RTLIL::Const res;
 		for (auto bit : sig)
-			res.bits.push_back((*this)(bit));
+			res.bits().push_back((*this)(bit));
 		return res;
 	}
 
@@ -93,12 +93,12 @@ struct FfInitVals
 		initbits[mbit] = std::make_pair(val,abit);
 		auto it2 = abit.wire->attributes.find(ID::init);
 		if (it2 != abit.wire->attributes.end()) {
-			it2->second[abit.offset] = val;
+			it2->second.bits()[abit.offset] = val;
 			if (it2->second.is_fully_undef())
 				abit.wire->attributes.erase(it2);
 		} else if (val != State::Sx) {
 			Const cval(State::Sx, GetSize(abit.wire));
-			cval[abit.offset] = val;
+			cval.bits()[abit.offset] = val;
 			abit.wire->attributes[ID::init] = cval;
 		}
 	}

yowasp_yosys/share/include/kernel/macc.h

@@ -104,7 +104,7 @@ struct Macc
 		ports.clear();
 		bit_ports = cell->getPort(ID::B);
 
-		std::vector<RTLIL::State> config_bits = cell->getParam(ID::CONFIG).bits;
+		auto config_bits = cell->getParam(ID::CONFIG);
 		int config_cursor = 0;
 
 		int config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();
@@ -199,7 +199,7 @@ struct Macc
 
 	bool eval(RTLIL::Const &result) const
 	{
-		for (auto &bit : result.bits)
+		for (auto &bit : result.bits())
 			bit = State::S0;
 
 		for (auto &port : ports)

yowasp_yosys/share/include/kernel/mem.h

@@ -255,7 +255,7 @@ private:
 	// return the offset the addr would have in the range at `it`
 	size_t _range_offset(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) const { return (addr - it->first) * _data_width; }
 	// assuming _range_contains(it, addr), return an iterator pointing to the data at addr
-	std::vector<State>::iterator _range_data(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) { return it->second.bits.begin() + _range_offset(it, addr); }
+	std::vector<State>::iterator _range_data(std::map<addr_t, RTLIL::Const>::iterator it, addr_t addr) { return it->second.bits().begin() + _range_offset(it, addr); }
 	// internal version of reserve_range that returns an iterator to the range
 	std::map<addr_t, RTLIL::Const>::iterator _reserve_range(addr_t begin_addr, addr_t end_addr);
 	// write a single word at addr, return iterator to next word

yowasp_yosys/share/include/kernel/rtlil.h

@@ -47,6 +47,8 @@ namespace RTLIL
 		STi = 7  // init
 	};
 
+	// Semantic metadata - how can this constant be interpreted?
+	// Values may be generally non-exclusive
 	enum ConstFlags : unsigned char {
 		CONST_FLAG_NONE   = 0,
 		CONST_FLAG_STRING = 1,
@@ -658,35 +660,115 @@ namespace RTLIL
 
 struct RTLIL::Const
 {
-	int flags;
-	std::vector<RTLIL::State> bits;
+	short int flags;
+private:
+	friend class KernelRtlilTest;
+	FRIEND_TEST(KernelRtlilTest, ConstStr);
+	using bitvectype = std::vector<RTLIL::State>;
+	enum class backing_tag: bool { bits, string };
+	// Do not access the union or tag even in Const methods unless necessary
+	mutable backing_tag tag;
+	union {
+		mutable bitvectype bits_;
+		mutable std::string str_;
+	};
+
+	// Use these private utilities instead
+	bool is_bits() const { return tag == backing_tag::bits; }
+	bool is_str() const { return tag == backing_tag::string; }
+
+	bitvectype* get_if_bits() const { return is_bits() ? &bits_ : NULL; }
+	std::string* get_if_str() const { return is_str() ? &str_ : NULL; }
 
-	Const() : flags(RTLIL::CONST_FLAG_NONE) {}
+	bitvectype& get_bits() const;
+	std::string& get_str() const;
+public:
+	Const() : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(std::vector<RTLIL::State>()) {}
 	Const(const std::string &str);
 	Const(long long val, int width = 32);
 	Const(RTLIL::State bit, int width = 1);
-	Const(const std::vector<RTLIL::State> &bits) : bits(bits) { flags = CONST_FLAG_NONE; }
+	Const(const std::vector<RTLIL::State> &bits) : flags(RTLIL::CONST_FLAG_NONE), tag(backing_tag::bits), bits_(bits) {}
 	Const(const std::vector<bool> &bits);
-	Const(const RTLIL::Const &c) = default;
-	RTLIL::Const &operator =(const RTLIL::Const &other) = default;
+	Const(const RTLIL::Const &other);
+	Const(RTLIL::Const &&other);
+	RTLIL::Const &operator =(const RTLIL::Const &other);
+	~Const();
 
 	bool operator <(const RTLIL::Const &other) const;
 	bool operator ==(const RTLIL::Const &other) const;
 	bool operator !=(const RTLIL::Const &other) const;
 
+	std::vector<RTLIL::State>& bits();
 	bool as_bool() const;
 	int as_int(bool is_signed = false) const;
-	std::string as_string() const;
+	std::string as_string(const char* any = "-") const;
 	static Const from_string(const std::string &str);
+	std::vector<RTLIL::State> to_bits() const;
 
 	std::string decode_string() const;
+	int size() const;
+	bool empty() const;
+	void bitvectorize() const;
+
+	class const_iterator {
+	private:
+		const Const& parent;
+		size_t idx;
 
-	inline int size() const { return bits.size(); }
-	inline bool empty() const { return bits.empty(); }
-	inline RTLIL::State &operator[](int index) { return bits.at(index); }
-	inline const RTLIL::State &operator[](int index) const { return bits.at(index); }
-	inline decltype(bits)::iterator begin() { return bits.begin(); }
-	inline decltype(bits)::iterator end() { return bits.end(); }
+	public:
+		using iterator_category = std::input_iterator_tag;
+		using value_type = State;
+		using difference_type = std::ptrdiff_t;
+		using pointer = const State*;
+		using reference = const State&;
+
+		const_iterator(const Const& c, size_t i) : parent(c), idx(i) {}
+
+		State operator*() const;
+
+		const_iterator& operator++() { ++idx; return *this; }
+		const_iterator& operator--() { --idx; return *this; }
+		const_iterator& operator++(int) { ++idx; return *this; }
+		const_iterator& operator--(int) { --idx; return *this; }
+		const_iterator& operator+=(int i) { idx += i; return *this; }
+
+		const_iterator operator+(int add) {
+			return const_iterator(parent, idx + add);
+		}
+		const_iterator operator-(int sub) {
+			return const_iterator(parent, idx - sub);
+		}
+		int operator-(const const_iterator& other) {
+			return idx - other.idx;
+		}
+
+		bool operator==(const const_iterator& other) const {
+			return idx == other.idx;
+		}
+
+		bool operator!=(const const_iterator& other) const {
+			return !(*this == other);
+		}
+	};
+
+	const_iterator begin() const {
+		return const_iterator(*this, 0);
+	}
+	const_iterator end() const {
+		return const_iterator(*this, size());
+	}
+	State back() const {
+		return *(end() - 1);
+	}
+	State front() const {
+		return *begin();
+	}
+	State at(size_t i) const {
+		return *const_iterator(*this, i);
+	}
+	State operator[](size_t i) const {
+		return *const_iterator(*this, i);
+	}
 
 	bool is_fully_zero() const;
 	bool is_fully_ones() const;
@@ -695,25 +777,29 @@ struct RTLIL::Const
 	bool is_fully_undef_x_only() const;
 	bool is_onehot(int *pos = nullptr) const;
 
-	inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const {
-		RTLIL::Const ret;
-		ret.bits.reserve(len);
-		for (int i = offset; i < offset + len; i++)
-			ret.bits.push_back(i < GetSize(bits) ? bits[i] : padding);
-		return ret;
-	}
+	RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const;
+
+	// find the MSB without redundant leading bits
+	size_t get_min_size(bool is_signed) const;
+
+	// compress representation to the minimum required bits
+	void compress(bool is_signed = false);
+
+	std::optional<int> as_int_compress(bool is_signed) const;
 
 	void extu(int width) {
-		bits.resize(width, RTLIL::State::S0);
+		bits().resize(width, RTLIL::State::S0);
 	}
 
 	void exts(int width) {
-		bits.resize(width, bits.empty() ? RTLIL::State::Sx : bits.back());
+		bitvectype& bv = bits();
+		bv.resize(width, bv.empty() ? RTLIL::State::Sx : bv.back());
 	}
 
 	inline unsigned int hash() const {
 		unsigned int h = mkhash_init;
-		for (auto b : bits)
+
+		for (State b : *this)
 			h = mkhash(h, b);
 		return h;
 	}
@@ -760,8 +846,8 @@ struct RTLIL::SigChunk
 	int width, offset;
 
 	SigChunk() : wire(nullptr), width(0), offset(0) {}
-	SigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.bits), width(GetSize(data)), offset(0) {}
-	SigChunk(RTLIL::Const &&value) : wire(nullptr), data(std::move(value.bits)), width(GetSize(data)), offset(0) {}
+	SigChunk(const RTLIL::Const &value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}
+	SigChunk(RTLIL::Const &&value) : wire(nullptr), data(value.to_bits()), width(GetSize(data)), offset(0) {}
 	SigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}
 	SigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}
 	SigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}

yowasp_yosys/share/include/kernel/yosys_common.h

@@ -62,6 +62,9 @@
          defines the Yosys Makefile would set for your build configuration.
 #endif
 
+#define FRIEND_TEST(test_case_name, test_name) \
+  friend class test_case_name##_##test_name##_Test
+
 #ifdef YOSYS_ENABLE_TCL
 #  include <tcl.h>
 #  ifdef YOSYS_MXE_HACKS

yowasp_yosys/share/include/passes/fsm/fsmdata.h

@@ -48,8 +48,8 @@ struct FsmData
 		cell->parameters[ID::STATE_TABLE] = RTLIL::Const();
 
 		for (int i = 0; i < int(state_table.size()); i++) {
-			std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits;
-			std::vector<RTLIL::State> &bits_state = state_table[i].bits;
+			std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits();
+			std::vector<RTLIL::State> &bits_state = state_table[i].bits();
 			bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());
 		}
 
@@ -57,16 +57,16 @@ struct FsmData
 		cell->parameters[ID::TRANS_TABLE] = RTLIL::Const();
 		for (int i = 0; i < int(transition_table.size()); i++)
 		{
-			std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits;
+			std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits();
 			transition_t &tr = transition_table[i];
 
 			RTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2);
 			RTLIL::Const const_state_out = RTLIL::Const(tr.state_out, state_num_log2);
-			std::vector<RTLIL::State> &bits_state_in = const_state_in.bits;
-			std::vector<RTLIL::State> &bits_state_out = const_state_out.bits;
+			std::vector<RTLIL::State> &bits_state_in = const_state_in.bits();
+			std::vector<RTLIL::State> &bits_state_out = const_state_out.bits();
 
-			std::vector<RTLIL::State> &bits_ctrl_in = tr.ctrl_in.bits;
-			std::vector<RTLIL::State> &bits_ctrl_out = tr.ctrl_out.bits;
+			std::vector<RTLIL::State> &bits_ctrl_in = tr.ctrl_in.bits();
+			std::vector<RTLIL::State> &bits_ctrl_out = tr.ctrl_out.bits();
 
 			// append lsb first
 			bits_table.insert(bits_table.end(), bits_ctrl_out.begin(), bits_ctrl_out.end());
@@ -97,23 +97,23 @@ struct FsmData
 		for (int i = 0; i < state_num; i++) {
 			RTLIL::Const state_code;
 			int off_begin = i*state_bits, off_end = off_begin + state_bits;
-			state_code.bits.insert(state_code.bits.begin(), state_table.bits.begin()+off_begin, state_table.bits.begin()+off_end);
+			state_code.bits().insert(state_code.bits().begin(), state_table.begin()+off_begin, state_table.begin()+off_end);
 			this->state_table.push_back(state_code);
 		}
 
 		for (int i = 0; i < trans_num; i++)
 		{
-			auto off_ctrl_out = trans_table.bits.begin() + i*(num_inputs+num_outputs+2*state_num_log2);
+			auto off_ctrl_out = trans_table.begin() + i*(num_inputs+num_outputs+2*state_num_log2);
 			auto off_state_out = off_ctrl_out + num_outputs;
 			auto off_ctrl_in = off_state_out + state_num_log2;
 			auto off_state_in = off_ctrl_in + num_inputs;
 			auto off_end = off_state_in + state_num_log2;
 
 			RTLIL::Const state_in, state_out, ctrl_in, ctrl_out;
-			ctrl_out.bits.insert(state_in.bits.begin(), off_ctrl_out, off_state_out);
-			state_out.bits.insert(state_out.bits.begin(), off_state_out, off_ctrl_in);
-			ctrl_in.bits.insert(ctrl_in.bits.begin(), off_ctrl_in, off_state_in);
-			state_in.bits.insert(state_in.bits.begin(), off_state_in, off_end);
+			ctrl_out.bits().insert(ctrl_out.bits().begin(), off_ctrl_out, off_state_out);
+			state_out.bits().insert(state_out.bits().begin(), off_state_out, off_ctrl_in);
+			ctrl_in.bits().insert(ctrl_in.bits().begin(), off_ctrl_in, off_state_in);
+			state_in.bits().insert(state_in.bits().begin(), off_state_in, off_end);
 
 			transition_t tr;
 			tr.state_in = state_in.as_int();

yowasp_yosys/share/python3/sby_design.py

@@ -146,12 +146,12 @@ class SbyModule:
         path_iter = iter(path)
 
         mod = next(path_iter).translate(trans)
-        if self.name != mod:
+        if self.name.translate(trans) != mod:
             raise ValueError(f"{self.name} is not the first module in hierarchical path {pretty_path(path)}.")
 
         mod_hier = self
         for mod in path_iter:
-            mod_hier = next((v for k, v in mod_hier.submodules.items() if mod == k.translate(trans)), None)
+            mod_hier = next((v for k, v in mod_hier.submodules.items() if mod.translate(trans) == k.translate(trans)), None)
             if not mod_hier:
                 raise KeyError(f"Could not find {pretty_path(path)} in design hierarchy!")
 

yowasp_yosys/share/quicklogic/qlf_k6n10f/bram_types_sim.v

@@ -1,5 +1,5 @@
 // **AUTOGENERATED FILE** **DO NOT EDIT**
-// Generated by ../yosys-src/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py at 2024-10-09 11:26:56.850043+00:00
+// Generated by ../yosys-src/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py at 2024-11-06 01:15:23.931694+00:00
 `timescale 1ns /10ps
 
 module TDP36K_BRAM_A_X1_B_X1_nonsplit (