yowasp-yosys 0.45.0.0.post775__py3-none-any.whl → 0.47.0.0.post805__py3-none-any.whl

yowasp_yosys/share/gowin/cells_sim.v

@@ -1966,5 +1966,103 @@ output CLKOUT;
 parameter DCS_MODE = "RISING";
 endmodule
 
+(* blackbox *)
+module EMCU (
+  input          FCLK,
+  input          PORESETN,
+  input          SYSRESETN,
+  input          RTCSRCCLK,
+  output  [15:0] IOEXPOUTPUTO,
+  output  [15:0] IOEXPOUTPUTENO,
+  input   [15:0] IOEXPINPUTI,
+  output         UART0TXDO,
+  output         UART1TXDO,
+  output         UART0BAUDTICK,
+  output         UART1BAUDTICK,
+  input          UART0RXDI,
+  input          UART1RXDI,
+  output         INTMONITOR,
+  output         MTXHRESETN,
+  output  [12:0] SRAM0ADDR,
+  output   [3:0] SRAM0WREN,
+  output  [31:0] SRAM0WDATA,
+  output         SRAM0CS,
+  input   [31:0] SRAM0RDATA,
+  output         TARGFLASH0HSEL,
+  output  [28:0] TARGFLASH0HADDR,
+  output   [1:0] TARGFLASH0HTRANS,
+  output   [2:0] TARGFLASH0HSIZE,
+  output   [2:0] TARGFLASH0HBURST,
+  output         TARGFLASH0HREADYMUX,
+  input   [31:0] TARGFLASH0HRDATA,
+  input    [2:0] TARGFLASH0HRUSER,
+  input          TARGFLASH0HRESP,
+  input          TARGFLASH0EXRESP,
+  input          TARGFLASH0HREADYOUT,
+  output         TARGEXP0HSEL,
+  output  [31:0] TARGEXP0HADDR,
+  output   [1:0] TARGEXP0HTRANS,
+  output         TARGEXP0HWRITE,
+  output   [2:0] TARGEXP0HSIZE,
+  output   [2:0] TARGEXP0HBURST,
+  output   [3:0] TARGEXP0HPROT,
+  output   [1:0] TARGEXP0MEMATTR,
+  output         TARGEXP0EXREQ,
+  output   [3:0] TARGEXP0HMASTER,
+  output  [31:0] TARGEXP0HWDATA,
+  output         TARGEXP0HMASTLOCK,
+  output         TARGEXP0HREADYMUX,
+  output         TARGEXP0HAUSER,
+  output   [3:0] TARGEXP0HWUSER,
+  input   [31:0] TARGEXP0HRDATA,
+  input          TARGEXP0HREADYOUT,
+  input          TARGEXP0HRESP,
+  input          TARGEXP0EXRESP,
+  input    [2:0] TARGEXP0HRUSER,
+  output  [31:0] INITEXP0HRDATA,
+  output         INITEXP0HREADY,
+  output         INITEXP0HRESP,
+  output         INITEXP0EXRESP,
+  output   [2:0] INITEXP0HRUSER,
+  input          INITEXP0HSEL,
+  input   [31:0] INITEXP0HADDR,
+  input    [1:0] INITEXP0HTRANS,
+  input          INITEXP0HWRITE,
+  input    [2:0] INITEXP0HSIZE,
+  input    [2:0] INITEXP0HBURST,
+  input    [3:0] INITEXP0HPROT,
+  input    [1:0] INITEXP0MEMATTR,
+  input          INITEXP0EXREQ,
+  input    [3:0] INITEXP0HMASTER,
+  input   [31:0] INITEXP0HWDATA,
+  input          INITEXP0HMASTLOCK,
+  input          INITEXP0HAUSER,
+  input    [3:0] INITEXP0HWUSER,
+  output   [3:0] APBTARGEXP2PSTRB,
+  output   [2:0] APBTARGEXP2PPROT,
+  output         APBTARGEXP2PSEL,
+  output         APBTARGEXP2PENABLE,
+  output  [11:0] APBTARGEXP2PADDR,
+  output         APBTARGEXP2PWRITE,
+  output  [31:0] APBTARGEXP2PWDATA,
+  input   [31:0] APBTARGEXP2PRDATA,
+  input          APBTARGEXP2PREADY,
+  input          APBTARGEXP2PSLVERR,
+  input    [3:0] MTXREMAP,
+  output         DAPTDO,
+  output         DAPJTAGNSW,
+  output         DAPNTDOEN,
+  input          DAPSWDITMS,
+  input          DAPTDI,
+  input          DAPNTRST,
+  input          DAPSWCLKTCK,
+  output   [3:0] TPIUTRACEDATA,
+  output         TPIUTRACECLK,
+  input    [4:0] GPINT,
+  input          FLASHERR,
+  input          FLASHINT
+
+ );
+endmodule
 
 

yowasp_yosys/share/gowin/cells_xtra.v

@@ -1699,9 +1699,6 @@ input CLKIN, CE;
 output CLKOUT, CLKOUTN;
 endmodule
 
-module EMCU (...);
-endmodule
-
 module FLASH64K (...);
 input[4:0]XADR;
 input[5:0]YADR;

yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h

@@ -1127,7 +1127,7 @@ struct fmt_part {
 			}
 
 			case UNICHAR: {
-				uint32_t codepoint = val.template get<uint32_t>();
+				uint32_t codepoint = val.template zcast<32>().template get<uint32_t>();
 				if (codepoint >= 0x10000)
 					buf += (char)(0xf0 |  (codepoint >> 18));
 				else if (codepoint >= 0x800)

yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h

@@ -50,9 +50,13 @@ class vcd_writer {
 
 	void emit_scope(const std::vector<std::string> &scope) {
 		assert(!streaming);
-		while (current_scope.size() > scope.size() ||
-		       (current_scope.size() > 0 &&
-			current_scope[current_scope.size() - 1] != scope[current_scope.size() - 1])) {
+		size_t same_scope_count = 0;
+		while ((same_scope_count < current_scope.size()) &&
+			   (same_scope_count < scope.size()) &&
+			   (current_scope[same_scope_count] == scope[same_scope_count])) {
+			same_scope_count++;
+		}
+		while (current_scope.size() > same_scope_count) {
 			buffer += "$upscope $end\n";
 			current_scope.pop_back();
 		}
@@ -123,6 +127,8 @@ class vcd_writer {
 			bool bit_curr = var.curr[bit / (8 * sizeof(chunk_t))] & (1 << (bit % (8 * sizeof(chunk_t))));
 			buffer += (bit_curr ? '1' : '0');
 		}
+		if (var.width == 0)
+			buffer += '0';
 		buffer += ' ';
 		emit_ident(var.ident);
 		buffer += '\n';

yowasp_yosys/share/include/frontends/ast/ast.h

@@ -410,6 +410,9 @@ namespace AST
 	extern void (*set_line_num)(int);
 	extern int (*get_line_num)();
 
+	// for stats
+	unsigned long long astnode_count();
+
 	// set set_line_num and get_line_num to internal dummy functions (done by simplify() and AstModule::derive
 	// to control the filename and linenum properties of new nodes not generated by a frontend parser)
 	void use_internal_line_num();

yowasp_yosys/share/include/kernel/bitpattern.h

@@ -80,7 +80,7 @@ struct BitPatternPool
 	bits_t sig2bits(RTLIL::SigSpec sig)
 	{
 		bits_t bits;
-		bits.bitdata = sig.as_const().bits;
+		bits.bitdata = sig.as_const().bits();
 		for (auto &b : bits.bitdata)
 			if (b > RTLIL::State::S1)
 				b = RTLIL::State::Sa;

yowasp_yosys/share/include/kernel/celltypes.h

@@ -29,6 +29,8 @@ struct CellType
 	RTLIL::IdString type;
 	pool<RTLIL::IdString> inputs, outputs;
 	bool is_evaluable;
+	bool is_combinatorial;
+	bool is_synthesizable;
 };
 
 struct CellTypes
@@ -56,9 +58,9 @@ struct CellTypes
 		setup_stdcells_mem();
 	}
 
-	void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false)
+	void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false)
 	{
-		CellType ct = {type, inputs, outputs, is_evaluable};
+		CellType ct = {type, inputs, outputs, is_evaluable, is_combinatorial, is_synthesizable};
 		cell_types[ct.type] = ct;
 	}
 
@@ -114,7 +116,7 @@ struct CellTypes
 	void setup_internals_eval()
 	{
 		std::vector<RTLIL::IdString> unary_ops = {
-			ID($not), ID($pos), ID($neg),
+			ID($not), ID($pos), ID($buf), ID($neg),
 			ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
 			ID($logic_not), ID($slice), ID($lut), ID($sop)
 		};
@@ -325,7 +327,7 @@ struct CellTypes
 
 	static RTLIL::Const eval_not(RTLIL::Const v)
 	{
-		for (auto &bit : v.bits)
+		for (auto &bit : v.bits())
 			if (bit == State::S0) bit = State::S1;
 			else if (bit == State::S1) bit = State::S0;
 		return v;
@@ -339,7 +341,7 @@ struct CellTypes
 			type = ID($shl);
 
 		if (type != ID($sshr) && type != ID($sshl) && type != ID($shr) && type != ID($shl) && type != ID($shift) && type != ID($shiftx) &&
-				type != ID($pos) && type != ID($neg) && type != ID($not)) {
+				type != ID($pos) && type != ID($buf) && type != ID($neg) && type != ID($not)) {
 			if (!signed1 || !signed2)
 				signed1 = false, signed2 = false;
 		}
@@ -384,7 +386,7 @@ struct CellTypes
 		HANDLE_CELL_TYPE(neg)
 #undef HANDLE_CELL_TYPE
 
-		if (type == ID($_BUF_))
+		if (type.in(ID($_BUF_), ID($buf)))
 			return arg1;
 		if (type == ID($_NOT_))
 			return eval_not(arg1);
@@ -419,13 +421,13 @@ struct CellTypes
 			RTLIL::Const ret;
 			int width = cell->parameters.at(ID::Y_WIDTH).as_int();
 			int offset = cell->parameters.at(ID::OFFSET).as_int();
-			ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);
+			ret.bits().insert(ret.bits().end(), arg1.begin()+offset, arg1.begin()+offset+width);
 			return ret;
 		}
 
 		if (cell->type == ID($concat)) {
 			RTLIL::Const ret = arg1;
-			ret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end());
+			ret.bits().insert(ret.bits().end(), arg2.begin(), arg2.end());
 			return ret;
 		}
 
@@ -448,7 +450,7 @@ struct CellTypes
 		{
 			int width = cell->parameters.at(ID::WIDTH).as_int();
 
-			std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits;
+			std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).to_bits();
 			while (GetSize(t) < (1 << width))
 				t.push_back(State::S0);
 			t.resize(1 << width);
@@ -460,7 +462,7 @@ struct CellTypes
 		{
 			int width = cell->parameters.at(ID::WIDTH).as_int();
 			int depth = cell->parameters.at(ID::DEPTH).as_int();
-			std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits;
+			std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).to_bits();
 
 			while (GetSize(t) < width*depth*2)
 				t.push_back(State::S0);
@@ -473,7 +475,7 @@ struct CellTypes
 				bool match_x = true;
 
 				for (int j = 0; j < width; j++) {
-					RTLIL::State a = arg1.bits.at(j);
+					RTLIL::State a = arg1.at(j);
 					if (t.at(2*width*i + 2*j + 0) == State::S1) {
 						if (a == State::S1) match_x = false;
 						if (a != State::S0) match = false;
@@ -513,7 +515,7 @@ struct CellTypes
 		if (cell->type == ID($_OAI3_))
 			return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));
 
-		log_assert(arg3.bits.size() == 0);
+		log_assert(arg3.size() == 0);
 		return eval(cell, arg1, arg2, errp);
 	}
 
@@ -524,7 +526,7 @@ struct CellTypes
 		if (cell->type == ID($_OAI4_))
 			return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));
 
-		log_assert(arg4.bits.size() == 0);
+		log_assert(arg4.size() == 0);
 		return eval(cell, arg1, arg2, arg3, errp);
 	}
 };

yowasp_yosys/share/include/kernel/consteval.h

@@ -76,7 +76,7 @@ struct ConstEval
 #ifndef NDEBUG
 		RTLIL::SigSpec current_val = values_map(sig);
 		for (int i = 0; i < GetSize(current_val); i++)
-			log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);
+			log_assert(current_val[i].wire != NULL || current_val[i] == value[i]);
 #endif
 		values_map.add(sig, RTLIL::SigSpec(value));
 	}
@@ -115,7 +115,7 @@ struct ConstEval
 
 				for (int i = 0; i < GetSize(coval); i++) {
 					carry = (sig_g[i] == State::S1) || (sig_p[i] == RTLIL::S1 && carry);
-					coval.bits[i] = carry ? State::S1 : State::S0;
+					coval.bits()[i] = carry ? State::S1 : State::S0;
 				}
 
 				set(sig_co, coval);
@@ -153,7 +153,7 @@ struct ConstEval
 
 			for (int i = 0; i < sig_s.size(); i++)
 			{
-				RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0);
+				RTLIL::State s_bit = sig_s.extract(i, 1).as_const().at(0);
 				RTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size());
 
 				if (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)
@@ -180,10 +180,10 @@ struct ConstEval
 
 			if (y_values.size() > 1)
 			{
-				std::vector<RTLIL::State> master_bits = y_values.at(0).bits;
+				std::vector<RTLIL::State> master_bits = y_values.at(0).to_bits();
 
 				for (size_t i = 1; i < y_values.size(); i++) {
-					std::vector<RTLIL::State> &slave_bits = y_values.at(i).bits;
+					std::vector<RTLIL::State> slave_bits = y_values.at(i).to_bits();
 					log_assert(master_bits.size() == slave_bits.size());
 					for (size_t j = 0; j < master_bits.size(); j++)
 						if (master_bits[j] != slave_bits[j])
@@ -248,8 +248,8 @@ struct ConstEval
 			RTLIL::Const val_x = const_or(t2, t3, false, false, width);
 
 			for (int i = 0; i < GetSize(val_y); i++)
-				if (val_y.bits[i] == RTLIL::Sx)
-					val_x.bits[i] = RTLIL::Sx;
+				if (val_y[i] == RTLIL::Sx)
+					val_x.bits()[i] = RTLIL::Sx;
 
 			set(sig_y, val_y);
 			set(sig_x, val_x);

yowasp_yosys/share/include/kernel/constids.inc

@@ -43,6 +43,7 @@ X(CE_OVER_SRST)
 X(CFG_ABITS)
 X(CFG_DBITS)
 X(CFG_INIT)
+X(chain)
 X(CI)
 X(CLK)
 X(clkbuf_driver)
@@ -153,7 +154,6 @@ X(PORTID)
 X(PRIORITY)
 X(PRIORITY_MASK)
 X(Q)
-X(qwp_position)
 X(R)
 X(ram_block)
 X(ram_style)