yowasp-yosys 0.45.0.0.post775__py3-none-any.whl → 0.46.0.0.post790__py3-none-any.whl

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Files changed (28) hide show
  1. yowasp_yosys/share/gowin/cells_sim.v +98 -0
  2. yowasp_yosys/share/gowin/cells_xtra.v +0 -3
  3. yowasp_yosys/share/include/frontends/ast/ast.h +3 -0
  4. yowasp_yosys/share/include/kernel/celltypes.h +3 -3
  5. yowasp_yosys/share/include/kernel/constids.inc +1 -0
  6. yowasp_yosys/share/include/kernel/drivertools.h +1332 -0
  7. yowasp_yosys/share/include/kernel/ff.h +4 -2
  8. yowasp_yosys/share/include/kernel/hashlib.h +32 -0
  9. yowasp_yosys/share/include/kernel/log.h +2 -0
  10. yowasp_yosys/share/include/kernel/mem.h +109 -0
  11. yowasp_yosys/share/include/kernel/rtlil.h +24 -1
  12. yowasp_yosys/share/include/kernel/sexpr.h +122 -0
  13. yowasp_yosys/share/include/kernel/utils.h +9 -0
  14. yowasp_yosys/share/include/kernel/yosys_common.h +2 -0
  15. yowasp_yosys/share/python3/sby_core.py +1 -0
  16. yowasp_yosys/share/python3/sby_design.py +18 -24
  17. yowasp_yosys/share/python3/sby_engine_aiger.py +39 -3
  18. yowasp_yosys/share/python3/sby_engine_smtbmc.py +16 -8
  19. yowasp_yosys/share/quicklogic/qlf_k6n10f/bram_types_sim.v +1 -1
  20. yowasp_yosys/share/simlib.v +21 -1
  21. yowasp_yosys/share/techmap.v +2 -1
  22. yowasp_yosys/smtbmc.py +19 -8
  23. yowasp_yosys/yosys.wasm +0 -0
  24. {yowasp_yosys-0.45.0.0.post775.dist-info → yowasp_yosys-0.46.0.0.post790.dist-info}/METADATA +1 -1
  25. {yowasp_yosys-0.45.0.0.post775.dist-info → yowasp_yosys-0.46.0.0.post790.dist-info}/RECORD +28 -26
  26. {yowasp_yosys-0.45.0.0.post775.dist-info → yowasp_yosys-0.46.0.0.post790.dist-info}/WHEEL +0 -0
  27. {yowasp_yosys-0.45.0.0.post775.dist-info → yowasp_yosys-0.46.0.0.post790.dist-info}/entry_points.txt +0 -0
  28. {yowasp_yosys-0.45.0.0.post775.dist-info → yowasp_yosys-0.46.0.0.post790.dist-info}/top_level.txt +0 -0
@@ -1966,5 +1966,103 @@ output CLKOUT;
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  parameter DCS_MODE = "RISING";
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  endmodule
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+ (* blackbox *)
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+ module EMCU (
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+ input FCLK,
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+ input PORESETN,
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+ input SYSRESETN,
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+ input RTCSRCCLK,
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+ output [15:0] IOEXPOUTPUTO,
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+ output [15:0] IOEXPOUTPUTENO,
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+ input [15:0] IOEXPINPUTI,
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+ output UART0TXDO,
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+ output UART1TXDO,
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+ output UART0BAUDTICK,
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+ output UART1BAUDTICK,
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+ input UART0RXDI,
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+ input UART1RXDI,
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+ output INTMONITOR,
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+ output MTXHRESETN,
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+ output [12:0] SRAM0ADDR,
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+ output [3:0] SRAM0WREN,
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+ output [31:0] SRAM0WDATA,
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+ output SRAM0CS,
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+ input [31:0] SRAM0RDATA,
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+ output TARGFLASH0HSEL,
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+ output [28:0] TARGFLASH0HADDR,
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+ output [1:0] TARGFLASH0HTRANS,
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+ output [2:0] TARGFLASH0HSIZE,
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+ output [2:0] TARGFLASH0HBURST,
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+ output TARGFLASH0HREADYMUX,
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+ input [31:0] TARGFLASH0HRDATA,
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+ input [2:0] TARGFLASH0HRUSER,
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+ input TARGFLASH0HRESP,
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+ input TARGFLASH0EXRESP,
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+ input TARGFLASH0HREADYOUT,
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+ output TARGEXP0HSEL,
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+ output [31:0] TARGEXP0HADDR,
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+ output [1:0] TARGEXP0HTRANS,
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+ output TARGEXP0HWRITE,
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+ output [2:0] TARGEXP0HSIZE,
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+ output [2:0] TARGEXP0HBURST,
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+ output [3:0] TARGEXP0HPROT,
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+ output [1:0] TARGEXP0MEMATTR,
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+ output TARGEXP0EXREQ,
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+ output [3:0] TARGEXP0HMASTER,
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+ output [31:0] TARGEXP0HWDATA,
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+ output TARGEXP0HMASTLOCK,
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+ output TARGEXP0HREADYMUX,
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+ output TARGEXP0HAUSER,
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+ output [3:0] TARGEXP0HWUSER,
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+ input [31:0] TARGEXP0HRDATA,
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+ input TARGEXP0HREADYOUT,
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+ input TARGEXP0HRESP,
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+ input TARGEXP0EXRESP,
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+ input [2:0] TARGEXP0HRUSER,
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+ output [31:0] INITEXP0HRDATA,
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+ output INITEXP0HREADY,
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+ output INITEXP0HRESP,
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+ output INITEXP0EXRESP,
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+ output [2:0] INITEXP0HRUSER,
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+ input INITEXP0HSEL,
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+ input [31:0] INITEXP0HADDR,
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+ input [1:0] INITEXP0HTRANS,
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+ input INITEXP0HWRITE,
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+ input [2:0] INITEXP0HSIZE,
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+ input [2:0] INITEXP0HBURST,
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+ input [3:0] INITEXP0HPROT,
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+ input [1:0] INITEXP0MEMATTR,
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+ input INITEXP0EXREQ,
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+ input [3:0] INITEXP0HMASTER,
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+ input [31:0] INITEXP0HWDATA,
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+ input INITEXP0HMASTLOCK,
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+ input INITEXP0HAUSER,
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+ input [3:0] INITEXP0HWUSER,
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+ output [3:0] APBTARGEXP2PSTRB,
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+ output [2:0] APBTARGEXP2PPROT,
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+ output APBTARGEXP2PSEL,
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+ output APBTARGEXP2PENABLE,
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+ output [11:0] APBTARGEXP2PADDR,
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+ output APBTARGEXP2PWRITE,
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+ output [31:0] APBTARGEXP2PWDATA,
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+ input [31:0] APBTARGEXP2PRDATA,
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+ input APBTARGEXP2PREADY,
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+ input APBTARGEXP2PSLVERR,
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+ input [3:0] MTXREMAP,
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+ output DAPTDO,
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+ output DAPJTAGNSW,
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+ output DAPNTDOEN,
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+ input DAPSWDITMS,
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+ input DAPTDI,
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+ input DAPNTRST,
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+ input DAPSWCLKTCK,
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+ output [3:0] TPIUTRACEDATA,
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+ output TPIUTRACECLK,
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+ input [4:0] GPINT,
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+ input FLASHERR,
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+ input FLASHINT
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+
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+ );
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+ endmodule
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@@ -1699,9 +1699,6 @@ input CLKIN, CE;
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  output CLKOUT, CLKOUTN;
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  endmodule
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- module EMCU (...);
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- endmodule
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-
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  module FLASH64K (...);
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  input[4:0]XADR;
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  input[5:0]YADR;
@@ -410,6 +410,9 @@ namespace AST
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  extern void (*set_line_num)(int);
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  extern int (*get_line_num)();
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+ // for stats
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+ unsigned long long astnode_count();
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+
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  // set set_line_num and get_line_num to internal dummy functions (done by simplify() and AstModule::derive
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  // to control the filename and linenum properties of new nodes not generated by a frontend parser)
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  void use_internal_line_num();
@@ -114,7 +114,7 @@ struct CellTypes
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  void setup_internals_eval()
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  {
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  std::vector<RTLIL::IdString> unary_ops = {
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- ID($not), ID($pos), ID($neg),
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+ ID($not), ID($pos), ID($buf), ID($neg),
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  ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
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  ID($logic_not), ID($slice), ID($lut), ID($sop)
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  };
@@ -339,7 +339,7 @@ struct CellTypes
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  type = ID($shl);
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341
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  if (type != ID($sshr) && type != ID($sshl) && type != ID($shr) && type != ID($shl) && type != ID($shift) && type != ID($shiftx) &&
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- type != ID($pos) && type != ID($neg) && type != ID($not)) {
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+ type != ID($pos) && type != ID($buf) && type != ID($neg) && type != ID($not)) {
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  if (!signed1 || !signed2)
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  signed1 = false, signed2 = false;
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  }
@@ -384,7 +384,7 @@ struct CellTypes
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  HANDLE_CELL_TYPE(neg)
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  #undef HANDLE_CELL_TYPE
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387
- if (type == ID($_BUF_))
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+ if (type.in(ID($_BUF_), ID($buf)))
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  return arg1;
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  if (type == ID($_NOT_))
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  return eval_not(arg1);
@@ -43,6 +43,7 @@ X(CE_OVER_SRST)
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  X(CFG_ABITS)
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  X(CFG_DBITS)
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  X(CFG_INIT)
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+ X(chain)
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  X(CI)
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  X(CLK)
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  X(clkbuf_driver)